Digital Design
With an Introduction to the Verilog HDL, VHDL, and
SystemVerilog
6th Edition
Chapter 04
Combinational Logic
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Figure 4.1
Block diagram of combinational circuit.
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Figure 4.2
Logic diagram for analysis example.
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Table 4.1
Truth Table for the Logic Diagram of Fig. 4.2.
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Figure PE4.1
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Table 4.2
Truth Table for Code Conversion Example.
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Figure 4.3
Maps for BCD-to-excess-3 code converter.
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Figure 4.4
Logic diagram for BCD-to-excess-3 code converter.
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Table 4.3
Half Adder.
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Figure 4.5
Implementation of half adder.
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Table 4.4
Full Adder.
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Figure 4.6
K-Maps for full adder.
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Figure 4.7
Implementation of full adder in sum-of-products form.
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Figure 4.8
Implementation of full adder with two half adders and an
OR gate.
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Figure 4.9
Four-bit adder.
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Binary Adder
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Figure 4.10
Full adder with P and G shown.
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Figure 4.11
Logic diagram of carry lookahead generator.
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Figure 4.12
Four-bit adder with carry lookahead.
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Figure 4.13
Four-bit adder–subtractor (with overflow detection).
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Table 4.5
Derivation of BCD Adder.
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Figure 4.14
Block diagram of a BCD adder.
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Figure 4.15
Two-bit by two-bit binary multiplier.
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Figure 4.16
Four-bit by three-bit binary multiplier.
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Figure 4.17
Four-bit magnitude comparator.
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Figure 4.18
Three-to-eight-line decoder.
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Table 4.6
Truth Table of a Three-to-Eight-Line Decoder.
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Figure 4.19
Two-to-four-line decoder with enable input.
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Figure 4.20
4 x 16 decoder constructed with two 3 x 8 decoders.
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Figure PE4.8
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Figure 4.21
Implementation of a full adder with a decoder.
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Table 4.7
Truth Table of an Octal-to-Binary Encoder.
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Table 4.8
Truth Table of a Priority Encoder.
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Figure 4.22
Maps for a priority encoder.
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Figure 4.23
Four-input priority encoder.
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Figure 4.24
Two-to-one-line multiplexer.
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Figure 4.25
Four-to-one-line multiplexer.
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Figure 4.26
Quadruple two-to-one-line multiplexer.
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Figure 4.27
Implementing a Boolean function with a multiplexer.
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Figure 4.28
Implementing a four-input function with a multiplexer.
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Figure PE4.9
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Figure 4.29
Graphic symbol for a three-state buffer.
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Figure 4.30
Multiplexers with three-state gates.
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Figure 4.31
Relationship of Verilog constructs to truth tables, Boolean
equations, and schematics.
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Figure 4.32
Relationship of VHDL constructs to truth tables, Boolean
equations, and schematics three-state gates.
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Table 4.9
Truth Table for Predefined Primitive Gates.
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Figure 4.33
Design hierarchy of an 8-bit ripple-carry adder. For
simplicity, some blocks are omitted where they replicate
what is already shown.
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Figure 4.34
Decomposition of an 8-bit ripple carry adder into a chain of two 4-bit
adders;9 each 4-bit adder consists of a chain of four full adders. The full
adders are composed of half adders and one OR gate; the half adders
are composed of logic gates.
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Figure 4.35
Three-state gates.
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Figure 4.36
Two-to-one-line multiplexer with three-state buffers.
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Table 4.10
Some Verilog Operators.
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Table 4.11a
SystemVerilog Assignment Operators15.
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Table 4.11b
SystemVerilog Increment/Decrement Operators.
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Table 4.12
Predefined VHDL Data Types.
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Table 4.13
VHDL Operators.
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Figure 4.37
Interaction between testbench and Verilog design unit.
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Figure 4.38
Interaction between testbench and VHDL design unit.
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Figure 4.39
Circuit for event-driven simulation.
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Figure 4.40
Representation of event-driven simulation (with zero
delay).
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Figure 4.41
Representation of event-driven simulation (with
propagation delay).
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FIGURE P4.1
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FIGURE P4.2
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FIGURE P4.9
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FIGURE P4.16
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