Combinational

Circuit

Adders Subtractor
Decoder-Encoder
Multiplexers-
Demultiplexers
Comparator
Parity IC Family
Combinational
Circuits
• output depends only on the present input
• The combinational circuit do not use any memory.
• The previous state of input does not have any effect on the present state of the
circuit.
 Half
Adder
A combinational logic circuit with two inputs and two
outputs. The half adder circuit add two single bit Cary
number
This circuit has two outputs carry and sum.

S(A, B) = ∑m (1, 2)
CY(A, B) = ∑m (3)
 Full Adder (1-bit
Adder)
A combinational logic circuit with 3 inputs and 2 outputs.
The Full adder circuit add 3 single bit Cary number This
circuit has two outputs carry and sum.

ABC  ABC  ABC  ABC A(BC

Sum(A, B,C) = ∑m (1, 2, 4,
7)  BC)  A(BC  BC)
Cout(A, B, C) = ∑m (3,5,6,7) A(B  C)  A(BC)
Let B  C  D
AD  AD
AD
ABC
For Cout

ABC  ABC  ABC  ABC

C( AB  AB)  AB(C  C) ( A 
B)C  AB

Cout=AB+BC+AC
Full Adder using Half
Adder
FA

Carry=AB+
Sum= A⊕B⊕C

(A⊕B)C

HA

Carry=AB
Sum= A⊕B
 Half
Subtractor
Combinational circuit perform binary
Subtraction
Accepts 2 input and Two output Difference
and Borrow

D(A, B) = ∑m (1, 2)
Br(A, B) = ∑m (1)
 Full
Subtractor
Performs subtraction of 3 bits
This circuit has three inputs and two outputs.
The three inputs A, B and C, denote the minuend, subtrahend, and previous borrow, respectively.
The two outputs, D and Bout
Sum(A, B,C) = ∑m (1, 2, 4, 7)
Bout(A, B,C) = ∑m (1,2,3,7)
Bout = A’B’C + A’BC’ + A’BC +
ABC
= C(AB + A’B’) + A’B(C + C’)
= C( A XNOR B) + A’B
= C (A XOR B)’ + A’B
Full Subtractor using Half
FS
Subtractor
Carry=A’B+
Sum= A⊕B⊕C

(A⊕B)’C

HS

Carry=A’B
Sum= A⊕B
Design a 3 input digital circuit produces high output for two or more binary input high

A B C Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
Design a 3 input digital circuit produces high output for ODD decimal equivalent

A B C Y
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
 1-BIT Magnitude
Comparator
GT
A 1-Bit
Magnitude
B Comparator EQ
LT
EQ
GT L
T

GT=AB’
EQ=A’B’+AB
LT=A’B
2-BIT Magnitude
Comparator
Multiplex
er
 A combinational circuit has maximum of 2 data inputs, ‘n’ selection lines and
n

single output line.

 One of these data inputs will be connected to the output based on the values of
selection lines

 Size of multiplexer is 2𝑛:1

 It is a data selector device

I0 0
Y =S’I0 + SI1
2:1 Multiplexer
I1 1

S
 4:1
Multiplexer

Selection Lines Output

S1 S0 Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3
 Expression implementation with
Multiplexer
Y(A, B,C) = ∑m (1, 3, 5, 6) implement with 4:1 multiplexer Y(A, B,C) = ∑m (1, 2, 4, 5) implement with 4:1 multiplexer

Y  ABC  ABC  ABC  ABC Y  ABC  ABC  ABC  ABC

Any 2 input (AB/BC/AC) select line Any 2 input (AB/BC/AC) select line

0 C
1
A C’
A 1
’ 0

Rearrange equation with selection line Rearrange equation with selection line

Y  0.(BC)  BC( A  A)  ABC  Y  ABC  ABC  AB(C  C)  AB.0

ABC
I0 I1 I2 I3
I0 I1 I2 I3
 Logic Gate implementation with 2:1 Multiplexer
AND GATE OR GATE

NOR GATE
NAND GATE
 Logic Gate implementation with 2:1 Multiplexer
XOR GATE XNOR GATE

NOT GATE
Full Adder implementation with 4:1
S(A, B, C ) = ∑(1, 2, 4, 7) Multiplexer
in
= m1 + m2 + m4 +m7
= A’B’Cin + A’BC’in + AB’C’in + ABCin
= A.(B’C’in) + A’.(B’Cin) + A’.(BC’in) + A.(B’C’in) (1)

4:1 Mux equation Y = I0S’1S’0 + I1S’1S0 + I2S1S’0 + I3S1S0 (2)

Compare (1) and (2) with S1 = B, S0 = Cin I0 = A, I1 = A’, I2 =

A’, I3 = A.

Cout(A, B, Cin) = ∑(3, 5, 6, 7)

= m3 + m5 + m6 + m7
= A’BCin + AB’Cin + ABC’in + ABCin
= (A’ + A) BCin + AB’Cin + ABC’in +
[Link]’C’in (3)
= 0.(B’C’in) + A.(B’Cin) + A.(BC’in) + 1.(BCin)
4:1 Mux equation Y = I0S’1S’0 + I1S’1S0 + I2S1S’0 + I3S1S0
(4)

Comparing equation (1) and (3) with S1 = B, S0 = Cin.

 8:1
Multiplexer S2 S1 S0 Out
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7

Out=S2’S1’S0’I0 + S2’S1’S0I1+ S2’S1S0’I2+ S2’S1S0I3

S2S1’S0’I4+ S2S1’S0I5+ S2S1S0’I6+ S2S1S0I7
Full adder using
8:1 Mux
S(A, B, Cin) = ∑(1, 2, 4, 7)
Cout(A, B, Cin) = ∑(3, 5, 6, 7)

High input for present minterm, low input

for minterm not present
4:1 Mux using 2:1 8:1 Mux using 4:1 and
2:1 Mux
0 0
Mux
S1 (MSB) S0(LSB) Out
I0
0 1 I1
1 0 12
1 1 I3
Demultiple
xer
switch one common input line to one of several output line based on select input
It is data distributor
Size of demux 1:2𝑛 Example 1:4, 1:8, 1:16….. Demultiplexer
Selection Inputs Outputs

S1 S0 Y3 Y2 Y1 Y0
0 0 0 0 0 I
0 1 0 0 I 0
1 0 0 I 0 0
1 1 I 0 0 0
Decod
n
One ofer
A combinational circuit that has ‘n’ input lines and maximum of 2 output lines.
these outputs will be active High based on the combination of inputs present, when the decoder is enabled.
The outputs of the decoder are min terms of ‘n’ input variables lines when it is enabled
Size of Decoder are 2:4, 3:8, 4:16….

A1 A0 Y3 Y2 Y1 Y0
0 0 0 0 0 1

0 1 0 0 1 0

1 0 0 1 0 0

1 1 1 0 0 0
 Full Adder using 3:8 Full Subtractor using 3:8
Decoder Decoder
S = A’B’C + A’BC’ + AB’C’ + ABC =
Σ(1,2,4,7) CY = A’BC +AB’C +ABC’+ABC= Σ (3, DIFFERENCE = A’B’C + A’BC’ + AB’C’ + ABC =
5, 6, 7) Σ(1,2,4,7) BORROW = A’B’C +A’BC’ +A’BC+ABC= Σ (1, 2,
3, 7)

Y
 3:8 decoder using 2:4
Decoder with Enable
decoder
One of outputs will be ‘1’ when enable, E is ‘1’

A2 A1 A0 HIGH OUTPUT
0 0 0 Y0
0 0 1 Y1
0 1 0 Y2
0 1 1 Y3
1 0 0 Y4
1 0 1 Y5
1 1 0 Y6
1 1 1 Y7
 4:16
A3 A2 A1 A0 HIGH OUTPUT
0 decoder
0 0 0 Y0
0 0 0 1 Y1
Y0
0 0 1 0 Y2
0 0 1 1 Y3 A3
0 1 0 0 Y4
0 1 0 1 Y5 A2
0 1 1 0 Y6
0
1
1
0
1
0
1
0
Y7
Y8
A1
4:16 Decoder
1 0 0 1 Y9
A0
1 0 1 0 Y10
1 0 1 1 Y11
1 1 0 0 Y12
1 1 0 1 Y13 Y15
1 1 1 0 Y14
EN
1 1 1 1 Y15
 4:16 decoder using 3:8
A3 A2 A1 A0 HIGH OUTPUT
0 0 0 decoder
0 Y0
0 0 0 1 Y1
0 0 1 0 Y2
0 0 1 1 Y3
0 1 0 0 Y4
0 1 0 1 Y5
0 1 1 0 Y6
0 1 1 1 Y7
1 0 0 0 Y8
1 0 0 1 Y9
1 0 1 0 Y10
1 0 1 1 Y11
1 1 0 0 Y12
1 1 0 1 Y13
1 1 1 0 Y14
1 1 1 1 Y15
 4:16 decoder using 2:4
A3 A2 A1 A0 HIGH OUTPUT
0 0 0 decoder
0 Y0
0 0 0 1 Y1
0 0 1 0 Y2
0 0 1 1 Y3
0 1 0 0 Y4
0 1 0 1 Y5
0 1 1 0 Y6
0 1 1 1 Y7
1 0 0 0 Y8
1 0 0 1 Y9
1 0 1 0 Y10
1 0 1 1 Y11
1 1 0 0 Y12
1 1 0 1 Y13
1 1 1 0 Y14
1 1 1 1 Y15
 4:2
Encoder
4-bit Ripple Carry
Adder
 4-bit Adder cum capable of both addition and subtraction of
binary numbers in one circuit

Subtractor K=0 Addition

K=1 Subtraction

For K=0: S=A+B For K=1: S=A-B

A(A3A2A1A0)=00102 and B(B3B2B1B0)=00113 A(A3A2A1A0)=00102 and B(B3B2B1B0)=00113
B0(exor)K=B0 and Cin=K=0 B0(exor)K=~B0, B1(exor)K=~B1, B2(exor)K=~B2,
First full adder=A0+B0+Cin=0+1+0,S0=1 C0=0 Second full B3(exor)K=~B3 and Cin=K=1
adder=A1+B1+C0=1+1+0,S1=0 C1=1 First full adder=A0+B0+Cin=0+0+1,S0=1 C0=0 Second full
Third full adder=A2+B2+C1=0+0+1=1,S2=1 adder=A1+B1+C0=1+0+1=0,S1=1 C1=0
C2=0 Fourth full Third full adder=A2+B2+C1=0+1+0=1,S2=1
adder=A3+B3+C2=0+0+0=0,S3=0 Cout=0 C2=0
S(S3S2S1S0) = 0101  5 Fourth full adder=A3+B3+C2=0+1+0=0,S3=1
 ity Generator
Par
Even Parity Generator

If odd number of ones present in the input, then Circuit Odd Parity Generator
If even number of ones present in the
even parity bit, P should be ‘1’ so that the resultant input, then odd parity bit, P should be
word contains even number of ones. ‘1’ so that the resultant word contains
odd number of ones
Binary Odd Parity
Binary Even Parity Input WXY bit P
Input WXY bit P
000 1
000 0
001 0
001 1
010 0
010 1
011 1
011 0
100 0
100 1
101 1
101 0
110 1
110 0 111 0
111 1
 Parity Checker
Circuit
Even parity checker checks error in the transmitted
data, which contains message bits along with
even parity.
 IC Families
Logic family are digital integrated circuit devices which are constructed with a combination of
electronic gates.
A family has its own power supply voltage and group potential; distinct logic levels.

•Diode Logic (DL) logic is implemented with the use of resistors and
•Resistor-Transistor Logic diodes. logic is implemented with the use of
(RTL) transistors and resistors logic is implemented with
•Diode-Transistor Logic the use of diodes and transistors. logic are
•(DTL)
Emitter Coupled Logic (ECL) implemented with transistors
logic are implemented with transistors
•Complementary
Transistor-Transistor
MetalLogic
Oxide Semiconductor Logic (CMOS) logic are implemented
(TTL)MOSFET
with
Fan out: It specifies the number of standard loads that the output of the gate can drive without affecting its normal
operation.
Fan in: This is the number of inputs of a logic gate.
Power Dissipation: This is the power supplied required to operate the gate.
Propagation delay Time delay between the occurrence of change in the logical level at the input and before it is reflected at
the output
Noise margin: This is the maximum noise voltage added to the input signal of digital circuit that does not cause an
undesirable change in the circuit output