SERDES

CONTENTS

1.Why do we need SerDes? 8. DFE

2. PLL 9. De-serializer
3. BGR 10. Clock
Generator
4. Serializer 11.Biasing
5. Driver 12.Advantages
6. Receiver 13.Applications
7. Termination
DEFINITION

 A SerDes, or serializer/de-serializer, is an
integrated circuit (IC or chip) transceiver
that converts parallel data to serial data
and vice versa.
 The transmitter section is a parallel-to-
serial converter, and the receiver section
is a serial-to-parallel converter.
 SerDes is a functional block that Serializes
and Deserializes digital data used in high-
speed chip-to-chip communication.
 A SerDes implementation
includes parallel-to-serial (serial-
to-parallel) data conversion,
impedance matching circuitry,
and clock data recovery
functionality.
 The primary role of SerDes is to
minimize the number of I/O
interconnects.
 Most SerDes devices support full-
duplex operations, meaning
that data conversion can take place
in both directions simultaneously.
 An IC can house multiple SerDes
devices, and a SerDes device can
house multiple lanes, with each lane
handling the input and output traffic
for a serial interface. Although SerDes
devices can vary, they generally
contain two functional blocks:
 1.Parallel in serial out(PISO)
 2.Serial in parallel out(SIPO)
 Parallel In Serial Out (PISO). The PISO is a parallel-to-
serial converter (serializer). It receives parallel data from the
local system as input, converts it to serial data and outputs it
as a single data stream.
 It has a set of data input lines, and input data latches.
 The simplest form of the PISO has a single shift register that
receives the parallel data once per parallel clock, and shifts it
out at the higher serial clock rate.
 Serial In Parallel Out (SIPO). The SIPO is a serial-
to-parallel converter (de-serializer). It receives serial
data as input, converts it to parallel data and outputs
it as a parallel data stream.
 It has a receive clock output, a set of data output lines
and output data latches. The receive clock may have
been recovered from the data by the serial clock
recovery technique.
Why Do We Need SerDes?

 Distributed data processing in ICs

need high speed data transfer
between the ICs. Parallel and
serial are the two options to
transfer data between chips.
 Parallel data transfer requires
multiple connections between ICs
compared to serial data transfer
that only needs one pair of
connection.
SERDES X4

 It consists of
1) One common
2) Four lanes
COMMON: It consists of a PLL, Biasing circuits
and buffer circuits where all the controlling of
the circuit happens here and the most important
circuit here is PLL as it generates clocks and
distributes it to two lanes one on the left and
other to the right, where those clocks will get
distributed to other lanes from these lanes, in
every lane we have a clock generator section to
receive these clock signals.
 COMMON:

 Biasing circuit sends signals to all lanes simultaneously where

we do have another biasing sections in every lane as it receives
the signals and distributes it to the lane as per the requirement.
 PLL

 The PLL is a critical part of the SerDes, responsible for

generating the clock signals required for high-speed data
transmission and regulating the phase connection between
these clocks.
 It is responsible for producing the clock signals that each
SerDes module requires and regulating the phase connection
between these clocks
 The PLL can be internal or external to the SerDes blocks, and
each block might have its own PLL, or the two blocks might
share the same PLL.
 The PLL may use an internal or
external phase-locked loop to
multiply the incoming parallel
clock up to the serial
frequency.
 In summary, the function of
the PLL in SerDes is to
generate the clock signals
required for high-speed data
transmission and to regulate
the phase connection between
 Band Gap Reference(BGR)

 In the context of Serializer/De-serializer (SerDes) circuits, a bandgap

reference (BGR) is a crucial component used to generate a stable and
accurate reference voltage.
 This reference voltage is essential for ensuring the proper operation of
various analog and mixed-signal circuits within the SerDes design.
 The bandgap reference is designed to produce a fixed voltage that
remains constant despite variations in power supply and temperature
changes, making it a valuable tool for maintaining the integrity of signals
within the SerDes system.
 The Bandgap Reference (BGR) circuit operates based on the generation of
two voltages, Proportional to Absolute Temperature (PTAT) and
Complementary to Absolute Temperature (CTAT), which are opposite to
each other.
 PTAT is proportional to absolute temperature, while CTAT is
complementary to absolute temperature. These voltages are added in
such a way that they cancel out the temperature coefficient effect and
produce a stable reference voltage with zero temperature coefficient
effect.
 The BGR circuit is designed to be stabilized over process, voltage, and
temperature variations, and it is implemented without any modification in
the fabrication process.
 The bandgap reference technique is widely used for creating a
temperature-independent reference voltage, and it is often implemented
using a combination of circuit elements such as Proportional To Absolute
Temperature (PTAT) voltage generators and voltage proportional to the
difference in base-emitter voltages of BJTs.
 This approach allows the bandgap reference to mitigate the impact of
temperature fluctuations on the reference voltage, ensuring stable
performance across varying operating conditions.
 Bandgap references can achieve improved line regulation and
lower noise, contributing to the overall precision and reliability of the
SerDes circuitry.
 BUFFERS

 Buffers are two types:

1. Signal Buffers
2.Clock Buffers
 Buffers are used in SerDes to drive the serialized bit stream out. A
Serializer/De-serializer (SerDes) is a pair of functional blocks commonly
used in high-speed communications to compensate for limited
input/output. These blocks convert data between serial data and
parallel interfaces in each direction. The primary use of a SerDes is to
provide data transmission over a single line or a differential pair to
minimize the number of I/O pins and interconnects. Clock buffers are
also used in SerDes to distribute clock signals to multiple devices.
LANE

A lane consists of
1.Transmitter Section
2.Receiver Section
3.Clock Generator
4.Biasing
 Transmitting Section:
It consists of a serializer that encodes he signal and converts
the parallel data to serial and we have driver which is used for pre-
emphasis, impedance matching and signal boosting.
 Receiver Section:
It consists of a rcvr circuit where the signal gets
boosted through equalizers and buffers in it and DFE where we have
De-serializer to convert serial data to parallel and it also decodes the
encoded signal.
 Clock Generator:
It generates different clock signals from an input
reference clock signal which drives transmitter and receiver
section.
 Biasing:
It is the process of providing precise bias voltages and
currents to various components within the SerDes system.
 SERIALIZER

 The serializer is part of the

transmitter (Tx) in a SerDes
system.
 A serializer/de-serializer (SerDes)
is a crucial component in VLSI
(Very Large Scale Integration)
design, especially in high-speed
chip-to-chip communication.
 It (SerDes) consists of functional blocks in a chip that convert
parallel data into serial data and vice versa.
 This conversion reduces the number of interconnects and
input/output pins required for data transmission, addressing
issues such as power consumption, electromagnetic interference,
and clock timing skew associated with transmitting parallel data.
 The serializer typically includes functional blocks such as Parallel In
Serial Out (PISO) and encoding/decoding blocks to prepare the data
for serialization and ensure efficient transmission.
 The process involves encoding the incoming parallel data word into
a defined bit pattern, which is then serialized using shift registers for
efficient transmission over a single differential transmission channel.
 It takes multiple low-speed parallel signals and changes them into
high-speed serial signals.
 The serializer can also include encoding blocks.
 For instance, in an 8b/10b SerDes, each byte from the parallel data
input is converted to a 10-bit symbol and embedded into the serial
stream.
 This encoding scheme achieves DC balance in the serial
transmission channel.
 In summary, a serializer in a SerDes system plays a crucial role in
converting parallel data into a serial data stream, enabling high-
speed and efficient data transmission in VLSI and other
applications like PCI Express, MIPI, USB, and USR.
 DRIVER

 Driver integrated circuits uses a logic signal to control high

voltage and current on or off. example uses include motor controls
and high power lighting switch. when using these chips, consider
adding a heat sink to help dissipate heat.
 Key aspects of the driver's role :
 Signal Strength: The driver is designed to provide sufficient
current or voltage to drive signals through the interconnects,
maintaining signal strength and integrity.
 Fan-out Capability: It must handle the fan-out, representing the
number of loads (e.g., gates or input capacitances) the driver can
effectively drive, without compromising performance.
 Propagation Delay: The driver contributes to the overall propagation
delay of the circuit. Designers strive to minimize propagation delays to
enhance the circuit's speed.
 Output Impedance: Matching the output impedance of the driver with
the transmission line or interconnect impedance is crucial to minimize
signal reflections and ensure efficient signal transfer.
 Buffering: In some cases, multiple driver stages may be used to provide
additional buffering for signals, especially when they need to traverse long
distances or pass through multiple logic gates.
 Power Consumption: Power efficiency is a significant consideration in
VLSI design. Drivers are optimized to operate efficiently, minimizing power
consumption in the circuit.
 In summary, the driver in VLSI plays a crucial role in driving signals through
the interconnects, considering factors such as signal strength, fan-out,
propagation delay, output impedance, power consumption, and technology-
specific considerations. Its effective design is essential for achieving reliable
and high-performance digital circuits in VLSI applications.
RECEIVER

 The receiver section is a serial-to-parallel

converter.
 It contains a demultiplexer (DEMUX)
 Clock and data recovery (CDR),
 Decoder,
 Signal processing
 Jitter tolerance
 Buffers
 CDR
• It is responsible for extracting the clock from the incoming
serial data's edge information and determining the best sampling
location.
• It ensures proper synchronization and alignment with
the transmitted data.
• CDRs operating at tens of gigabits data rate evoke many
challenges, such as high speed phase detection, clock jitter,
speed limitation, power consumption, and low noise VCO design.
• CDRs operating at tens of gigabits data rate evoke
many challenges, such as high speed phase detection,
clock jitter, speed limitation, power consumption, and
low noise VCO design.
 Demultiplexer
• It generates many outputs with the single input by the selection
lines.
 Signal Processing
• The receiver resolves the incoming bits represented by voltage
swings into a digital bit stream
• This involves signal processing to interpret the incoming serial
data and convert it back into parallel form for further processing
by the receiving system.
 Decoder
• It serves multiple functions, primarily related to shaping the incoming
application data stream to make it suitable for deserialization.
• Parallel to Serial Conversion
• Clock Recovery Support
 Jitter Tolerance
• Jitter tolerance specifies how much input jitter a CDR can tolerate
without
increasing the bit error rate (BER)
SIGDET

 The SIGDET (Signal Detect) pin in a SERDES circuit is

used as an indication of link up/down status
 it plays a crucial role in detecting the presence of a valid
signal on the communication channel
 When the SIGDET pin is asserted, it indicates that a valid
signal is present, signifying link up status
 when the SIGDET pin is not asserted, it indicates link
down status, implying the absence of a valid signal on
the communication channel
TERMINATION

 The termination block in a SERDES circuit is a critical component

that ensures proper signal integrity and impedance matching,
especially at the input and output interfaces.
 It includes termination resistors that are essential for matching
the characteristic impedance of the transmission line to minimize
signal reflections and ensure efficient signal transmission.
 The correct choice of termination resistor is crucial for optimizing
signal integrity and minimizing signal distortion
 It is designed to provide impedance matching between the
SERDES circuit and the transmission medium, such as a PCB
trace or a cable
 DFE CORE

 Decision Feedback Equalizer (DFE) is a type of digital signal processing

filter used to equalize distorted signals in communication systems. It is
commonly used in high-speed data transmission systems.
 DFE works by making decisions based on the received signal and using
these decisions to correct errors that occurred in the previous symbol
period. It does this by using a feedback loop that incorporates previous
decisions and errors to adjust the equalization filter coefficients.
 The DFE core typically samples data at each clock sample time and
adjusts the amplitude of the waveform by a correction voltage to
minimize ISI.
 DESERIALIZER

 Deserialization refers to the conversion of serial data back into its

parallel form. A de-serializer circuit (often called a "DESER") will
take in data that has been serialized (sent one bit at a time) and
convert it back into a parallel data stream.
 De-serializer are commonly used in high-speed data transmission
to reduce the number of data lines.
 In many de-serializer designs, a clock signal is embedded in the
serial data stream to facilitate synchronization and proper data
capture.
 It is used to decode the signal.
• DESERIALIZER ( serial to parallel
converter)​
 DFE DACS

 "DFE DACS" refers to the digital-to-analog converters (DACs) used

in the decision feedback equalizer (DFE) of SerDes systems.
 Equalization Control:
The DFE DACs are used to control the equalization levels in the
feedback path of the DFE. The feedback equalization is adjusted based
on the decisions made about previously received symbols.
 Improving Signal Quality:
By dynamically adjusting the feedback equalization using DFE
DACs, the SerDes can improve the overall signal quality and enhance
the ability to recover the transmitted data accurately.
 CLOCK GENERATOR

 In Serializers and De-serializers (SerDes), clock generators play a

crucial role in providing stable and synchronized clock signals for
high-speed data transmission. These clock generators are
designed to minimize jitter, reduce electromagnetic interference
(EMI), and enable flexible frequency planning.
 They are also tailored for low-power, low-area, and high-speed
applications, making them suitable for on-chip SerDes
implementations.
 The clock generator typically takes an input reference clock and
generates the necessary clock signals for the SerDes system. It
helps in ensuring that the transmitted data is synchronized and
accurately sampled at the receiving end.
 The input reference clock is from the clock and data recovery
circuit(CDR),it uses phase detectors and voltage-controlled
oscillators (VCOs) to recover the clock signal from the incoming
data stream.
 The generated clock signals drives the transmitter and receiver
sections through buffers in SERDES.
 BIASING

 In Serializer/De-serializer (SerDes), the term "biasing block" refers to the

circuitry or components responsible for generating and maintaining the
necessary bias voltages and currents within the SerDes system. These
bias voltages and currents are crucial for ensuring proper operation and
performance of the SerDes interface.
 Biasing blocks in SerDes circuits are used to establish the appropriate DC
levels and ensure proper functionality.
 Biasing usually refers to a fixed DC voltage or current applied to a
terminal of an electronic component such as a diode, transistor or vacuum
tube in a circuit in which AC signals are also present, in order to establish
proper operating conditions for the component.
 Bias Voltage Generation:
The biasing block generates stable bias voltages that are required for
different parts of the SerDes circuit, such as amplifiers, comparators, and
other analog components.
 Current Sources:
Biasing often involves the use of current sources to ensure a consistent
and controlled current flow through specific parts of the circuit.
This is important for maintaining the desired operating conditions.
 Noise Margin Improvement:
Proper biasing helps improve the noise margin of the SerDes circuit,
 Temperature Compensation:
Biasing blocks may include temperature compensation
mechanisms to account for variations in temperature that could affect the
performance of the circuit. Temperature stability is crucial for reliable
operation.
 Power Efficiency:

Efficient biasing is essential for minimizing power consumption while

maintaining the required performance. This is especially important in
applications where power efficiency is a critical consideration.
 DC Level Adjustment:

Biasing blocks are responsible for setting the DC operating points

 Common-Mode Voltage Control: Biasing is crucial for controlling
common-mode voltages in differential signal paths. Common-mode
voltage refers to the average voltage between the positive and
negative signal lines. Biasing ensures that the common-mode voltage
is at the desired level, helping to maintain signal integrity.
In summary, the biasing block in SerDes plays a critical role in
maintaining proper voltage levels, currents, and signal integrity, which
are essential for the reliable operation of high-speed serial data
interfaces. It ensures that the transmitted and received signals are
accurately interpreted and processed, contributing to the overall
performance of the SerDes system.
 ADVANTAGES

 Reduction in cable or channel count and pin count, leading to cost

savings, complexity reduction, and decreased board-space requirements.
 Ability to transmit bytes of data via a pair of differential signal pins,
which leads to cost savings due to smaller packages and denser PCBs
 Low-power consumption, robust EMI performance, and easy
implementation in high-speed chip-to-chip communication.
 Support for multiple data rates and standards like PCI Express (PCIe),
MIPI, Ethernet, USB, USR/XSR, making it suitable for various applications
such as high-performance computing, artificial intelligence, automotive,
mobile, and Internet-of-Things (IoT).
 APPLICATIONS

SerDes chips are used in

 Gigabit Ethernet systems
 wireless network
 routers, fiber optic communication
systems
 storage systems, automotive
components and a wide range of other
environments.
 Many of today's SerDes devices
operate at speeds in excess of 100
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