Chapter 7

Memory and Programmable

Logic

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 7-1. Introduction
 There are two types of memories that are used in di
gital systems:
Random-access memory(RAM): perform both the write and
read operations.

Read-only memory(ROM): perform only the read operation.

 The read-only memory is a programmable logic devi
ce. Other such units are the programmable logic arr
ay(PLA), the programmable array logic(PAL), and the
field-programmable gate array(FPGA).

2
 Array logic
 A typical programmable logic device may have hund
reds to millions of gates interconnected through hun
dreds to thousands of internal paths.
 In order to show the internal logic diagram in a conc
ise form, it is necessary to employ a special gate sy
mbology applicable to array logic.

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 7-2. Random-Access
Memory
 A memory unit stores binary information in groups of bits called
words.
1 byte = 8 bits
1 word = 2 bytes
 The communication between a memory and its environment is
achieved through data input and output lines, address selection
lines, and control lines that specify the direction of transfer.

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 Content of a memory
 Each word in memory is
assigned an identification
number, called an
address, starting from 0
up to 2k-1, where k is the
number of address lines.
 The number of words in a
memory with one of the
letters K=210, M=220, or
G=230.
64K = 216 2M = 221
4G = 232 5
 Write and Read operations
 Transferring a new word to be stored into
memory:
1. Apply the binary address of the desired
word to the address lines.
2. Apply the data bits that must be stored in
memory to the data input lines.
3. Activate the write input.

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 Write and Read operations
 Transferring a stored word out of memory:
1. Apply the binary address of the desired word to
the address lines.
2. Activate the read input.
 Commercial memory sometimes provide the two
control inputs for reading and writing in a
somewhat different configuration in table 7-1.

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 Memory description in HDL
A memory of 1024 words
with 16-bits per word is
declared as
reg [15:0] memword[0:102
3];

Read/Write = 1
DataOut  Mem[Address];

Read/Write =0
Mem[Address]  DataIn;

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 Timing Waveforms (write)
 The access time and cycle
time of the memory must be
within a time equal to a fixed
number of CPU clock cycles.
 The memory enable and the
read/write signals must be
activated after the signals in
the address lines are stable
to avoid destroying data in
other memory words.
 Enable and read/write
signals must stay active for
at least 50ns.
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 Timing Waveforms (read)
 The CPU can
transfer the data
into one of its
internal registers
during the negative
transition of T3.

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 Types of memories
 In random-access memory, the word
locations may be thought of as being
separated in space, with each word
occupying one particular location.
 In sequential-access memory, the
information stored in some medium is not
immediately accessible, but is available only
certain intervals of time. A magnetic disk or
tape unit is of this type.
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 Types of memories
 In a random-access memory, the access time
is always the same regardless of the
particular location of the word.
 In a sequential-access memory, the time it
takes to access a word depends on the
position of the word with respect to the
reading head position; therefore, the access
time is variable.

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 Static RAM
 SRAM consists essentially of internal latches that
store the binary information.
 The stored information remains valid as long as
power is applied to the unit.
 SRAM is easier to use and has shorter read and write
cycles.
 Low density, low capacity, high cost, high speed,
high power consumption.

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 Dynamic RAM
 DRAM stores the binary information in the form of
electric charges on capacitors.
 The capacitors are provided inside the chip by MOS
transistors.
 The capacitors tends to discharge with time and
must be periodically recharged by refreshing the
dynamic memory.

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 Dynamic RAM
 DRAM offers reduced power consumption and larger
storage capacity in a single memory chip.
 High density, high capacity, low cost, low speed, low
power consumption.

15
 Types of memories
 Memory units that lose stored information
when power is turned off are said to be
volatile.
 Both static and dynamic, are of this category
since the binary cells need external power to
maintain the stored information.
 Nonvolatile memory, such as magnetic disk,
ROM, retains its stored information after
removal of power.
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 7-3. Memory decoding
 The equivalent logic of a binary cell that stores one bit of
information is shown below.
Read/Write = 0, select = 1, input data to S-R latch
Read/Write = 1, select = 1, output data from S-R latch

SR latch with NOR gates 17

Ref. Figure 5-3
 4X4 RAM
 There is a need for decoding
circuits to select the
memory word specified by
the input address.
 During the read operation,
the four bits of the selected
word go through OR gates to
the output terminals.
 During the write operation,
the data available in the
input lines are transferred
into the four binary cells of
the selected
A memory word.
with 2k words of n bits per word requires k address lines that go into
x2k decoder. 18
 Coincident decoding
address
 A decoder with k inputs
and 2k outputs requires 2k
AND gates with k inputs
per gate.
 Two decoding in a two-
dimensional selection
scheme can reduce the
number of inputs per
gate.
 1K-word memory, instead
of using a single 10X1024
decoder, we use two
5X32 decoders.
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 Address multiplexing
 DRAMs typically have four times the density of SRA
M.

 The cost per bit of DRAM storage is three to four tim

es less than SRAM. Another factor is lower power req
uirement.

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 Address multiplexing
 Address multiplexing will reduce the number of pins
in the IC package.

 In a two-dimensional array, the address is applied in

two parts at different times, with the row address
first and the column address second. Since the same
set of pins is used for both parts of the address, so
can decrease the size of package significantly.

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 Address multiplexing for 64K
DRAM
 After a time equivalent Column Address Selection
to the settling time of
the row selection, RAS
goes back to the 1 level.
Row Address Selection
 Registers are used to
store the addresses of
the row and column.
 CAS must go back to the
1 level before initialing
another memory
operation.
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 7-4. Error detection and
correction
 It is protecting the occasional errors in
storing and retrieving the binary information.
 Parity can be checked the error, but it can’t
be corrected.
 An error-correcting code generates multiple
parity check bits that are stored with the
data word in memory.

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 Hamming Code
 One of the most common used in RAM was devised
by R. W. Hamming (called Hamming code).
 In Hamming code:
k = parity bits in n-bit data word,
forming a new word of n + k bits. Those positions
numbered as a power of 2 are reserved for the
parity bits.
the remaining bits are the data bits.

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 Hamming Code
Ex. Consider the 8-bit data word 11000100. we include
four parity bits with it and arrange the 12 bits as
follows:
Bit position: 1 2 3 4 5 6 7 8 9 10 11 12
P1 P 2 1 P 4 1 0 0 P 8 0 1 0 0

P1 = XOR of bits(3,5,7,9,11) = 1 ⊕ 1 ⊕ 0 ⊕ 0 ⊕ 0 = 0

P2 = XOR of bits(3,6,7,10,11) = 1 ⊕ 0 ⊕ 0 ⊕ 1 ⊕ 0 = 0

P4 = XOR of bits(5,6,7,12) = 1 ⊕ 0 ⊕ 0 ⊕ 0 = 1

P8 = XOR of bits(9,10,11,12) = 0 ⊕ 1 ⊕ 0 ⊕ 0 = 1 25
 Hamming Code
 The data is stored in memory together with the parity
bit as 12-bit composite word.
Bit position: 1 2 3 4 5 6 7 8 9 10 11 12
0 0 1 1 1 0 0 1 0 1 0 0

 When read from memory, the parity is checked over

the same combination of bits including the parity bit.
C1 = XOR of bits(3,5,7,9,11)
C2 = XOR of bits(3,6,7,10,11)
C4 = XOR of bits(5,6,7,12)
C8 = XOR of bits(9,10,11,12)
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 Error-Detection
 A 0 check bit designates an even parity over
the checked bits and a 1 designates an odd
parity.
 Since the bits were stored with even parity,
the result,
C = C8C4C2C1 = 0000, indicates that no error
has occurred.
 If C ≠ 0, then the 4-bit binary number
formed by the check bits gives the position
of the erroneous bit. 27
 Example
Bit position: 1 2 3 4 5 6 7 8 9 10 11 12
0 0 1 1 1 0 0 1 0 1 0 0 No error
1 0 1 1 1 0 0 1 0 1 0 0 Error in bit 1
0 0 1 1 0 0 0 1 0 1 0 0 Error in bit 5
 Evaluating the XOR of the corresponding bits, get the
four check bits

C8 C4 C2 C1
For no error: 0 0 0 0

with error in bit 1: 0 0 0 1

with error in bit 5: 0 1 0 1

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 Hamming Code
 The Hamming Code can
be used for data words of
any length.
 Total bit in Hamming
Code is n + k bits, the
syndrome value C
consists of k bits and has
a range of 2k value
between 0 and 2k − 1. the
range of k must be equal
to or greater than n + k,
giving the relationship
2k-1 ≥ n + k
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 Single-Error correction, Double-
Error detection
 The Hamming Code can detect and correct only a
single error.
 By adding another parity bit to the coded word, the
Hamming Code can be used to correct a single error
and detect double errors. Becomes 001110010100P 13.

001110010100 P13  001110010100 1

P= XOR( 001110010100 1 )

if P = 0, the parity is correct (even parity), but if P = 1,

then the parity over the 13 bits is incorrect (odd
parity).
the following four cases can occur:
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 Single-Error correction, Double-
Error detection
1. If C = 0 and P = 0, no error occurred
2. If C ≠ 0 and P = 1, a single error occurred
that can be corrected
3. If C ≠ 0 and P = 0, a double error occurred
that is detected but that cannot be
corrected
4. If C = 0 and P = 1, an error occurred in the
P13 bit

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 7-5. Read-Only Memory
 A block diagram of a ROM is shown below. It consists
of k address inputs and n data outputs.
 The number of words in a ROM is determined from
the fact that k address input lines are needed to
specify 2k words.

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 Construction of ROM
 Each output of the decoder represents a memory address.
 Each OR gate must be considered as having 32 inputs.
 A 2k X n ROM will have an internal k X 2k decoder and n
OR gates.

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 Truth table of ROM
 A programmable connection between to lines is
logically equivalent to a switch that can be altered
to either be close or open.
 Intersection between two lines is sometimes called a
cross-point.

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 Programming the ROM
In Table 7-3, 0  no connection
1  connection
Address 3 = 10110010 is permanent storage using fuse link

1 0 1 1 0 0 1 0

X : means connection

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 Combinational circuit
implementation
 The internal operation of a ROM can be interpreted
in two way: First, a memory unit that contains a
fixed pattern of stored words. Second, implements a
combinational circuit.
 Fig. 7-11 may be considered as a combinational
circuit with eight outputs, each being a function of
the five input variables.

A7(I4, I3, I2, I1, I0) = Σ(0,2,3…,29)

Sum of minterms

In Table 7-3, output A7

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 Example
 Design a combinational circuit using a ROM. The circuit accepts a 3-bit
number and generates an output binary number equal to the square of
the input number.
Derive truth table first

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Example

38
 Types of ROMs
 The required paths in a ROM may be programmed
in four different ways.
1. Mask programming: fabrication process
2. Read-only memory or PROM: blown fuse /fuse
intact
3. Erasable PROM or EPROM: placed under a special
ultraviolet light for a given period of time will
erase the pattern in ROM.
4. Electrically-erasable PROM(EEPROM): erased with
an electrical signal instead of ultraviolet light.
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 Combinational PLDs
 A combinational PLD is an integrated circuit with pro
grammable gates divided into an AND array and an
OR array to provide an AND-OR sum of product impl
ementation.
 PROM: fixed AND array constructed as a decoder an
d programmable OR array.
 PAL: programmable AND array and fixed OR array.
 PLA: both the AND and OR arrays can be programme
d.

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Combinational PLDs

41
 7-6. Programmable Logic
Array
 Fig.7-14, the decoder in PROM is replaced by an
array of AND gates that can be programmed to
generate any product term of the input variables.
 The product terms are then connected to OR gates
to provide the sum of products for the required
Boolean functions.
 The output is inverted when the XOR input is
connected to 1 (since x⊕1 = x’). The output doesn’t
change and connect to 0 (since x⊕0 = x).

42
PLA
F1 = AB’+AC+A’BC’
F2 = (AC+BC)’

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 Programming Table
1. First: lists the product terms numerically
2. Second: specifies the required paths betwe
en inputs and AND gates
3. Third: specifies the paths between the AND
and OR gates
4. For each output variable, we may have a T
(ture) or C(complement) for programming t
he XOR gate

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 Simplification of PLA
 Careful investigation must be undertaken in
order to reduce the number of distinct
product terms, PLA has a finite number of
AND gates.
 Both the true and complement of each
function should be simplified to see which
one can be expressed with fewer product
terms and which one provides product terms
that are common to other functions.
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 Example 7-2
Implement the following two Boolean functions with a PLA:
F1(A, B, C) = ∑(0, 1, 2, 4)
F2(A, B, C) = ∑(0, 5, 6, 7)

The two functions are simplified in the maps of Fig.7-15

1 elements

0 elements
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 PLA table by simplifying the
function
 Both the true and
complement of the functions
are simplified in sum of
products.
 We can find the same terms
from the group terms of the
functions of F1, F1’,F2 and F2’
which will make the
minimum terms.

F1 = (AB + AC + BC)’
F2 = AB + AC + A’B’C’

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PLA implementation

AB

AC

BC

A’B’
C’

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 7-7. Programmable Array
Logic
 The PAL is a programmable logic device with a fixed OR array
and a programmable AND array.

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 PAL
 When designing with a PAL, the Boolean
functions must be simplified to fit into each
section.
 Unlike the PLA, a product term cannot be
shared among two or more OR gates.
Therefore, each function can be simplified by
itself without regard to common product terms.
 The output terminals are sometimes driven by
three-state buffers or inverters.
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 Example
w(A, B, C, D) = ∑(2, 12, 13)
x(A, B, C, D) = ∑(7, 8, 9, 10, 11, 12, 13, 14, 15)
y(A, B, C, D) = ∑(0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)
z(A, B, C, D) = ∑(1, 2, 8, 12, 13)

Simplifying the four functions as following Boolean function

s:

w = ABC’ + A’B’CD’
x = A + BCD
w = A’B + CD + B’D’
w = ABC’ + A’B’CD’ + AC’D’ + A’B’C’D = w + AC’D’ + A’B’C
’D
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 PAL Table
 z has four product terms, and we can replace by w
with two product terms, this will reduce the number
of terms for z from four to three.

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PAL implementation

53
Fuse map for example

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 7-8. Sequential Programmable
Devices
 Sequential programmable devices include
both gates and flip-flops.
 There are several types of sequential
programmable devices, but the internal logic
of these devices is too complex to be shown
here.
 We will describe three major types without
going into their detailed construction.

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 Sequential Programmable
Devices
1. Sequential (or simple) Programmable Logic Device
(SPLD)
2. Complex Programmable Logic Device (CPLD)
3. Field Programmable Gate Array (FPGA)

56
 FPLS
 The first programmable device developed to support
sequential circuit implementation is the field-progra
mmable logic sequencer(FPLS).
 A typical FPLS is organized around a PLA with severa
l outputs driving flip-flops.
 The flip-flops are flexible in that they can be progra
mmed to operate as either JK or D type.
 The FPLS did not succeed commercially because it h
as too many programmable connections.

57
 SPLD
 Each section of an SPLD is called a macrocell.
 A macrocell is a circuit that contains a sum-o
f-products combinational logic function and a
n optional flip-flop.
 We will assume an AND-OR sum of products
but in practice, it can be any one of the two-l
evel implementation presented in Sec.3-7.

58
 Macrocell
 Fig.7-19 shows the logic of a basic macrocell.
 The AND-OR array is the same as in the combination
al PAL shown in Fig.7-16.

59
 CPLD
 A typical SPLD has from 8 to 10 macrocells within on
e IC package. All the flip-flops are connected to the c
ommon CLK input and all three-state buffers are con
trolled by the EO input.
 The design of a digital system using PLD often requir
es the connection of several devices to produce the
complete specification. For this type of application, i
t is more economical to use a complex programmabl
e logic device (CPLD).
 A CPLD is a collection of individual PLDs on a single i
ntegrated circuit.
60
 CPLD
 Fig.7-20 shows a general configuration of a CPLD. It co
nsists of multiple PLDs interconnected through a progr
ammable switch matrix. 8 to 16 macrocell per PLD.

61
 Gate Array
 The basic component used in VLSI design is
the gate array.
 A gate array consists of a pattern of gates
fabricated in an area of silicon that is
repeated thousands of times until the entire
chip is covered with the gates.
 Arrays of one thousand to hundred thousand
gates are fabricated within a single IC chip
depending on the technology used.

62
 FPGA
 FPGA is a VLSI circuit that can be programmed in
the user’s location.
 A typical FPGA logic block consists of look-up tables,
multiplexers, gates, and flip-flops.
 Look-up table is a truth table stored in a SRAM and
provides the combinational circuit functions for the
logic block.

63
 Differential of RAM and ROM in
FPGA
 The advantage of using RAM instead of ROM to store
the truth table is that the table can be programmed
by writing into memory.
 The disadvantage is that the memory is volatile and
presents the need for the look-up table content to
be reloaded in the event that power is disrupted.

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