MIXED-TYPED DESCRIPTIONS
IN VERILOG AND VHDL
CPEHDL
IN THIS DISCUSSION, WE WILL FOCUS ON THE
FOLLOWING TOPICS:
[Link] to Mixed-Type Description
[Link] User-Defined Types
[Link] Packages
[Link]-Type Description Examples in Verilog and
VHDL
DEFINITION
Mixed-Typed Descriptions in hardware description
languages (HDLs) refer to the ability to combine different
data types (e.g., integers, arrays, records) within a single
design or description. This approach enables more flexible
and reusable code and allows for creating complex designs
that leverage various data types in both Verilog and VHDL.
INTRODUCTION TO MIXED-TYPE DESCRIPTION
• In hardware description languages (HDLs) like Verilog and
VHDL, mixed-type descriptions involve using multiple data
types within the same design. This can include primitive types
(such as bit or integer) alongside user-defined types (such as
arrays, records, or enumerations).
• Using mixed-type descriptions allows for creating more
compact, readable, and flexible code that can model more
complex hardware systems. For example, a VHDL record may
combine multiple signal types, or a Verilog struct can hold
different data elements in a single variable, enabling better
abstraction of hardware structures.
WHY USE MIXED-TYPE DESCRIPTIONS?
Using mixed-type descriptions allows designers to:
• Balance Abstraction and Detail: High-level parts of the
design can be modeled behaviorally, while low-level, timing-
critical parts can be modeled with dataflow or structurally.
• Optimize Readability and Performance: Behavioral
descriptions are easier to understand and modify, while
structural or dataflow descriptions offer precise control over
hardware resources.
• Reuse Components: Structural modeling lets designers reuse
pre-existing components (like registers), while behavioral
sections can describe unique logic.
EXAMPLE: CONSIDER A CASE WHERE YOU NEED TO MODEL A SYSTEM
WITH AN INTEGER COUNTER AND A BOOLEAN SIGNAL. IN VERILOG, THIS
COULD BE DONE BY COMBINING THE INTEGER AND BOOLEAN INTO A
STRUCT OR ARRAY, WHILE IN VHDL, THE RECORD TYPE COULD BE
USED.
Verilog
struct {
integer counter; // Here, mySystem is a single
entity containing both an
Integer counter variable integer and a bit (Verilog's
equivalent of a boolean). This
bit signal; // Boolean
makes it easy to pass the two
signal related variables as a single
unit within a design.
} mySystem;
EXAMPLE: CONSIDER A CASE WHERE YOU NEED TO MODEL A SYSTEM
WITH AN INTEGER COUNTER AND A BOOLEAN SIGNAL. IN VERILOG, THIS
COULD BE DONE BY COMBINING THE INTEGER AND BOOLEAN INTO A
STRUCT OR ARRAY, WHILE IN VHDL, THE RECORD TYPE COULD BE
USED.
VHDL code
type MySystemType is record
counter : integer; -- Integer In this case, MySystemType is a
counter variable record that combines both an
integer and a boolean, which
signal : boolean; -- Boolean
are two different data types,
signal
into one cohesive type. The
end record; mySystem signal is of this
record type, holding both the
counter and signal.
signal mySystem : MySystemType; --
Declare signal of type MySystemType
Example of accessing and modifying fields:
-- To assign values to the fields of mySystem (VHDL)
[Link] := 10; -- Set the counter to 10
[Link] := TRUE; -- Set the signal to TRUE
Verilog
// Declare and initialize mySystem
[Link] = 10; // Set the counter to 10
[Link] = 1; // Set the signal to true (1)
WHY IS THIS A MIXED-TYPE DESCRIPTION?
Mixed-type refers to the use of multiple data types
together. In this case, an integer (counter) and a boolean
(signal) are different types, but they are combined together
in a single data structure (struct in Verilog, record in VHDL).
The structure allows you to handle and manipulate both
types in a single entity, simplifying the design and making
the code cleaner when dealing with related signals.
VHDL USER-DEFINED TYPES
• In VHDL, you can define your own data types, which can be either simple or
complex. This allows for flexibility in how data is represented and manipulated
within your design. Common user-defined types include enumerated types,
array types, and record types.
COMMON USER-DEFINED TYPES IN VHDL:
Enumerated types: These are types that allow you to define a set of named
values, making it easier to represent finite state machines, logic levels, etc.
Summary:
• The enumerated type state_type defines a
set of possible states: IDLE, RUN, and STOP.
type state_type is
• The signal current_state will hold one of these
(IDLE, RUN,
states at any given time.
STOP); • This structure is commonly used in finite
signal state machine (FSM) designs to track and
current_state : manage the system's state, making the code
state_type; more readable and easier to manage
transitions between different stages or
EXAMPLE OF A COMPLETE FSM IN VHDL:
-- Define the type for states process (clk)
type state_type is (IDLE, RUN, begin
STOP);
if rising_edge(clk) then
current_state <= next_state; --
-- Signal to hold the current state Update the current state at the
rising edge of clk
signal current_state, next_state :
state_type; end if;
end process;
-- Process that defines the state
machine
Usage in a Finite State Machine
(FSM):
-- Process to define the state transitions when RUN =>
and actions
-- Transition to STOP if some other
process (current_state) condition is met
begin next_state <= STOP;
when STOP =>
case current_state is
-- Return to IDLE (or stay in STOP
when IDLE => based on design needs)
-- Transition to RUN if some next_state <= IDLE;
condition is met
when others =>
next_state <= RUN;
next_state <= IDLE; -- Default case
end case;
end process;
COMMON USER-DEFINED TYPES IN VHDL (CONT):
Array types: These can hold multiple elements of the same base type, often used
for signals like buses or memory storage.
Summary:
•This line defines a new array type called
array_type.
type array_type is
•The range (0 to 7) specifies the valid indices for
array (0 to 7) of
the array, so it will have indices 0, 1, 2, ..., up to
bit; 7. This is an 8-bit wide array.
signal my_array : •The signal my_array will hold an array of 8 bit
array_type; values, and its values can change over time
based on the logic implemented in the VHDL
process.
EXAMPLE OF FULL USAGE IN A PROCESS:
type array_type is array (0 to 7) -- Manipulating individual
of bit; bits
signal my_array : array_type; if my_array(3) = '1'
process(clk) then
begin my_array(5) <= '0';
if rising_edge(clk) then -- Change bit 5 based on
-- Assigning a value to the condition
entire array end if;
my_array <= "10101010"; end if;
-- Set the array to an 8-bit
end process;
pattern
COMMON USER-DEFINED TYPES IN VHDL (CONT):
Record types: These are used to group together different types of data under a
single variable, similar to structures in C or Verilog.
type data_type is Summary:
record • This line declares a new user-defined type
address : integer; called data_type which is a record.
data : •This declares a field named address of type
bit_vector(7 downto integer.
0); •This declares a field named data of type
end record; bit_vector(7 downto 0)
•This line declares a signal named my_data of
signal my_data : the previously defined data_type.
-- Accessing the fields of
my_data
Usage of my_data
Signal if my_data.address = 100
then
process(clk) -- Do something with the
begin data when the address is 100
if rising_edge(clk) then report "Data at address
100 is: " &
-- Assigning values to my_data
to_string(my_data.data);
my_data.address <= 100;
end if;
-- Set address to 100
my_data.data <= end if;
"10101010"; -- Set data to end process;
8-bit pattern
VHDL PACKAGES
In VHDL, packages allow you to encapsulate type
definitions, constants, and function declarations into a
reusable module. This allows you to define complex types
and operations in one place and make them accessible
across multiple designs. Packages help in modularizing
designs, enhancing reusability and maintainability.
KEY CONCEPTS OF PACKAGES IN VHDL
[Link] Declaration: A package is created by using the
package keyword. It contains the definitions of types,
constants, functions, procedures, etc., that you want to make
available to other VHDL units.
[Link] Body: If the package contains functions or
procedures, these must be implemented in a package body. A
package body provides the actual code or implementation for
the functions and procedures declared in the package.
[Link]: Once a package is defined, you can use it in other
parts of your design (such as entities, architectures, or other
packages) by including a use statement. This allows you to
EXAMPLE OF USING A PACKAGE IN VHDL
package my_package is -- Package
declaration (my_package.vhdl)
1. Creating a Package type std_logic_vector_8 is array(0 to 7)
of std_logic; -- Define a custom type (8-
You can define a package
bit vector)
that contains types,
constants, and functions. constant max_value : integer := 255; --
For example, let's create a Constant declaration
package that defines a
function reverse_bits(input :
custom type
std_logic_vector_8) return
(std_logic_vector_8) and a std_logic_vector_8; -- Function
function to reverse the bits declaration
in the vector.
end package;
EXAMPLE OF USING A PACKAGE IN VHDL
package body my_package is --
Package body (my_package_body.vhdl)
2. Package Body function reverse_bits(input :
std_logic_vector_8) return
In the package body, you std_logic_vector_8 is
would implement the variable reversed :
std_logic_vector_8 := (others => '0’); --
functions declared in the
Function to reverse the bits of an 8-bit
package header. Here, vector
we'll implement the begin
reverse_bits function to for i in 0 to 7 loop
reversed(i) := input(7 - i);
reverse the bits in the
end loop;
std_logic_vector_8. return reversed;
end function;
end package body;
USING THE PACKAGE IN A DESIGN
-- VHDL entity that uses the architecture behavior of
package test_entity is
library IEEE; begin
use IEEE.STD_LOGIC_1164.ALL; process(input_bits)
use work.my_package.all; -- Use begin
the package
-- Reverse the bits using the
entity test_entity is function from the package
port( output_bits <=
reverse_bits(input_bits);
input_bits : in
std_logic_vector(7 downto 0); end process;
output_bits : out end architecture behavior;
std_logic_vector(7 downto 0)
);
BENEFITS OF USING PACKAGES
• Modularity: Packages allow you to separate concerns. For
example, you can have one package defining custom data
types and another defining functions. This separation
makes your code more organized and easier to manage.
• Reusability: Once a package is created, you can reuse it in
different parts of your design or in multiple projects. This
promotes code reuse and reduces redundancy.
BENEFITS OF USING PACKAGES
• Maintainability: Changes to commonly used types,
constants, or functions can be made in one place (the
package), and the changes will be reflected in all designs
that use the package. This makes the codebase easier to
maintain.
• Abstraction: Packages allow you to abstract away complex
logic or definitions. For instance, if you have a complex bit
manipulation function, you can define it once in a package,
and all other VHDL entities that need to use it can simply
use the package.
In VHDL, packages are powerful tools for encapsulating
types, constants, and functions, allowing you to organize
and reuse your code across multiple designs. They promote
modularity, reusability, and maintainability, helping you
manage large and complex designs more effectively.
KEY DIFFERENCES BETWEEN HDL CONSTRUCTS AND MIXED-TYPE
DESCRIPTIONS
MIXED-TYPE DESCRIPTION EXAMPLES IN VERILOG AND VHDL
Here are some examples of mixed-type descriptions in
Verilog and VHDL, showcasing how both languages can
handle signals of different types in the same design:
EXAMPLE 1: COMBINING WIRE AND REG TYPES
(VERILOG)
module assign data =
mixed_type_example; 4'b1101;
// Scalar and vector types
reg clk; initial begin
wire [3:0] data; clk = 0;
reg [7:0] reg_data; #10 clk = 1;
end
// Mixed operations with Endmodule
different data types
always @(posedge clk)
begin
reg_data <= data +
4'b1010; // Adding vector
with scalar value
end
EXAMPLE 2: MIXED TYPES IN A FUNCTION (VERILOG)
module assign output_data =
mixed_function_example; process_data(input_data[
reg [7:0] input_data; 7:4], input_data[3:0]);
wire [7:0] output_data;
initial begin
// Function using mixed-
input_data =
type arguments
function [7:0] 8'b11011010;
process_data(input [3:0] end
part1, input [3:0] part2); Endmodule
begin
process_data =
{part1, part2}; //
Concatenation of two 4-bit
parts
EXAMPLE 3: MIXED SIGNAL TYPES IN A PROCESS
(VHDL)
library IEEE; architecture Behavioral of
use mixed_type_example is
IEEE.STD_LOGIC_1164.ALL; begin
use process(clk)
IEEE.STD_LOGIC_ARITH.ALL;
begin
use
if rising_edge(clk)
IEEE.STD_LOGIC_UNSIGNED
.ALL; then
reg_data <=
entity mixed_type_example std_logic_vector(unsigne
is d(data) + "1010");
Port ( clk : in STD_LOGIC; end if;
data : out end process;
STD_LOGIC_VECTOR(3
downto 0); data <= "1101";
EXAMPLE 4: FUNCTION WITH MIXED TYPES
library IEEE; architecture Behavioral of begin
use mixed_function_example return part1 &
IEEE.STD_LOGIC_1164.ALL; is part2; --
use function Concatenate two 4-
IEEE.STD_LOGIC_ARITH.ALL; process_data(part1 : bit parts to form 8
STD_LOGIC_VECTOR(3 bits
entity downto 0);
mixed_function_example is end function;
part2 :
Port ( input_data : in STD_LOGIC_VECTOR(3
STD_LOGIC_VECTOR(7 begin
downto 0))
downto 0); output_data <=
return
output_data : out process_data(input_d
STD_LOGIC_VECTOR is
STD_LOGIC_VECTOR(7 ata(7 downto 4),
downto 0));
begin
input_data(3 downto
end return part1 & part2;
-- Concatenate two 4-bit 0));
mixed_function_example;
KEY DIFFERENCES:
• Verilog uses wire and reg types to differentiate between
combinational and sequential signals. Operations on these
types often require explicit type conversions (e.g., unsigned
or logic).
• VHDL is more strongly typed and uses packages like
STD_LOGIC_ARITH or STD_LOGIC_UNSIGNED for arithmetic
operations and conversions between different types (e.g.,
from STD_LOGIC_VECTOR to unsigned).
END
