3.

4 Bus Interconnection
 A bus is a shared transmission medium.
 A Bus is a communication pathway connecting two or more
devices.
 A bus consists of multiple communication pathways, or lines,
often grouped. A System Bus connects major computer
components.
 A number of line/channel in one bus, each capable of carrying one
bit. Clock

Cycles
Over time, a sequence of binary digits can be transmitted over a
single line.
 Taken together, several lines of a bus can be used to transmit
binary data simultaneously (in parallel).
 e.g. 32 bit data bus is 32 separate single bit channels.
 For example, an 8-bit unit of data can be transmitted over eight
bus lines.
1
Types of Buses
A system bus consists typically, of from about
fifty to hundreds of separate lines.
Each line is assigned a particular meaning or
function.
The bus lines can be classified into three groups:
1) Address lines (bus)2) Data lines (bus) 3)
Control lines (bus)
In addition, there may be power distribution
lines to attached module.
Two way
Communicatio
n;
Read & Write
2
1. Data Bus
 The data lines provide a path for moving data among system
modules.
 These lines, collectively, are called the data bus.
 The data bus may consist of 32, 64, 128 or even more separate
lines.
 Each line can carry only one bit at a time, the number of lines
determine how many bits can be transferred at a time.
 The number of these data lines are called the width of the
data bus.
 The width of the data bus determines the overall system
performance.
 For example, if the data bus is 32 bits wide and each
instruction is 64 bits long, then the processor must access the
memory module twice during each instruction cycle. (e.g. two
fetch operations in each line)
3
2. Address Bus
 The address lines are used to designate the source or
destination of the data on the data bus.
 If the processor wishes to read a word (8, 16 or 32 bits)
of data from memory, it puts the address of the desired
word on the address lines.
 The width of the address bus determines the maximum
‘memory capacity’ of the system. (i.e. more bits mean
more memory locations)
 E.g. 8080 has 16 bit address bus giving 2^16 = 64k
address space.
 Furthermore, the address lines are also used to address
I/O ports.
 The higher-order bits are used to select a particular
module on the bus, and the lower-order bits select a
memory location or I/O port.
4
3. Control Bus
The control lines are used to control the access to
and the use of the data and address lines.
Because data and address lines are shared by all
components, there must be a means of controlling
their use.
Control signals transmit both command and timing
information among system modules. (Control Unit)
Timing signals indicate the validity of data and
address information.
Command signals specify operations to be
performed.
Typical control line signals are given in the next
slide.
5
Control Line Signals

6
Limitations of Bus Design
A bus is a shared transmission medium.
Multiple devices connect to the bus, and a signal
transmitted by any one device is available for
reception by all other devices attached to the bus.
If two devices transmit during the same time
period, their signals will overlap and will become
garbled (Make false by subtract or addition).
Thus, only one device at a time can successfully
transmit.
We need to set up rules so that only one device
can take control of the bus at a time.
7
Bus Operation Explained
 If one module wishes to send data to another, it must do two
things:
1. Obtain the use of the bus, using ‘bus request’ control
signal.
2. Transfer data via the bus, using memory write or I/O write
signal.

 If one module wishes to request data from another module, it

must:
1. Obtain the use of the bus, using ‘bus request’ control
signal.
2. Transfer a request to the other module over the
appropriate control and address lines, using memory read
or I/O read control signal.
3. It must then wait for the second module to send the data.
8
Single-Bus Problems
 If a great number of devices are connected to a single
bus, performance will suffer. There are two main causes:
1. In general, the more devices attached to the bus, the
greater the bus length and hence the greater the
propagation delay.
 Delay in co-ordination of bus use can adversely affect
performance.
2. The bus may become a bottleneck as the aggregate data
transfer demand approaches the capacity of the bus.
 This problem can be countered to some extent by
increasing the data rate that the bus can carry and by
using wider buses.
 Solution: Instead of a single –bus, use multiple buses in a
hierarchy.
9
Traditional Bus Architecture

Break

10
Elements of Bus Design

11
Hierarchy – Elements of Bus Design
Types of buses
Dedicated
Multiplexed
Distributed Arbitration
Centralized Arbitration
 Synchronous Timing
 Asynchronous Timing.

12
Bus Types
Bus lines can be separated into two generic types:
1) Dedicated 2) Multiplexed
1. Dedicated bus line: is permanently assigned to one
physical subset of computer components. E.g.
processor and cache.
It refers to the use of multiple buses, each of which
connects only a subset of modules.
An example is the use of separate dedicated address
and data lines.
The potential advantage of physical dedication is high
throughput (data rate), because there is less bus
contention.
A disadvantage is the increased size and cost of the
system.
13
Multiplexed Bus
2. Multiplexed bus line: Using the same set of lines for
multiple purposes and multiple modules is known as time
multiplexing.
 For example, address and data information may be
transmitted over the same set of lines using an Address
Valid control line.
 First place address, each module copies address and
determines if it’s the addressed module. The address is
removed from the bus and the same bus is used for the
subsequent read or write data transfer.
 The advantage is the use of fewer lines, which saves space
and cost.
 Disadvantage, more complex circuitry is needed within each
module.
 There is a reduction in performance because certain events
that share the same line cannot take place in parallel.
14
Method

of Arbitration & Its Types
In multiplexed, more than one module may need control of the
bus.
 The purpose of arbitration is to designate one device as
master/slave.
 Because only one unit can successfully transmit over the bus,
some method of arbitration is needed (to gain control of the
bus).
 The two arbitration methods can be classified as:
1) Centralized arbitration (e.g. CPU) 2) Distributed
arbitration
1. Centralized arbitration: a single hardware device, called an
arbiter or bus controller, is responsible for allocating time on
the bus. CPU.
2. Distributed arbitration: there is no central controller.
Rather, each module contains access control logic and the
modules act together to share the bus. (e.g. they sense if line
is available or not) 15
Bus Timing & Its Types
 In centralized arbitration, each device is allocated time on the
bus.
 Timing refers to the way in which events are coordinated on
the bus.
 Buses use two types of timing:
1) Synchronous timing 2) Asynchronous timing
1. Synchronous timing: The occurrence of events on the bus
is determined by a clock. It uses ‘Time multiplexing’
technique.
 It is simpler to implement and test, however it is less flexible
(fixed Cl)
2. Asynchronous timing: the occurrence of one event on a
bus follows and depends on the occurrence of a previous
event.
 Advantage, a mixture of slow and fast devices, can share a
bus.
16
Timing of Synchronous Bus Operation
With Synchronous bus timing
 Events determined by clock signals
 Control Bus includes clock line
 A single 1-0 is a bus/clock cycle, ‘time slot’.
 All devices can read clock line
 Usually sync on leading edge
 Usually a single cycle for an event
In a simple example, the processor places a
memory address on the address line during the
first clock cycle, it may assert status symbols.
Once the address lines have stabilized, the
processor issues an address enable signal. 17
See Synchronous Timing Figure (Next Slide)
For read operation, the processor issues a read
command at the start of the second cycle.
A memory module recognizes the address and,
after a delay of one cycle, places the data on the
data lines.
The processor reads the data from the data lines
and drops the read signal.
For a write operation, the processor puts the data
on the data lines at the start of the second cycle
and issues a write command.
The memory module copies the information from
the data lines during the third clock cycle.
18
 1st cycle 2nd cycle3rd cycle

1 1 1
0 0 0
Synchronous
Bus Timing (Bus is
1st cycle place Busy)
Read Operation Sequence:
1. Place memory address on address line.
2. Issues ‘address enable’ signal. 1
3. Issues ‘read’ single in 2nd cycle. Address
4. Memory module recognizes address. enable
Data placed
5. Places data on ‘data lines’, 3rd cycle.
Read=1
Second cycle
‘Address’ is placed on Address bus.
Data placed
Data copied
Write Operation Sequence:
1. Processor puts ‘data’, 2nd cycle.
2. Then issues a ‘write’ command. Write=1
3. Memory module copies data Write
from ‘data lines’ in 3rd cycle. Enabled

19
Asynchronous Read Operation
Step-1 (Bus is
Steps of Asynchronous Read Busy)
Operation:
1. The processor places
‘address’ and ‘status’ signals.
2. Then it issues a read
Step-2: Read
command.
command
3. The memory decodes
address Step-3:
and places the data on the Places
‘data line’. data
4. Memory gives Step-4: Ack signal
‘acknowledge’ signal.
5. Master reads data, removes
read.
6. Memory drops data and Ack
signal.
7. The master removes the 20
 Asynchronous Write Operation
Steps of Asynchronous Write
Operation:
1. Master simultaneously
places data,
status and address on
respective lines.
2. Then it issues the ‘Write’
command.
3. Memory module copies the
data.
4. Then it asserts the
acknowledge line.
5. Master drops the write
signal.
6. Memory drops the
21
acknowledge signal.
Read for Knowledge
Hardware interrupts are asynchronous and can
occur in the middle of instruction execution,
requiring additional care in programming. The
act of initiating a hardware interrupt is referred
to as an interrupt request (IRQ).
Each interrupt has its own interrupt handler. The
number of hardware interrupts is limited by the
number of interrupt request (IRQ) lines to the
processor, but there may be hundreds of different
software interrupts. Interrupts are a commonly
used technique for computer multitasking,
especially in real-time computing. Such a system
is said to be interrupt-driven.
22
Preparatory Questions
1. What are the two ‘types of interrupts’? Explain.
2. What are the different ‘classes of interrupts’?
3. Write down the steps of ‘interrupt handler
process’.
4. List and briefly define two approaches to dealing
with ‘multiple interrupts’.
5. What is the ‘limitation’ of a bus design?
6. Explain the ‘bus operation’ for a read & write
operation, using ‘bus request’ signal.
7. What is a ‘system bus’? Explain its three
constituent buses.
8. List the different ‘elements of a bus design’.
(Bus-type, method of arbitration, timing).
23