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UNIT-V - Peephole and Code Generator

Peephole optimization is a code optimization technique that improves performance by examining and replacing short sequences of target instructions. Key characteristics include eliminating redundant instructions, unreachable code, flow-of-control optimizations, algebraic simplifications, and utilizing machine idioms. The document also discusses code generation for various statements, including assignment, indexed, and pointer assignments, along with the use of register and address descriptors.

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0% found this document useful (0 votes)
25 views19 pages

UNIT-V - Peephole and Code Generator

Peephole optimization is a code optimization technique that improves performance by examining and replacing short sequences of target instructions. Key characteristics include eliminating redundant instructions, unreachable code, flow-of-control optimizations, algebraic simplifications, and utilizing machine idioms. The document also discusses code generation for various statements, including assignment, indexed, and pointer assignments, along with the use of register and address descriptors.

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2021it0080
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IT16604 – Automata and

Compiler Design
UNIT-V
Peephole Optimization
• Peephole optimization is a type of code optimization
performed on a small part of the code. It is performed on
the very small set of instructions in a segment of code.

• A method for trying to improve the performance of the


target program by examining a short sequence of target
instructions (called the peephole) and replacing these
instructions by a shorter or faster sequence, whenever
possible.

• Peephole - small, moving window on the target program.


characteristic of peephole optimizations
• Redundant-instructions elimination
• Unreachable Code
• Flow-of-control optimizations
• Algebraic simplifications and Reduction in Strength
• Use of machine idioms
Redundant-instructions elimination
• If we see the instruction sequence
– LD R0, a
– ST a, R0 in a target program
• we can delete the store instruction because whenever it is executed,
the first instruction will ensure that the value of a has already been
loaded into register R0.

• Note that if the store instruction had a label, we could not be sure
that the first instruction is always executed before the second, so we
could not remove the store instruction.
– LD R0, a
– L1: ST a, R0
• i.e, the two instructions have to be in the same basic block for this
transformation to be safe.
Redundant-instructions elimination

• Initial code:
y = x + 5;
i = y;
z = i;
w = z * 3;
Optimized code:
y = x + 5;
i = y;
w = y * 3;
Eliminating Unreachable code
• An unlabeled instruction immediately following
an unconditional jump may be removed.
if debug == 1 goto L1
goto L2
L1: print debugging information
L2:
Optimized Code
if debug != 1 goto L2
print debugging information
L2:
Eliminating Unreachable code
void add(int x)
{
return x + 10;
printf(“value of x is %d”, x);
}
the printf statement will never be executed as
the program control returns back before it can
execute, hence printf can be removed.
Flow-of-control optimizations
• Simple intermediate code-generation algorithms frequently produce jumps
to jumps, jumps to conditional jumps, or conditional jumps to jumps.

• These unnecessary jumps can be eliminated in either the intermediate code


or the target code by the following types of peephole optimizations.
• We can replace the sequence
goto L1

L1: goto L2

• by the sequence
goto L2

L1: goto L2
Flow-of-control optimizations

• Similarly, the sequence


if a < b goto L1

L1: goto L2

can be replaced by the sequence


if a < b goto L2

L1: goto L2
Algebraic simplifications and Reduction in Strength

• Algebraic identities can be used by a peephole


optimizer to eliminate three-address statements such as
x=x+0
x=x*1
in the peephole.
• Reduction-in-strength transformations can be applied in
the peephole to replace expensive operations by
equivalent cheaper ones on the target machine.
x2 = x * x
2x = x + x
Use of machine idioms
• The target machine may have hardware instructions to
implement certain specific operations efficiently.
• For example, some machines have auto-increment and auto-
decrement addressing modes. These add or subtract one from
an operand before or after using its value.
• The use of these modes greatly improves the quality of code
when pushing or popping a stack, as in parameter passing.
These modes can also be used in code for statements like
• x=x+1 → x++
• x:=x-1 → x- -
Simple Code Generator
• A code generator generates target code for a sequence of
three- address statements and effectively uses registers to
store operands of the statements.
• consider the three-address statement
a := b+c

It can have the following sequence of codes:


ADD Rj, Ri Cost = 1 // if Ri contains b and Rj contains c (or)

ADD c, Ri Cost = 2 // if c is in a memory location (or)

MOV c, Rj Cost = 3 // move c from memory to Rj and add


ADD Rj, Ri
Register and Address Descriptors
• A register descriptor is used to keep track of what is
currently in each registers. The register descriptors
show that initially all the registers are empty.

• An address descriptor stores the location where the


current value of the name can be found at run time.
A code-generation algorithm
• The algorithm takes as input a sequence of three-address statements
constituting a basic block.
• For each three-address statement of the form x : = y op z, perform the
following actions:
1. Invoke a function getreg to determine the location L where the result of the
computation y op z should be stored.
2. Consult the address descriptor for y to determine y’, the current location of
y. Prefer the register for y’ if the value of y is currently both in memory
and a register. If the value of y is not already in L, generate the instruction
MOV y’ , L to place a copy of y in L.
3. Generate the instruction OP z’ , L where z’ is a current location of z. Prefer
a register to a memory location if z is in both. Update the address
descriptor of x to indicate that x is in location L. If x is in L, update its
descriptor and remove x from all other descriptors.
4. If the current values of y or z have no next uses, are not live on exit from
the block, and are in registers, alter the register descriptor to indicate that,
after execution of x : = y op z , those registers will no longer contain y or z.
Generating Code for Assignment
Statements
• The assignment d : = (a-b) + (a-c) + (a-c)
• Translated to three address code sequence:
t:=a–b
u:=a–c
v:=t+u
d:=v+u
with d live at the end.
Code sequence
Statements Code Generated Register Address
descriptor descriptor
Register empty
t:=a-b MOV a, R0 R0 contains t t in R0
SUB b, R0
u:=a-c MOV a , R1 R0 contains t t in R0
SUB c , R1 R1 contains u u in R1
v:=t+u ADD R1, R0 R0 contains v u in R1 v in R0
R1 contains u
d:=v+u ADD R1, R0 R0 contains d d in R0
MOV R0, d d in R0 and
memory
Generating Code for Indexed Assignments
• code sequences generated for the indexed assignment
statements
a : = b [ i ] and a [ i ] : = b

Statements Code Generated Cost


a : = b[i] MOV b(Ri), R 2
a[i] : = b MOV b, a(Ri) 3
Generating Code for Pointer Assignments

• code sequences generated for the pointer


assignments
a : = *p and *p : = a
Statements Code Generated Cost
a : = *p MOV *Rp, a 2
*p : = a MOV a, *Rp 2
Generating Code for Conditional
Statements
Statement Code
if x < y goto z CMP x, y
CJ< z /* jump to z if condition code is
negative */
x : = y +z MOV y, R0
if x < 0 goto z ADD z, R0
MOV R0,x
CJ< z

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