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Lecture 9 Truth Tables

The document covers topics in Digital Logic Design, including truth table construction, incompletely specified functions, and the design of adders and subtractors. It provides examples of binary adders, specifically half-adders and full-adders, and discusses the use of don't care conditions in simplifying logical expressions. The next lecture will focus on Karnaugh Maps.

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Tilahun Eirku
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41 views10 pages

Lecture 9 Truth Tables

The document covers topics in Digital Logic Design, including truth table construction, incompletely specified functions, and the design of adders and subtractors. It provides examples of binary adders, specifically half-adders and full-adders, and discusses the use of don't care conditions in simplifying logical expressions. The next lecture will focus on Karnaugh Maps.

Uploaded by

Tilahun Eirku
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd

ENDD 200 Digital Logic Design

Truth Tables, Incomplete Functions , & Full


Adders

Wed, January 28 DLD 200 Digital Logic Design Slide 1 of 10


Chapter in textbook 4

CLOs 2

Friday, January 9 ENDD 200 Digital Logic Design Slide 2 of 16


Lecture Outline

• Examples of Truth Table Construction


• Incompletely Specified Functions
• Design of Adders and Subtractors

Wed, January 28 DLD 200 Digital Logic Design Slide 3 of 10


Examples of Truth Table Construction

• Design a binary adder that adds two 1-bit binary


numbers (A and B) to give a 2-bit sum (X Y)
A B XY
0 0 00
A X A
B + Y
+B
XY
0
0
1
1
1
1
0
0
01
01
1 1 10
1 1

This device is X A B
sometimes called
a half-adder Y  A B  AB
A  B

Wed, January 28 DLD 200 Digital Logic Design Slide 4 of 10


Examples of Truth Table Construction

• Design a binary adder that


adds two UNSIGNED 2-bit
binary numbers to form a 3-
bit sum.

AB
+CD
XYZ

X= S m (7,10,11,13,14,15)
Y= S m (2,3,5,6,8,9,12,15)
Z= S m (1,3,4,6,9,11,12,14)
Wed, January 28 DLD 200 Digital Logic Design Slide 5 of 10
Design of Adders and Subtracters
A Binary Adder
• Design a 1-bit Full-Adder A B Cin Cout S
0 0 0 0 0
0 0 1 0 1
A 0 1 0 0 1
+B 0 1 1 1 0
+ Cin 1 0 0 0 1
Cout S 1 0 1 1 0
1 1 0 1 0
= Sum 1 1 1 1 1

Cout  ABCin  ABCin  ABCin  ABCin S  ABCin  ABCin  ABCin  ABCin


 ACin  BCin  AB   
 A BCin  BCin  A BCin  BCin 
 A  B  Cin   A B  C  in

 A   B  Cin 
Wed, January 28 DLD 200 Digital Logic Design Slide 6 of 10
Incompletely Specified Functions

• The four inputs to a circuit (A,B,C,D) 0


1
represent an 8-4-2-1 BCD digit. 2
The output should be 1 iff the 3
decimal number represented by the 4
5
inputs is exactly divisible by three 6
(i.e. a remainder of “0”). 7
 Assume that only valid BCD digits 8
occur as inputs. 9

These inputs will not occur.


Do I care what the associated outputs are?

Z  m(0,3, 6,9)  d (10,11,12,13,14,15)


Wed, January 28 DLD 200 Digital Logic Design Slide 7 of 10
Incompletely Specified Functions

• Consider the truth table


A B C F
 If we make both don’t cares “0”
0 0 0 1
F  ABC  ABC  ABC  ABC  BC 0 0 1 X
1
0
 If we make a “1” and a “0” 0 1 0 0
0 1 1 1
F  ABC  ABC  ABC  ABC  AB  BC 1 0 0 0
 If we make a “0” and a “1” 1 0 1 0

F  ABC  ABC  ABC  ABC  ABC  BC  AB 1 1 0 X


1
0
1 1 1 1
 If we make a “1” and a “1”
F  ABC  ABC  ABC  ABC  ABC
 AB  BC  AB
We can select the “don’t cares” to make our expression simpler!!
Wed, January 28 DLD 200 Digital Logic Design Slide 8 of 10
• Midterm until here

Wed, January 28 DLD 200 Digital Logic Design Slide 9 of 10


Next Lecture

• Karnaugh Maps

Wed, January 28 DLD 200 Digital Logic Design Slide 10 of 10

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