General Register Organization

The registers communicate with each other not only for direct data transfers, but also while performing

various microoperations. Hence it is necessary to provide a common unit that can perform all the

arithmetic, logic, and shift microoperations in the processor. The output of each register is connected to

two multiplexers (MUX) to form the two buses A and B. The selection lines in each multiplexer select one

register or the input data for the particular bus. The A and B buses form the inputs to a common arithmetic

logic unit (ALU). The operation selected in the ALU determines the arithmetic or logic microoperation that

is to be performed. The result of the microoperation is available for output data and also goes into the

inputs of all the registers.

register load inputs, thus providing a transfer path between the data in the output bus and the inputs of the selected

destination register. The control unit that operates the CPU bus system directs the information flow through the registers

and ALU by selecting the various components in the system. For example, to perform the operation R1 <--R2 + R3 the

control must provide binary selection variables to the following selector inputs: 1. MUX A selector (SELA): to place the

content of R2 into bus A. 2. MUX B selector (SELB): to place the content o f R 3 into bus B. 3. ALU operation selector (OPR):

to provide the arithmetic addition A+ B. 4. Decoder destination selector (SELD): to transfer the content of the output bus

into R 1. The four control selection variables are generated in the control unit and must be available at the beginning of a

clock cycle. The data from the two source registers propagate through the gates in the multiplexers and the ALU, to the

output bus, and into the inputs of the destination register, all during the clock cycle interval. Then, when the next clock

transition occurs, the binary information from the output bus is transferred into R 1.
The 3-bit binary code listed in the first column of the table
specifies the binary code for each of the three fields. The register
selected by fields SELA, SELB, and SELD is the one whose decimal
number is equivalent to the binary number in the code. When
SELA or SELB is 000, the corresponding multiplexer selects the
external input data. When SELD = 000, no destination register is
selected but the contents of the output bus are available in the
external output.
Stack Organization
A useful feature that is included in the CPU of most computers is a stack or last-in, first-out (UFO) list. A stack is a
storage device that stores information in such a manner that the item stored last is the first item retrieved. The
operation of a stack can be compared to a stack of trays. The last tray placed on top of the stack is the first to be taken
off The register that holds the address for the stack is called a stack pointer (SP) because its value always points at the
top item in the stack. The two operations of a stack are the insertion and deletion of items. The operation of insertion is
called push (or push-down) because it can be thought of as the result of pushing a new item on top. The operation of
deletion is called pop (or pop-up) because it can be thought of as the result of removing one item so that the stack pops
up.
In a 64-word stack, the stack pointer contains 6 bits because 2 6 = 64. Since SP has only six bits, it cannot exceed a
number greater than 63 (111111 in binary). When63 is incrementedby 1, the resultis 0 since 111111 + 1 = 1000000 in
binary, but SP can accommodate only the six least significant bits. Similarly, when 000000 is decremented by 1, the
result is 111111. The one-bit register FULL is set to 1 when the stack is full, and the one-bit register EMTY is set to 1
when the stack is empty of items
DR is the data register that holds the binary data to be written into or
read out of the stack. Initially, SP is cleared to 0, EMTY is set to 1, and
FULL is cleared to 0, so that SP points to the word at address 0 and the
stack is marked empty and not full. If the stack is not full (if FULL = 0), a
new item is inserted with a push operation.
Instruction Formats
The format of an instruction is usually depicted in a rectangular box symbolizing the bits of the instruction as they appear
in memory words or in a control register. The bits of the instruction are divided into groups called fields. The most common
fields found in instruction formats are: 1. An operation code field that specifies the operation to be performed. 2. An
address field that designates a memory address or a processor register. 3. A mode field that specifies the way the operand
or the effective address is determined.
Three-Address Instructions
Computers with three-address instruction formats can use each address field to specify either a processor register or a
memory operand. The program in assembly language that evaluates X = (A + B) • (C + D) is shown below, together with
comments that explain the register transfer operation of each instruction.
Two-Address Instructions
Two-address instructions are the most common in commercial computers. Here again each address field can specify
either a processor register or a memory word. The program to evaluate X = (A + B) • (C + D) is as follows:

One-Address Instructions
One-address instructions use an implied accumulator (AC) register for all data manipulation. For multiplication and
division there is a need for a second register. However, here we will neglect the second register and assume that the AC
contains the result of all operations. The program to evaluate X = (A + B) • (C + D) is
Zero-Address Instructions
A stack-organized computer does not use an address field for the instructions ADD and MUL. The PUSH and POP
instructions, however, need an address field to specify the operand that communicates with the stack. The following
program shows how X = (A + B) • (C + D) will be written for a stack organized computer. (TOS stands for top of stack.)
Addressing Modes
Computers use addressing mode techniques for the purpose of accommodating one or both of the following provisions:
1. To give programming versatility to the user by providing such facilities as pointers to memory, counters for loop control,
indexing of data, and program relocation.
2. To reduce the number of bits in the addressing field of the instruction

Implied Mode: In this mode the operands are specified implicitly in the definition of the instruction. For example, the
instruction "complement accumulator" is an implied-mode instruction because the operand in the accumulator register is
implied in the definition of the instruction. In fact, all register reference instructions that use an accumulator are implied-
mode instructions. Zero-address instructions in a stack-organized computer are implied-mode instructions since the
operands are implied to be on top of the stack.
Immediate Mode:
In this mode the operand is specified in the instruction itself. In other words, an immediate-mode instruction has an
operand field rather than an address field. The operand field contains the actual operand to be used in conjunction with
the operation specified in the instruction. Immediate-mode instructions are useful for initializing registers to a constant
value.
Register Indirect Mode:
In this mode the instruction specifies a register in the CPU whose contents give the address of the operand in memory. In
other words, the selected register contains the address of the operand rather than the operand itself.
Autoincrement or Autodecrement Mode:
This is similar to the register indirect mode except that the register is incremented or decremented after (or before) its
value is used to access memory. When the address stored in the register refers to a table of data in memory, it is
necessary to increment or decrement the register after every access to the table. This can be achieved by using the
increment or decrement instruction.
The effective address is defined to be the memory address obtained from the computation dictated by the given
addressing mode. The effective address is the address of the operand in a computational- type instruction. It is the
address where control branches in response to a branch-type instruction.
Direct Address Mode:
In this mode the effective address is equal to the address part of the instruction. The operand resides in memory and its
address is given directly by the address field of the instruction. In a branch-type instruction the address field specifies the
actual branch address.
Indirect Address Mode:
In this mode the address field of the instruction gives the address where the effective address is stored in memory.
Control fetches the instruction from memory and uses its address part to access memory again to read the effective
address.
Relative Address Mode:
In this mode the content of the program counter is added to the address part of the instruction in order to obtain the
effective address. The address part of the instruction is usually a signed number (in 2' s complement representation)
which can be either positive or negative. When this number is added to the content of the program counter, the result
produces an effective address whose position in memory is relative to the address of the next instruction.
Relative addressing is often used with branch-type instructions when the branch address is in the area surrounding the
instruction word itself. It results in a shorter address field in the instruction format since the relative address can be
specified with a smaller number of bits compared to the number of bits required to designate the entire memory address.
Indexed Addressing Mode:
In this mode the content of an index register is added to the address part of the instruction to obtain the effective
address. The index register is a special CPU register that contains an index value. The address field of the instruction
defines the beginning address of a data array in memory. Each operand in the array is stored in memory relative to the
beginning address. The distance between the beginning address and the address of the operand is the index value stored
in the index register.
Base Register Addressing Mode:
In this mode the content of a base register is added to the address part of the instruction to obtain the effective address.
This is similar to the indexed addressing mode except that the register is now called a base register instead of an index
register. The difference between the two modes is in the way they are used rather than in the way that they are
computed. An index register is assumed to hold an index number that is relative to the address part of the instruction. A
base register is assumed to hold a base address and the address field of the instruction gives a displacement relative to
this base address.
In the direct address mode the effective address is
the address part of the instruction 500 and the
operand to be loaded into AC is 800. In the
immediate mode the second word of the
instruction is taken as the operand rather than an
address, so 500 is loaded into AC. (The effective
address in this case is 201 .) In the indirect mode
the effective address is stored in memory at
address 500. Therefore, the effective address is 800
and the operand is 300. In the relative mode the
effective address is 500 + 202 = 702 and the
operand is 325. (Note that the value in PC after the
fetch phase and during the execute phase is 202.) In
the index mode the effective address is XR + 500 =
100 + 500 = 600 and the operand is 900. In the
register mode the operand is in R 1 and 400 is
loaded into AC. (There is no effective address in this
case.) In the register indirect mode the effective
address is 400, equal to the content of R 1 and the
operand loaded into AC is 700.