Combinational Standard Modules

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 Part III. Standard Modules

Interconnect Modules:
1. Decoder, 2. Encoder
3. Multiplexer, 4. Demultiplexer

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 Multiplexer
• Definition
• Logic Diagram
• Application

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 3. Mux (Multiplexer): Definition

En Description
If En = 1
y = Di where i = (Sn-1, .. , S0)
D2n-1-D0 Else
y y=0
(Data input)

Sn-1,0
(Control input)

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 Multiplexer (Mux): Definition
• Selects between one of N inputs to
connect to the output.
• log2N-bit select input – control input
S
• Example: D0
2:1 Mux
0
Y
D1 1

S D1 D0 Y S Y
0 0 0 0 0 D0
0 0 1 1 1 D1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
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Multiplexer Definition: Example
En

D0 0
If D0 = 0 and S1S0 = 00 => y = 0
If D0 = 1 and S1S0 = 00 => y = 1
D1 1
y
D2 2

D3 3

S1 S0

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 Multiplexer: Logic Diagram
• Logic gates • Tristates
– Sum-of-products form – For an N-input mux,
use N tristates
Y
D0 D1
00 01 11 10
– Turn on exactly one to
S
0 0 0 1 1 select the appropriate
1 0 1 1 0 input
Y = D0S + D1S
S

D0 D0

D1
S
D1

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 Multiplexer Application
• Mux for a Boolean function with
truth table as input A B Y
0 0 0
0 1 0
1 0 0
1 1 1
Y = AB
AB
00
01
10
Y
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 Multiplexer: Application

A
A B Y A Y
0 0 0
0 0 0
0 1 0 Y
Y = AB 1 0 0 1 B B 1
1 1 1

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Multiplexer Application: universal set {Mux}
Example 1: Given f (a,b,c) = m (0,1,7) + d(2), implement
with an 8-input Mux.

En

Id a b c f 1 0
1 1
0 0 0 0 1 0 2
1 0 0 1 1 0 3
2 0 1 0 -
0 4 y
0 5
3 0 1 1 0 0 6
1 7
4 1 0 0 0
5 1 0 1 0 S2 S1 S0
6 1 1 0 0
7 1 1 1 1
a b c
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Multiplexer Application
Example 2: Given f (a,b,c) = m (0,1,7) + d(2), implement
with 4-input Muxes.
En

a b c=0 c=1 D (c)

a b

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Multiplexer Application
Example 3: Given f (a,b,c) = m (0,1,7) + d(2), implement
with 2-input Muxes.
a 00 01 10 11 D (b,c)

0 1 1 - 0 D0 (b,c) En
1 0 0 0 1 D1 (b,c)

En b’ 0
D0 (b,c) = b’ D1 (b,c) = bc y
1 - 0 0 0 0 1

c 1 0 c 0 1
c 1

b b a
D1 (b,c) b
b c=0 c=1

0 0 0 l1(0) = 0
1 0 1 l1(c) = c
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 4. Demultiplexers

En
yi = x if i = (Sn-1, .. , S0) & En = 1
yi = 0 otherwise

x y2n-1 -y0

S(n-1,0)
Control Input

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 Shifter
xn xn-1 x0 x-1
yi = xi-1 if En = 1, s = 1, and d = L
s s/n En = xi+1 if En = 1, s = 1, and d = R
d l/r = xi if En = 1, s = 0
= 0 if En = 0
yn-1 y0
xi+1 xi xi-1
Can be implemented with a mux

s 1 3 2 1 0
En
d 0

yi
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 Barrel Shifter

shift x

0 1 0 1 0 1
s0 O or 1 shift

s1 O or 2 shift
0 1 0 1 0 1 0 1 0 1

s2 O or 4 shift

y 0 1 0 1 0 1 0 1 0 1 0 1

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