Hardware view of the Embedded

Systems-2
Lecture-3
Memory
• important part of ES
– onchip memory,off chip memory
– working memory-to hold data for a while
• review of memory aspects
– Data stored-byte(one address to one byte)
– Memory devices with 16 bits-each 16 bit data
has one address
– Memory access time-reading/writing time
– Memory cycle time-time interval between two
memory access
Types of Memory
• ROM
– PROM
– MROM
– EPROM
– EEPROM
– FLASH
• RAM
– SRAM
– DRAM
ROM( Read Only Memory)
• Stores the program instruction
• Also called as program storage memory
or code memory
• Retains the contents even after the power
is turmed off
• Non-volatile storage memory
Types of ROM
 PROM
 MROM
 EPROM
 EEPROM
 FLASH
PROM
• Programmable ROM or called as One
Time Programmable Memory (OTP)
• Can be programmed by end user
• Memory has nichrome or polysilicon wires
arranged in matrix - wires act as fuses
• NOT BLOWN = 1
• BLOWN fuses = 0
• Default state is logic 1
MROM
• Masked ROM
• One time proramable device
• Handwired technology to store data
• Programmable by masking and
mettalisation
• Low cost for high volume production
EPROM
• Erasable Programmable ROM
• Flexibility to re-program
• Stores the bit information by charging a
floating gate of FET - applying high
voltage to charge the floating gate
• Contains quartz crystal window for
erasing the stored information and when
exposed to UV for a certain time, entire
memory will be erased
• Tedious and time consuming to erase
EEPROM
• Electrically EPROM
• Memory can be erased by electrical
signals
• Erasing can be done in ms
• Greater flexibility for system design
• Capacity is limited
FLASH
• Popular ROM technology (Latest too)
• Combination of EEPROM with high
capacity
• Stores information in an array of memory
cells of floating gate MOSFETs
• Memory is organised as sectors or blocks
or pages
• erasing can be done at sector level
without affecting other sectors
Ex: SST39LF010 from microchip-
1M bit organised as 128K*8.
Flash Memory Cell structure
• stores data in an array of memory cells made from
floating-gate MOSFETS (known as FGMOS).
• stores an electrical charge for extended periods of time
(2 to 10 years) even without a connecting to a power
supply.
• FGMOS is fabricated by electrically isolating the gate of
a standard MOS transistor, so that there are no resistive
connections to this gate (floating gate)
• A secondary gate/ control gate is then deposited above
this floating gate and is electrically isolated from it using
an insulator like Si02.
• So, in terms of its DC operating point, the FG is a
floating node.
Principle of data storage in FLASH

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Working principle
• Flash stores the data by removing or putting electrons on
its floating gate
• Charge on floating gate affects the threshold of the
memory element.
• When electrons are present on the floating gate, no
current flows through the transistor, indicating a logic-0.
When electrons are removed from the floating gate, the
transistor starts conducting, indicating a logic-1.
• This is achieved by applying voltages between the
control gate and source or drain.
• Tunneling(NAND) and hot electron injection(NOR) -
processes where electrons are transported through a
barrier( thickness of the Si02 insulator layer surrounding
the floating gate).
https://r2.community.samsung.com/t5/Tech-Talk/Flash-memory/td-p/4457583
• A typical flash-array has a grid of columns and rows of
FGMOS-transistor cells
• The word line (WL) is the horizontal line and bit line (BL)
is the vertical line
• The Control gates of the FGMOS cells are connected to
the word-line WL. The decoded address is actually
applied to this word-line.
• The bit line BL connects drains of the FGMOS cells
together and represent data bus.
• The Source-line (SL) connects sources of the FGMOS
to common ground.
• The voltage combinations applied to WL and BL define
an operation, whether it is read, erase or program.
https://semiwiki.com/wikis/semiconductor-ip-wikis/non-volatile-memory-nvm-
wiki/
http://www.eeherald.com/section/design-guide/esmod16.html
Erase operation(0 1)
• Default state of flash memory cells will be bit 1's because
floating gates carry no negative charges.
• Erasing a flash-memory cell(reset to 1) is achieved by
applying a voltage across the source and control gate
(word line) in the range of -9V to -12V.
• Around 6V to the source.
• The electrons in the floating gate are pulled off and
transferred to the source by quantum tunneling (a tunnel
current).
Write(program) operation (1 0)
• While writing a high voltage of around 12V is applied to
the control gate (word line).
• If high voltage around 7V is applied to Bit Line (Drain
terminal), bit 0 is stored in the cell.
• The channel is now turned on, so electrons can flow
from the source to the drain.
• Through the thin oxide layer electrons move to the
floating gate.
• The source-drain current is sufficiently high to cause
some high-energy electrons to jump through the
insulating layer onto the floating gate
• Due to applied voltage at floating-gate the excited
electrons are forced through and trapped on other side
of the thin oxide layer, giving it a negative charge on the
floating gate.
• These negatively charged electrons act as a barrier
between the control gate and the floating gate.
• Since floating gate is insulated by oxide, the charge
accumulated on the floating gate will not leak out, even if
the power is turned off.
• If low voltage is applied to the drain via the bit line, the
amount of electrons on the floating gate remains the
same, and logic state doesn't change, storing the bit 1.
Read operation
• Apply a voltage around 5V to the control gate and
around 1V to the drain.
• The state of the memory cell is distinguished by the
current flowing between the drain and the source.
• To read the data, a voltage is applied to the control gate,
and the MOSFET channel will be either conducting or
remain insulating, based on the threshold voltage of the
cell, which is in turn controlled by charge on the floating
gate.
• The current flow through the MOSFET channel is sensed
and forms a binary code, reproducing the stored data.
Types of FLASH
• NOR FLASH-Intel
– flash cells connected in parallel to bit
lines-reading/writing/erasing cell
individually
– READ-relatively higher speed
– WRITE/ERASE-relatively slower(erase
block-64 to 128 KB)
– random access is possible
– program code of ES is stored
– Ex:BIOS in PCs
• NAND FLASH-Toshiba
– flash cells connected in series
– READ-relatively slower speed
– WRITE/ERASE-relatively faster(erase
block-8 to 32 KB-smaller erase blocks)
– sequential access(unsuitable for
Processors or controllers as they require
random access)
– data read/write only as blocks-good
storage density
– Ex:digital camera,MP3 players,USB,SD
cards
http://www.eeherald.com/section/design-guide/esmod16.html
RAM
• Read-Write Memory/ Random Access
Memory
• Data memory or working memory of the
controller or processor
• Controller/ processor can read from it and
write to it
• RAM is volatile ( when power off, data is
lost)
• Memory location can be directly accessed
Types of RAM
 SRAM
SSRAM-Synchronous SRAM-Processor
clocks generate timing for READ and WRITE
 DRAM
SDRAM-Synchronous DRAM-shares the bus
clock with the CPU
SRAM-Static RAM
• Holds either 1 or 0
• static content as stored as a voltage(does
not change with time)
• Fastest RAM
• Realized using 6 MOSFETS for one bit

2 to control the
4 to build the latch(flipflop)
access
SRAM cell

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Working of SRAM cell to store one bit
• M1 and M3-bistable multivibrator with M2
and M4 as loads
• output of circuit is M2 or M4
• No READ/WRITE-WL is low--- M5 and M6
are OFF
• WRITE---BL and BL are high-M5 and M6
are ON by setting WL to high
• After storing info in bistable
multivibrator,M5 and M6 willbe put OFF
• READ-WL is ON to activate M5 and M6
when info is sensed at bit lines
SRAM chip

D0
A0

RAM

An-1 D7

OS
WE

CS
• N address lines,8 data lines,control signals
for reading and writing
• Chip Signal(CS) activated to enable the
chip
• WE-write control signal ,OS(output signal)-
read control signal which enables data
lines for reading
• tRC-read cycle time;t1-read access
time(minimum time between two read
cycles)
 Timing diagram of SRAM
tRC

Data Valid

Data
hold
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DRAM

• Dynamic RAM
• Stores data in the form of charge
• Made of MOS transistor gates
• High density and low cost
• As data store is in form of charge, it can
leak off with time and so has to be
refreshed periodically
• Memory is in the form of matrix
DRAM cell
Word
line

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Working of DRAM
• Bit cells of the dynamic RAM memory are built
based on the electric charge storing in
condensers.
• A bit cell constitutes a transistor with a
condenser interconnected to the line that selects
a memory row and to the bit line in the word (bit
read and write lines).
• A write takes place as a result of row line
selection (positive voltage) and insertion through
a bit line of the voltage that corresponds to the
stored bit: 0V for logical zero and the positive
voltage for one.
https://edux.pjwstk.edu.pl/mat/264/lec/main93.html
• For logical one, the condenser will charge through the
conducting transistor to the positive voltage.
• For zero, the transistor will be turned off and the
condenser will discharge if loaded or it will remain not
charged (in both cases the condenser plate at the
transistor side will reach 0V potential).
• For read, a row line will be set to the positive potential
and the transistor will be turned on.
• If the condenser was charged (the bit cell was storing
one), the positive voltage from the condenser plate will
be transferred into the bit line (readout of one) after
which the condenser discharges through the bit line.
• If the condenser was not charged, 0V will be transferred
to the bit line i.e. a logical zero, stored in this cell.
DRAM chip
• Many DRAM cells form words consisting
of bits
• Memory address are decoded and
converted as rows and columns of the
matrix that memory elements are arranged
in.
• When processor addresses memory on
address pins,memory controller inbetween
processor and DRAM chip splits address
into rows and columns
• A DRAM has only half the number of
address pins as address lines of the
DRAM chip are multiplexed in time for the
row and column addresses
• Memory controller generates signals for
reading and writing from/to DRAM
• DRAM chips are large rectangular arrays
of memory cells arranged in rows and
columns
• Each memory cycle has unique location or
address defined by the intersection of a
row and a column
Timing diagram of DRAM
• READ cycle
– Row address is placed on the rows ,sufficient
time given to stabilize and be latched
– row address pin RAS is activated
– row address decoder selects the proper row
– Column address is placed on the
rows ,sufficient time given to stabilize and be
latched
– column address pin CAS is activated
– column address decoder selects the proper
column
– CAS pin also serves as output enable pin
– Now data in the selected address is available
for output buffer to transfer to the data bus
Which memory in the processor chips
used in ES
• small amount of SRAM with reatively large
amount of FLASH
• SRAM-small amount of storage for
intermediate data during computations
• FLASH-code is burned(part of FLASH can
be used for data storage too)
• Ex:PIC 18 F series
– SRAM size-4KB
– FLASH-128KB
– EEPROM-1024 bytes