EEEN 103 Digital System Design and

Microprocessors

Microprocessor Basics

Fall 2024
 Inside the Computer
terminology
• A bit is a binary digit that can have the value 0 or 1.

• A nibble is 4 bits.
• A byte is defined as 8 bits.
• A word is two bytes, or 16 bits.

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 Inside the Computer
terminology
• A kilobyte is 210 bytes, which is 1,024 bytes.
– The abbreviation K is often used to represent kilobytes.
• A megabyte, or meg, is 220 bytes.
– A little over 1 million bytes; exactly 1,048,576 bytes.
• A gigabyte is 230 bytes (over 1 billion).
• A terabyte is 240 bytes (over 1 trillion).

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 Inside the Computer
two common memory types
• RAM - which stands for “random access memory”
(sometimes called read/write memory).
– Used for temporary storage of programs while running.
• Data is lost when the computer is turned off.
• RAM is sometimes called volatile memory.
• ROM - stands for “read-only memory”.
– Contains programs and information essential to the operation of the
computer.
• Information in ROM is permanent, cannot be changed
by the user, and is not lost when the power is turned
off.
• ROM is called nonvolatile memory.

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 Inside the Computer
internal organization of computers
• Internal workings of every computer can be broken down into three parts:
• CPU function is to execute (process) information stored in memory.
• I/O devices, such as keyboard & monitor provide
a means of communicating with the CPU.
• The CPU is connected to memory and I/O through
a group of wires called a bus.
– Allows signals to carry information from place to place.
• In every computer there are three types of buses:
– Address bus; Data bus; Control bus.

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 Inside the Computer
internal organization of computers
• For a device (memory or I/O) to be recognized
by the CPU, it must be assigned an address.
– No two devices can have the same address.
• The address assigned to a given device must be
unique.
• The CPU puts the address (in binary) on the address bus &
decoding circuitry finds the device.
– The CPU then uses the data bus either to get data
from that device or to send data to it.
• Control buses provide device read/write signals.
– To indicate if the CPU is asking for, or sending information.

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 Inside the Computer
internal organization of computers

Internal Organization Of Computers

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 Inside the Computer
more about the data bus
• As data buses carry information in/out of a CPU,
the more data buses available, the better the CPU.
– More buses mean a more expensive CPU & computer.
• Data buses are bidirectional, because the CPU must use
them either to receive or to send data.
– Average bus size is between 8 and 64.

• Computer processing power is related to bus size.

– An 8-bit bus can send out 1 byte a time.
– A 16-bit bus can send out 2 bytes at a time.
• Twice as fast.

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 Inside the Computer
more about the address bus
• The address bus is used to identify devices and memory
connected to the CPU.
– The more address bits available, the larger the number
of devices that can be addressed.
• The number of CPU address bits determines the number of
locations with which it can communicate.
– Always equal to 2x, where x is the number of address lines,
regardless of the size of the data bus.
• The address bus is unidirectional.
– The CPU uses the bus only to send addresses out.

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 Inside the Computer
CPU & relation to RAM and ROM
• For the CPU to process information, the data must be stored
in RAM or ROM.
– The CPU cannot get the information from the disk
directly because the disk is too slow.
– RAM & ROM are often referred to as primary memory.
• Disks are called secondary memory.

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 Inside the Computer
inside CPUs
• A program stored in memory provides instructions to the CPU to perform an action.
– Adding payroll
numbers or
controlling
a robot.

Function of the CPU is to

fetch these instructions
from memory and then
execute them.

Figure 0-19 Internal Block Diagram of a CPU

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 Inside the Computer
CPU and relation to RAM and ROM
• To perform the actions of fetch and execute, all CPUs are
equipped with resources such as…
– Registers - to store information temporarily.
• 8, 16, 32, 64 bit, depending on CPU.
– ALU (arithmetic/logic unit) - for arithmetic functions
such as add, subtract, multiply, and divide.
• Also logic functions such as AND, OR, and NOT.
– Program counter - to point to the address of the
next instruction to be executed.
• In the IBM PC, a register called IP or instruction
pointer.
– Instruction decoder - to interpret the instruction
fetched into the CPU.

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 Inside the Computer
internal workings of computers
• A step-by-step analysis of CPU processes to add three
numbers, with steps & code shown.
– Assume a CPU has registers A, B, C, and D.
• An 8-bit data bus and a 16-bit address bus.
– The CPU can access memory addresses 0000 to FFFFH.
• A total of 10000H locations.

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 Inside the Computer
internal workings of computers

• If the program to perform the actions listed above,

is stored in memory locations starting at 1400H,
the following would represent the contents for
each memory address location…

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 Inside the Computer
internal workings of computers

• The CPU’s program counter can have a value between 0000

and FFFFH.
– The program counter must be set to the address of
the first instruction code to be executed - 1400H.

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 Inside the Computer
internal workings of computers
• The CPU puts the address 1400H on the address bus and
sends it out.
– Memory finds the location while the CPU activates the READ signal,
indicating it wants the byte at 1400H.
• The content (B0) is put on the data bus & brought to
the CPU.

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 Inside the Computer
internal workings of computers
• The CPU decodes the instruction B0 with the help of its
instruction decoder dictionary.
– Bring the byte of the next memory location into CPU Register A.

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 Inside the Computer
internal workings of computers
• From memory location 1401H, the CPU fetches code 21H
directly to Register A.
– After completing the instruction, the program counter points to the
address of the next instruction - 1402H.
• Address 1402H is sent out on the address bus, to fetch
the next instruction.

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 Inside the Computer
internal workings of computers
• From 1402H, the CPU fetches code 04H.
– After decoding, the CPU knows it must add the byte at
the next address (1403) to the contents of register A.
• After it brings the value (42H) into the CPU, it provides
the contents of Register A, along with this value to the
ALU to perform the addition.
• Program counter becomes 1404, the next instruction
address.

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 Inside the Computer
internal workings of computers
• Address 1404H is put on the address bus and
the code is fetched, decoded, and executed.
– Again adding a value to Register A.
• The program counter is updated to 1406H

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 Inside the Computer
internal workings of computers
• The contents of address 1406 (HALT code) are
fetched in and executed.
– The HALT instruction tells the CPU to stop incrementing the program counter
and asking for the next instruction.
• Without HALT, the CPU would continue updating the
program counter and fetching instructions.

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 The Original IBM PC
Reprogrammable Microcomputer

• Introduced in mid-1981.
• Leading personal computer architecture ever since.
• Enormous amount of application software is available [>50000].
• Open system. Functionality can be expanded by adding boards to system.
• Additional memory, modem, serial communication interface, local area network
interface etc… [Through 8-bit expansion bus]
• Industry Standard Architecture (ISA) / Peripheral Component Interface (PCI)

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 General Architecture of a Microcomputer System

Memory Unit
Primary storage memory

Program Data Secondary

Storage Storage Storage
Memory Memory Memory

Input Output
MPU
Unit Unit

• Four functional unit : (1) Input Unit (2) Micro-processing Unit (3) Memory Unit (4) Output Unit.

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 Micro-processing Unit

Intel Corporation’s 8088 Microprocessor

• Microprocessor is a general purpose processing unit.

• Built into a single integrated circuit (IC).
• It is responsible for performing all arithmetic operations and making
logical decisions.
• It controls overall system operation.
• 8088 is a 16-bit microprocessor. It can directly process 16-bit wide
data.

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 Evolution of Mic. Architecture

• Microprocessors can be categorized in terms of

max. number of binary bits in the data they process.
• 4-bit: the 4004, 4-bit words or nibble of data.
[Calculators]; 1972
• 8-bit: the 8008, 8080, 8085. [Cash registers,
printers];1975
• 16-bit: the 8086, 8088 (8-bit bus version); 1979
• 32-bit: the 80386DX, 1985
the Pentium, 1993
 Transistor Count

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 BRIEF HISTORY OF THE x86 FAMILY
evolution from 8080/8085 to 8086

• In 1978, Intel Corporation introduced the 16-bit 8086

microprocessor, a major improvement over the previous
generation 8080/8085 series.
1. The 8086 capacity of 1 megabyte of memory exceeded
the 8080/8085 maximum of 64K bytes of memory.
2. 8080/8085 was an 8-bit system, which could work on
only 8 bits of data at a time.
 Data larger than 8 bits had to be broken into 8-bit pieces to
be processed by the CPU.
3. 8086 was a pipelined processor, as opposed to the
non-pipelined 8080/8085.

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BRIEF HISTORY OF THE x86 FAMILY
evolution from 8080/8085 to 8086

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 BRIEF HISTORY OF THE x86 FAMILY
evolution from 8080/8085 to 8086
• The 8086 microprocessor has a 16-bit data bus, internally and externally.
– All registers are 16 bits wide, and there is a 16-bit
data bus to transfer data in and out of the CPU
– There was resistance to a 16-bit external bus as
peripherals were designed around 8-bit processors.
– A printed circuit board with a 16-bit data bus also cost more.
• As a result, Intel came out with the 8088 version.
– Identical to the 8086, but with an 8-bit external data bus.
– It has the same memory capacity of 1 megabyte.
– Picked up by IBM as the microprocessor in designing the PC.
• The 8088-based IBM PC was an great success, because IBM &
Microsoft made it an open system.
– Documentation and specifications of the hardware and software of the PC were
made public.
– Making it possible for many vendors to clone the hardware successfully & spawn
a major growth in both hardware and software designs based on the IBM PC.
– In contrast to Apple computer which was a fully closed system.

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 BRIEF HISTORY OF THE x86 FAMILY
80286, 80386, and 80486
• Intel introduced the 80286 in 1982, which IBM picked up for
the design of the PC AT.
– 16-bit internal & external data buses.
– 24 address lines, for 16mb memory. (224 = 16mb)
– Virtual memory for the first time.
– Virtual memory is way to fool microprocessor into thinking that it has
access to an almost unlimited amount of memory by swapping data
between disk storage and RAM.

• 80286 can operate in one of two modes:

o Real mode - a faster 8088/8086 with the same maximum of 1
megabyte of memory.
o Protected mode - which allows for 16M of memory.
o Also capable of protecting the operating system & programs from
accidental or deliberate destruction by a user.

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 BRIEF HISTORY OF THE x86 FAMILY
80286, 80386, and 80486
• In 1985 Intel introduced 80386 (or 80386DX).
– 32-bit internally/externally, with a 32-bit address bus.
– Capable of handling memory of up to 4 gigabytes. (232)
– Virtual memory increased to 64 terabytes. (246)
• Later Intel introduced 386SX, internally identical, but with a 16-bit external
data bus & 24-bit address bus.
– This makes the 386SX system much cheaper.
• Since general-purpose processors could not handle mathematical
calculations rapidly, Intel introduced numeric data processing chips.
– Math co-processors, such as 8087, 80287, 80387.
• On the 80486, in 1989, Intel put a greatly enhanced 80386 & math
coprocessor on a single chip.
– Plus additional features such as cache memory.
– Cache memory is static RAM with a very fast access time.
• All programs written for the 8088/86 will run on
286, 386, and 486 computers.

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BRIEF HISTORY OF THE x86 FAMILY
80286, 80386, and 80486

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 BRIEF HISTORY OF THE x86 FAMILY
Pentium® & Pentium® Pro

• In 1992, Intel released the Pentium®. (not 80586)

– A name can be copyrighted, but numbers cannot.
• On release, Pentium® had speeds of 60 & 66 MHz.
– Designers utilized over 3 million transistors on the Pentium ® chip
using submicron fabrication technology.
– New design features made speed twice that of 80486/66.
– Over 300 times faster than that of the original 8088.
• Pentium® is fully compatible with previous x86 processors
but includes several new features.
– Separate 8K cache memory for code and data.
– 64-bit bus, and a vastly improved floating-point processor.

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 BRIEF HISTORY OF THE x86 FAMILY
Pentium® & Pentium® Pro

• The Pentium® is packaged in a 273-pin PGA chip

– BICMOS technology, combines the speed of bipolar transistors with
power efficiency of CMOS technology
– 64-bit data bus, 32-bit registers & 32-bit address bus.
– Capable of addressing 4gb of memory.
• In 1995 Intel Pentium® Pro was released—the sixth
generation x86.
– 5.5 million transistors.
– Designed primarily for 32-bit servers & workstations.

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BRIEF HISTORY OF THE x86 FAMILY
Pentium® & Pentium® Pro

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 BRIEF HISTORY OF THE x86 FAMILY
Pentium® II

• In 1997 Intel introduced the Pentium® II processor

– 7.5-million-transistor processor featured MMX
(MultiMedia Extension) technology incorporated
into the CPU.
– For fast graphics and audio processing.
• In 1998 the Pentium® II Xeon was released.
– Primary market is for servers and workstations.
• In 1999, Celeron® was released.
– Lower cost & good performance make it ideal for PCs used to
meet educational and home business needs.

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 BRIEF HISTORY OF THE x86 FAMILY
Pentium® III
• In 1999 Intel released Pentium® III.
– 9.5-million-transistor processor.
– 70 new instructions called SIMD.
– Enhance video/audio performance in 3-D imaging, and streaming
audio.
• In 1999 Intel introduced the Pentium® III Xeon.
– Designed more for servers and business workstations with
multiprocessor configurations.

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 BRIEF HISTORY OF THE x86 FAMILY
Pentium® 4
• The Pentium® 4 debuted late in 1999.
– Speeds of 1.4 to 1.5 GHz.
– System bus operates at 400 MHz
• Completely new 32-bit architecture, called NetBurst.
– Designed for heavy multimedia processing.
– Video, music, and graphic file manipulation on the Internet.
– New cache and pipelining technology & expansion of
the multimedia instruction set make the P4 a high-end media
processing microprocessor.

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 BRIEF HISTORY OF THE x86 FAMILY
Intel 64 Architecture
• Intel has selected Itanium® as the new brand name for
the first product in its 64-bit family of processors.
– Formerly called Merced.
• The evolution of microprocessors is increasingly
influenced by the evolution of the Internet.
– Itanium® architecture is designed to meet Internet-driven needs
for servers & high-performance workstations.
– Itanium® will have the ability to execute many instructions
simultaneously, plus extremely large memory capabilities.

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 Inside The 8088/86
• There are two ways to
make the CPU process
information faster:
1. Increase the working
frequency.
o Using technology available,
with cost considerations.
2. Change the internal
architecture of the CPU.

Figure 1-1
Internal Block Diagram of the 8088/86 CPU
(Reprinted by permission of Intel Corporation,
Copyright Intel Corp.1989)

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 Inside The 8088/86
pipelining
• 8085 could either fetch or execute at any given time.
– The idea of pipelining in its simplest form is to allow the CPU to fetch
and execute at the same time.

Figure 1-2 Pipelined vs Nonpipelined Execution

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 INSIDE THE 8088/86
pipelining
• Intel implemented pipelining in 8088/86 by splitting the
internal structure of the into two sections:
– The execution unit (EU) and the bus interface unit (BIU).
– These two sections work simultaneously.
• The BIU accesses memory and peripherals, while the
EU executes instructions previously fetched.
– This works only if the BIU keeps ahead of the EU, so
the BIU of the 8088/86 has a buffer, or queue
– The buffer is 4 bytes long in 8088 and 6 bytes in 8086.
• 8088/86 pipelining has two branches, fetch & execute.
– In more powerful computers, it can have many stages.

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 INSIDE THE 8088/86
pipelining

• If an instruction takes too long to execute, the queue is

filled to capacity and the buses will sit idle.
• In some circumstances, the microprocessor must flush
out the queue.
– When a jump instruction is executed, the BIU starts to fetch
information from the new location in memory and information
fetched previously is discarded.
– The EU must wait until the BIU fetches the new instruction
– In computer science terminology, a branch penalty.
– In a pipelined CPU, too much jumping around reduces
the efficiency of a program.

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 INSIDE THE 8088/86
registers
• In the CPU, registers store information temporarily.
– One or two bytes of data to be processed.
– The address of data.
• General-purpose registers in 8088/86 processors can be
accessed as either 16-bit or 8-bit registers.
– All other registers can be accessed only as the full 16 bits.
• In 8088/86, data types are either 8 or 16 bits.
– To access 12-bit data, for example, a 16-bit register must be used
with the highest 4 bits set to 0.

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 INSIDE THE 8088/86
registers
• The bits of a register are numbered in descending order, as
shown:

 Some instructions use only specific registers.

 The first letter of each register indicates its use.
– AX is used for the accumulator.
– BX is a base addressing register.
– CX is a counter in loop operations.
– DX points to data in I/O operations.

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 INSIDE THE 8088/86
registers

 AX accumulator, BX base addressing register, CX counter in

loop operations, DX to point data in I/O operations.

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INTRODUCTION TO ASSEMBLY PROGRAMMING

• The CPU can work only in binary, very high speeds.

– It is tedious & slow for humans to deal with 0s & 1s in order to
program the computer.
• A program of 0s & 1s is called machine language.
– Early computer programmers actually coded programs
in machine language.
• Eventually, Assembly Languages were developed, which
provided mnemonics for machine code.
– Mnemonic is typically used in computer science and engineering
literature to refer to codes & abbreviations that are relatively
easy to remember.

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INTRODUCTION TO ASSEMBLY PROGRAMMING
• Assembly language is referred to as a low-level language
because it deals directly with the internal structure of the
CPU.
– Assembly language programs must be translated into machine
code by a program called an assembler.
– To program in Assembly language, programmers must know the
number of registers and their size.
– As well as other details of the CPU.
• Today there are many different programming languages,
such as C/C++, BASIC, C#, etc.
– Called high-level languages because the programmer does not
have to be concerned with internal CPU details.
• High-level languages are translated into machine code by
a program called a compiler.
– To write a program in C, one must use a C compiler to translate the
program into machine language
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INTRODUCTION TO ASSEMBLY PROGRAMMING
• An Assembly language program consists of a series of
lines of Assembly language instructions.
• An Assembly language instruction consists of a
mnemonic, optionally followed by one or two operands.
– Operands are the data items being manipulated.
– Mnemonics are commands to the CPU, telling it what to do with
those items.
• Two widely used instructions are move & add.

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 INTRODUCTION TO ASSEMBLY PROGRAMMING
MOV instruction
• The MOV instruction copies data from one location to
another, using this format:

 This instruction tells the CPU to move (in reality, copy) the
source operand to the destination operand.
– For example, the instruction "MOV DX,CX" copies the contents of register CX
to register DX.
– After this instruction is executed, register DX will have the same value as
register CX.
 Instruction does not affect the source operand.

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 INTRODUCTION TO ASSEMBLY PROGRAMMING
MOV instruction
• This program first loads CL with value 55H, then moves this
value around to various registers
inside the CPU.

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 INTRODUCTION TO ASSEMBLY PROGRAMMING
MOV instruction
• The use of 16-bit registers is shown here:

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 INTRODUCTION TO ASSEMBLY PROGRAMMING
MOV instruction
• In the 8086 CPU, data can be moved among all the
registers, as long as the source and destination registers
match in size (Except the flag register.)
– There is no such instruction as "MOV FR,AX“.
• Code such as "MOV AL,DX" will cause an error.
– One cannot move the contents of a 16-bit register into an
8-bit register.

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 INTRODUCTION TO ASSEMBLY PROGRAMMING
MOV instruction
• Using the MOV instruction, data can be moved directly into
non-segment registers only.
– The following demonstrates legal & illegal instructions.

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 INTRODUCTION TO ASSEMBLY PROGRAMMING
MOV instruction
• Values cannot be loaded directly into any segment register
(CS, DS, ES, or SS).
– To load a value into a segment register, load it to a non-segment
register, then move it to the segment register.

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 INTRODUCTION TO ASSEMBLY PROGRAMMING
MOV instruction
• If a value less than FFH is moved into a 16-bit register, the rest
of the bits are assumed to be zeros.
– For example, in "MOV BX,5" the result will be BX = 0005.
– BH = 00 and BL = 05.

 Moving a value that is too large into a register will cause an

error.

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 INTRODUCTION TO ASSEMBLY PROGRAMMING
ADD instruction
 The ADD instruction has the following format:

 ADD tells the CPU to add the source & destination operands and put the
result in the destination.
– To add two numbers such as 25H and 34H, each can be moved to a
register, then added together:

– Executing the program above results in:

AL = 59H (25H + 34H = 59H) and BL = 34H.
• The contents of BL do not change.

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 INTRODUCTION TO ASSEMBLY PROGRAMMING
ADD instruction
• The program above can be written in many ways,
depending on the registers used, such as:

– The program above results in DH = 59H

and CL = 34H.

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 INTRODUCTION TO ASSEMBLY PROGRAMMING
ADD instruction
• Is it necessary to move both data items into registers before
adding them together?
– No, it is not necessary.

– In the case above, while one register contained one value, the
second value followed the instruction as
an operand.
• This is called an immediate operand.

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 INTRODUCTION TO ASSEMBLY PROGRAMMING
ADD instruction
• An 8-bit register can hold numbers up to FFH.
– For numbers larger than FFH (255 decimal), a 16-bit register such as
AX, BX, CX, or DX must be used.
• The following program can add 34EH & 6A5H:

– Running the program gives DX = 9F3H.

• (34E + 6A5 = 9F3) and AX = 34E.

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 INTRODUCTION TO ASSEMBLY PROGRAMMING
ADD instruction
• Any 16-bit non-segment registers could have been used to
perform the action above:

– The general-purpose registers are typically used in arithmetic operations

• Register AX is sometimes referred to as the accumulator.

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INTRODUCTION TO PROGRAM SEGMENTS
• A typical Assembly language program consists of
at least three segments:
– A code segment - which contains the Assembly language
instructions that perform the tasks that the program was
designed to accomplish.
– A data segment - used to store information (data) to
be processed by the instructions in the code segment.
– A stack segment - used by the CPU to store information
temporarily.

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 INTRODUCTION TO PROGRAM SEGMENTS
origin and definition of the segment

• A segment is an area of memory that includes up

to 64K bytes, and begins on an address evenly divisible
by 16 (such an address ends in 0H)
– 8085 addressed a maximum of 64K of physical memory, since it
had only 16 pins for address lines. (216 = 64K)
– Limitation was carried into 8088/86 design for compatibility.
• In 8085 there was 64K bytes of memory for all code,
data, and stack information.
– In 8088/86 there can be up to 64K bytes in each category at any
given time.
– The code segment, data segment, and stack segment.

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 INTRODUCTION TO PROGRAM SEGMENTS
logical address and physical address

• In literature concerning 8086, there are three types of

addresses mentioned frequently:
– The physical address - the 20-bit address actually on the
address pins of the 8086 processor, decoded by the memory
interfacing circuitry.
• This address can have a range of 00000H to
FFFFFH.
• An actual physical location in RAM or ROM within
the 1 mb memory range.
– The offset address - a location in a 64K-byte segment range,
which can can range from 0000H to FFFFH.
– The logical address - which consists of a segment value and
an offset address.

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 INTRODUCTION TO PROGRAM SEGMENTS
code segment
• To execute a program, 8086 fetches the instructions
(opcodes and operands) from the code segment.
– The logical address of an instruction always consists of a CS (code
segment) and an IP (instruction pointer), shown in CS:IP format.
– The physical address for the location of the instruction
is generated by shifting the CS left one hex digit, then adding it to the
IP.
• IP contains the offset address.
• The resulting 20-bit address is called the physical address
since it is put on the external physical address bus pins.

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 INTRODUCTION TO PROGRAM SEGMENTS
code segment
• Assume values in CS & IP as shown in the diagram:

– The offset address contained in IP, is 95F3H.

– The logical address is CS:IP, or 2500:95F3H.
– The physical address will be 25000 + 95F3 = 2E5F3H

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 INTRODUCTION TO PROGRAM SEGMENTS
code segment
• Calculate the physical address of an instruction:

– The microprocessor will retrieve the instruction from memory locations starting at
2E5F3.

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 INTRODUCTION TO PROGRAM SEGMENTS
code segment
• Calculate the physical address of an instruction:

– Since IP can have a minimum value of 0000H and a maximum of FFFFH, the logical
address range in this example is 2500:0000 to 2500:FFFF.

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 INTRODUCTION TO PROGRAM SEGMENTS
code segment
• Calculate the physical address of an instruction:

– This means that the lowest memory location of the code segment above will be
25000H (25000 + 0000) and the highest memory location will be 34FFFH (25000 +
FFFF).

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 INTRODUCTION TO PROGRAM SEGMENTS
code segment
• What happens if the desired instructions are located beyond
these two limits?
– The value of CS must be changed to access those instructions.

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 INTRODUCTION TO PROGRAM SEGMENTS
code segment logical/physical address
• In the next code segment, CS and IP hold the logical address of the
instructions to be executed.
– The following Assembly language instructions have been assembled
(translated into machine code) and stored in memory.
– The three columns show the logical address of CS:IP, the machine code
stored at that address, and the corresponding Assembly language code.
– The physical address is put on the address bus by the CPU to be decoded by
the memory circuitry.

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 INTRODUCTION TO PROGRAM SEGMENTS
code segment logical/physical address

Instruction "MOV AL,57" has a machine code of B057.

B0 is the opcode and 57 is the operand.

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 INTRODUCTION TO PROGRAM SEGMENTS
code segment logical/physical address

Instruction "MOV AL,57" has a machine code of B057.

B0 is the opcode and 57 is the operand.
The byte at address 1132:0100 contains B0, the opcode for moving
a value into register AL.
Address 1132:0101 contains the operand to be moved to AL.

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 INTRODUCTION TO PROGRAM SEGMENTS
data segment
• Assume a program to add 5 bytes of data, such as 25H,
12H, 15H, 1FH, and 2BH.
– One way to add them is as follows:

– In the program above, the data & code are mixed together in the
instructions.
• If the data changes, the code must be searched for every place it
is included, and the data retyped
• From this arose the idea of an area of memory strictly for data

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 INTRODUCTION TO PROGRAM SEGMENTS
data segment
• In x86 microprocessors, the area of memory set aside for data is
called the data segment.
– The data segment uses register DS and an offset value.
– DEBUG assumes that all numbers are in hex.
• No "H" suffix is required.
– MASM assumes that they are in decimal.
• The "H" must be included for hex data.
• The next program demonstrates how data can
be stored in the data segment and the program
rewritten so that it can be used for any set of data.

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 INTRODUCTION TO PROGRAM SEGMENTS
data segment
• Assume data segment offset begins at 200H.
– The data is placed in memory locations:

– The program can be rewritten as follows:

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 INTRODUCTION TO PROGRAM SEGMENTS
data segment
• The offset address is enclosed in brackets, which indicate
that the operand represents the address
of the data and not the data itself.

– If the brackets were not included, as in

"MOV AL,0200", the CPU would attempt to move 200 into
AL instead of the contents of offset address 200. decimal.
• This program will run with any set of data.
• Changing the data has no effect on the code.

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INTRODUCTION TO PROGRAM SEGMENTS
data segment

• If the data had to be stored at a different offset address

the program would have to be rewritten
– A way to solve this problem is to use a register to hold
the offset address, and before each ADD, increment the register
to access the next byte.
• 8088/86 allows only the use of registers BX, SI,
and DI as offset registers for the data segment
– The term pointer is often used for a register holding
an offset address.

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 INTRODUCTION TO PROGRAM SEGMENTS
data segment
• In the following example, BX is used as a pointer:

• The INC instruction adds 1 to (increments) its operand.

– "INC BX" achieves the same result as "ADD BX,1“
– If the offset address where data is located is changed, only one instruction will need
to be modified.

78
 INTRODUCTION TO PROGRAM SEGMENTS data
segment logical/physical address

• The physical address for data is calculated using the

same rules as for the code segment.
– The physical address of data is calculated by shifting DS left one
hex digit and adding the offset value, as shown
in coming examples

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INTRODUCTION TO PROGRAM SEGMENTS data
segment logical/physical address

80
INTRODUCTION TO PROGRAM SEGMENTS data
segment logical/physical address

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 INTRODUCTION TO PROGRAM SEGMENTS
little endian convention
• Previous examples used 8-bit or 1-byte data.
– What happens when 16-bit data is used?

 The low byte goes to the low memory location and the high byte
goes to the high memory address.
– Memory location DS:1500 contains F3H.
– Memory location DS:1501 contains 35H.
• (DS:1500 = F3 DS:1501 = 35)
– This convention is called little endian vs big endian.
• From a Gulliver’s Travels story about how an egg should
be opened—from the little end, or the big end.

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 INTRODUCTION TO PROGRAM SEGMENTS
little endian convention
• In the big endian method, the high byte goes to the low address.
– In the little endian method, the high byte goes to the
high address and the low byte to the low address.

 All Intel microprocessors and many microcontrollers use the little endian
convention.
o Freescale (formerly Motorola) microprocessors, along with some other
microcontrollers, use big endian.
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 INTRODUCTION TO PROGRAM SEGMENTS
extra segment (ES)
• ES is a segment register used as an extra data segment.
– In many normal programs this segment is not used.
– Use is essential for string operations.

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 INTRODUCTION TO PROGRAM SEGMENTS
memory map of the IBM PC
• The 20-bit address of 8088/86 allows
1mb (1024K bytes) of memory space
with the address range 00000–FFFFF.
– During the design phase of the first IBM
PC, engineers had to decide on the
allocation of the 1-megabyte memory space
to various sections of the PC.
• This memory allocation is
called a memory map.

Figure 1-3 Memory Allocation in the PC

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 INTRODUCTION TO PROGRAM SEGMENTS
memory map of the IBM PC
• Of this 1 megabyte, 640K bytes from
addresses 00000–9FFFFH were set
aside for RAM

• 128K bytes A0000H– BFFFFH were

allocated for video memory
• The remaining 256K bytes from
C0000H–FFFFFH were set aside for
ROM

Figure 1-3 Memory Allocation in the PC

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 INTRODUCTION TO PROGRAM SEGMENTS
more about RAM
• In the early 80s, most PCs came with 64K to 256K bytes of
RAM, more than adequate at the time
– Users had to buy memory to expand up to 640K.
• Managing RAM is left to Windows because...
– The amount of memory used by Windows varies.
– Different computers have different amounts of RAM.
– Memory needs of application packages vary.
• For this reason, we do not assign any values for the CS, DS,
and SS registers.
– Such an assignment means specifying an exact physical address in the
range 00000–9FFFFH, and this is beyond the knowledge of the user.

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INTRODUCTION TO PROGRAM SEGMENTS
video RAM

• From A0000H to BFFFFH is set aside for video

– The amount used and the location vary depending
on the video board installed on the PC

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 1.INTRODUCTION TO PROGRAM SEGMENTS
more about ROM
• C0000H to FFFFFH is set aside for ROM.
– Not all the memory in this range is used by the PC's ROM.
• 64K bytes from location F0000H–FFFFFH are
used by BIOS (basic input/output system) ROM.
– Some of the remaining space is used by various adapter cards (such
as the network card), and the rest is free.
• The 640K bytes from 00000 to 9FFFFH is referred
to as conventional memory.
– The 384K bytes from A0000H to FFFFFH are called
the UMB (upper memory block).

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INTRODUCTION TO PROGRAM SEGMENTS
function of BIOS ROM
• There must be some permanent (nonvolatile) memory to
hold the programs telling the CPU what to do when the
power is turned on
– This collection of programs is referred to as BIOS.
• BIOS stands for basic input-output system.
– It contains programs to test RAM and other components
connected to the CPU.
– It also contains programs that allow Windows to communicate
with peripheral devices.
– The BIOS tests devices connected to the PC when the computer
is turned on and to report any errors.

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 THE STACK
what is a stack? why is it needed?

• The stack is a section of read/write memory (RAM) used

by the CPU to store information temporarily.
– The CPU needs this storage area since there are only a limited
number of registers.
• There must be some place for the CPU to store
information safely and temporarily.
• The main disadvantage of the stack is access time.
– Since the stack is in RAM, it takes much longer to access
compared to the access time of registers.
• Some very powerful (expensive) computers do not have
a stack.
– The CPU has a large number of registers to work with.

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 THE STACK
how stacks are accessed

• The stack is a section of RAM, so there must be

registers inside the CPU to point to it.
– The SS (stack segment) register.
– The SP (stack pointer) register.
• These registers must be loaded before any
instructions accessing the stack are used.
• Every register inside the x86 can be stored in the stack,
and brought back into the CPU from the stack memory,
except segment registers and SP.
– Storing a CPU register in the stack is called a push.
– Loading the contents of the stack into the CPU register
is called a pop.

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 THE STACK
how stacks are accessed
• The x86 stack pointer register (SP) points at the current
memory location used as the top of the stack.
– As data is pushed onto the stack it is decremented.
– As data is popped off the stack into the CPU, it is incremented.
• When an instruction pushes or pops a general-purpose
register, it must be the entire 16-bit register.
– One must code "PUSH AX".
• There are no instructions such as "PUSH AL" or "PUSH
AH".

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 THE STACK
how stacks are accessed
• The SP is decremented after the push is to make sure the
stack is growing downward from upper addresses to lower
addresses.
– The opposite of the IP. (instruction pointer)
• To ensure the code section & stack section of the program
never write over each other, they are located at opposite ends
of the RAM set aside for the program.
– They grow toward each other but must not meet.
• If they meet, the program will crash.

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 THE STACK
pushing onto the stack
• As each PUSH is executed, the register contents are saved on
the stack and SP is decremented by 2.

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 THE STACK
pushing onto the stack
• For every byte of data saved on the stack, SP is decremented
once.

Since the push

is saving the
contents of a
16-bit register,
it decrements
twice.

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 THE STACK
pushing onto the stack
• In the x86, the lower byte is always stored in the memory
location with the lower address.

24H, the content of

AH, is saved
in the memory
location with the
address 1235.
AL is stored in
location 1234.

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 THE STACK
popping the stack
• With every pop, the top 2 bytes of the stack are copied to the
x86 CPU register specified by the instruction & the stack
pointer is incremented twice.

While the data

actually remains
in memory, it is
not accessible,
since the stack
pointer, SP is
beyond that point.

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 THE STACK
logical vs physical stack address
• The exact physical location of the stack depends on the
value of the stack segment (SS) register and SP, the stack
pointer.
– To compute physical addresses for the stack, shift left SS, then add
offset SP, the stack pointer register.

– Windows assigns values for the SP and SS.

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 THE STACK
a few more words about x86 segments
• Can a single physical address belong to many different
logical addresses?
– Observe the physical address value of 15020H.
• Many possible logical addresses represent this single
physical address:

– An illustration of the dynamic behavior of the segment and offset concept in the
8086 CPU.

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 THE STACK
a few more words about x86 segments
• When adding the offset to the shifted segment register
results in an address beyond the maximum allowed range of
FFFFFH, wrap-around will occur.

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 THE STACK
overlapping
• In calculating the physical address, it is possible that two
segments can overlap.

102
 FLAG REGISTER
• Many Assembly language instructions alter flag register bits
& some instructions function differently based on the
information in the flag register.
• The flag register is a 16-bit register sometimes referred to as
the status register.
– Although 16 bits wide, only some of the bits are used.
• The rest are either undefined or reserved by Intel.

103
 1.6 FLAG REGISTER
• Six flags, called conditional flags, indicate some condition
resulting after an instruction executes.

– These six are CF, PF, AF, ZF, SF, and OF.
– The remaining three, often called control flags, control
the operation of instructions before they are executed.

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 FLAG REGISTER
bits of the flag register

• Flag register bits used in x86 Assembly language

programming, with a brief explanation each:
– CF (Carry Flag) - Set when there is a carry out, from d7 after an 8-bit
operation, or d15 after a 16-bit operation.
• Used to detect errors in unsigned arithmetic operations.
– PF (Parity Flag) - After certain operations, the parity of the result's
low-order byte is checked.
• If the byte has an even number of 1s, the parity flag is
set to 1; otherwise, it is cleared.
– AF (Auxiliary Carry Flag) - If there is a carry from d3 to d4 of an
operation, this bit is set; otherwise, it is cleared.
• Used by instructions that perform BCD (binary coded
decimal) arithmetic.

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 FLAG REGISTER
bits of the flag register
• Flag register bits used in x86 Assembly language
programming, with a brief explanation each:
– ZF (Zero Flag) - Set to 1 if the result of an arithmetic or logical operation is zero;
otherwise, it is cleared.

– SF (Sign Flag) - Binary representation of signed numbers uses the most significant
bit as the sign bit.
• After arithmetic or logic operations, the status of this sign
bit is copied into the SF, indicating the sign of the result.
– TF (Trap Flag) - When this flag is set it allows the program to single-step, meaning to
execute one instruction at a time.
• Single-stepping is used for debugging purposes.

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 FLAG REGISTER
bits of the flag register
• Flag register bits used in x86 Assembly language
programming, with a brief explanation each:
– IF (Interrupt Enable Flag) - This bit is set or cleared to enable/disable only external
maskable interrupt requests.

– DF (Direction Flag) - Used to control the direction of string operations.

– OF (Overflow Flag) - Set when the result of a signed number operation is too large,
causing the high-order
bit to overflow into the sign bit.
• Used only to detect errors in signed arithmetic operations.

107
 FLAG REGISTER
flag register and ADD instruction
• Flag bits affected by the ADD instruction:
– CF (carry flag); PF (parity flag); AF (auxiliary carry flag).
– ZF (zero flag); SF (sign flag); OF (overflow flag).

108
 FLAG REGISTER
flag register and ADD instruction
• Flag bits affected by the ADD instruction:
– CF (carry flag); PF (parity flag); AF (auxiliary carry flag).
– ZF (zero flag); SF (sign flag); OF (overflow flag).

109
 FLAG REGISTER
flag register and ADD instruction

• It is important to note differences between 8- and 16-bit

operations in terms of impact on the flag bits.
– The parity bit only counts the lower 8 bits of the result
and is set accordingly.

110
 FLAG REGISTER
flag register and ADD instruction
• The carry flag is set if there is a carry beyond bit d15 instead
of bit d7.
– Since the result of the entire 16-bit operation is zero (meaning the
contents of BX), ZF is set to high.

111
 FLAG REGISTER
flag register and ADD instruction
• Instructions such as data transfers (MOV) affect no flags.

112
 FLAG REGISTER
use of the zero flag for looping
• A widely used application of the flag register is the use of the
zero flag to implement program loops.
– A loop is a set of instructions repeated a number of times.

113
 FLAG REGISTER
use of the zero flag for looping
• As an example, to add 5 bytes of data, a counter can be
used to keep track of how many times the loop needs to be
repeated.
– Each time the addition is performed the counter
is decremented and the zero flag is checked.
• When the counter becomes zero, the zero flag is
set (ZF = 1) and the loop is stopped.

114
 FLAG REGISTER
use of the zero flag for looping
• Register CX is used to hold the counter.
– BX is the offset pointer.
• (SI or DI could have been used instead)

115
 FLAG REGISTER
use of the zero flag for looping
• AL is initialized before the start of the loop
– In each iteration, ZF is checked by the JNZ instruction
• JNZ stands for "Jump Not Zero“, meaning that if ZF = 0,
jump to a new address.
• If ZF = 1, the jump is not performed, and the instruction
below the jump will be executed.

116
 FLAG REGISTER
use of the zero flag for looping

• JNZ instruction must come immediately after the

instruction that decrements CX.
– JNZ needs to check the effect of "DEC CX" on ZF.
• If any instruction were placed between them, that
instruction might affect the zero flag.

117
 x86 ADDRESSING MODES
• The CPU can access operands (data) in various ways, called
addressing modes.
– The number of addressing modes is determined when the
microprocessor is designed & cannot be changed
• The x86 provides seven distinct addressing modes:

– 1 - Register – 5 - Based relative

– 2 - Immediate – 6 - Indexed relative
– 3 - Direct – 7 - Based indexed relative
– 4 - Register indirect

118
 x86 ADDRESSING MODES
register addressing mode
• Register addressing mode involves use of registers to hold
the data to be manipulated.
– Memory is not accessed, so it is relatively fast.
• Examples of register addressing mode:

– The the source & destination registers must match in size.

• Coding "MOV CL,AX" will give an error, since the source is
a 16-bit register and the destination is an 8-bit register.

119
 x86 ADDRESSING MODES
immediate addressing mode
• In immediate addressing mode, as the name implies, when
the instruction is assembled, the operand comes
immediately after the opcode.
– The source operand is a constant.
• This mode can be used to load information into any of
register except the segment and flag registers.

120
 x86 ADDRESSING MODES
immediate addressing mode
• To move information to the segment registers, the data must
first be moved to a general-purpose register, then to the
segment register.

121
 x86 ADDRESSING MODES
direct addressing mode
• In direct addressing mode, the data is in some memory
location(s).
– In most programs, the data to be processed is often
in some memory location outside the CPU.
– The address of the data in memory comes immediately after the
instruction.

122
 x86 ADDRESSING MODES
direct addressing mode
• The address of the operand is provided with the
instruction, as an offset address.
– Calculate the physical address by shifting left the DS register and adding it to the
offset:

• Note the bracket around the address.

– If the bracket is absent, executing the command will give an error, as it is interpreted
to move the value 2400
(16-bit data) into register DL.
• An 8-bit register.

123
 x86 ADDRESSING MODES
register indirect addressing mode
• In register indirect addressing mode, the address of the
memory location where the operand resides is held by a
register.
– The registers used for this purpose are SI, DI, and BX.
• If these three registers are used as pointers, they must be
combined with DS in order to generate
the 20-bit physical address.

– Notice that BX is in brackets.

– The physical address is calculated by shifting DS
left one hex position and adding BX to it.

124
 x86 ADDRESSING MODES
register indirect addressing mode
• The same rules apply when using register SI or DI.

• Example 1-16 shows 16-bit data.

125
 x86 ADDRESSING MODES
based relative addressing mode
• In based relative addressing mode, base registers BX & BP,
and a displacement value, are used to calculate the effective
address.
– Default segments used for the calculation of the
physical address (PA) are DS for BX and SS for BP.

– Alternatives are "MOV CX,[BX+10]" or "MOV CX,10[BX]"

• Again the low address contents will go into CL
and the high address contents into CH.

126
 x86 ADDRESSING MODES
based relative addressing mode
• In the case of the BP register:

– Alternatives are "MOV AL,[BP+5]" or "MOV AL,5[BP]".

• BP+5 is called the effective address since the fifth byte from
the beginning of the offset BP is moved to register AL.

127
 x86 ADDRESSING MODES
indexed relative addressing mode
• The indexed relative addressing mode works the same as
the based relative addressing mode.
– Except that registers DI & SI hold the offset address.

128
 x86 ADDRESSING MODES
indexed relative addressing mode
• The indexed relative addressing mode works the same as
the based relative addressing mode.
– Except that registers DI & SI hold the offset address.

129
 x86 ADDRESSING MODES
based indexed addressing mode
• By combining based & indexed addressing modes, a new
addressing mode is derived called the
based indexed addressing mode.
– One base register and one index register are used.

– The coding of the instructions can vary.

130
 x86 ADDRESSING MODES
segment overrides
• The x86 CPU allows the program to override the default
segment and use any segment register.
– In "MOV AL,[BX]", the physical address of the operand to be moved
into AL is DS:BX.
• To override that default, specify the desired segment
in the instruction as "MOV AL,ES:[BX]"

131
x86 ADDRESSING MODES
summary

132