Layout Overview

 Minimum dimensions of mask

features determine:
– transistor size and die size
– hence speed, cost, and power
 “Historical” Feature size f = polysilico

gate length (in nm) n

gate W

– Set by minimum width of tox

polysilicon n+
L
n
SiO2 gate
o (good
+
– Other minimum feature sizes p-type
body
insulator,

tend to be 30 to 50%
bigger.
 Design or Layout Rules: rules
for designing masks
based on minimum
feature sizes
 Rules often “normalized” for
portability across
generations

What Are Typical Rules

 Length & Width of Transistor gate

 Separation between 2 wires on same level
 Width of wires
 Contact pad for Vias
 Cross section of Vias
 Size of Wells
 …
 Determining a Design Rule
 What is the minimum spacing between a poly
gate and a contact? What does it depend
on?
?

GND
VDD

nMOS transistor pMOS

transistor

substrate tap well tap

Design Rules CMOS VLSI Design

Factors Determining a Design Rule

 Mask alignment accuracy

– How accurate is one mask aligned to another mask?
 Process variation
– If cutting a hole, how much do sides of the cut vary?
– If implanting dopants, how much does the width of the
diffusion vary?
 How conservative do you need to be to assure
good process yield?
– 30 to 40 mask levels
– 5 to 10 process steps per mask level
 Circuit Interconnect Layout

Simplified CMOS Process

SiO2 gate oxide polysilicon

NMOS PMOS fSiei

Old2
n well
n diffusion oxide
p diffusion
p silicon substrate
 Wiring with Metal and Contacts

metal (Al)

NMOS PMOS

contact cut

Design Rules CMOS VLSI Design

Transistors of Same Type in Series

can’t do this with opposite types!

NMOS NMOS

connected by shared diffusion

Connecting Poly and Diffusion

can’t contact poly to diffusion directly!

NMOS NMOS

Design Rules CMOS VLSI Design

The Book’s 65nm Process

 The Book’s 65nm Proces s
- Up to Metal 2

Design Rules CMOS VLSI Design

The Book’s 65nm Process

- Metals

Design Rules
 65nm Design Rules (Page 1)
65nm
Rule Description (nm)
1.1 Width 500

Well
1.2 Space to well at different potential 700
1.3 Space to well at same potential 700
2.1 Width 100
(diffusion) 2.2 Spacing to active 120
Active

2.3 Source/drain surround by well 150

2.4 Substrate/well contact surround by well 150
2.5 Spacing to active of opposite type 250
3.1 Width 65
3.2 Spacing to poly over field oxide 100
Poly (i.e.
Gate)

3.2a Spacing to poly over active 100

3.3 Gate extension beyond active 100
3.4 Active extension beyond poly 100
3.5 Spacing of poly to active 70
4.1 Spacing from substrate/well to gate 150
(n or p)
Select

4.2 Overlap by poly or active 120

4.3 Overlap of substrate/well contact 120
4.4 Spacing to select 200

Design Rules CMOS VLSI Design

65nm Design Rules (Page 2)

65nm
Rule Description (nm)
5.1, 6.1 Width (exact) 80
poly or active)

5.2b, 6.26 Overlap by poly or active 10

Contact (to

5.3, 6.3 Spacing to contact 100

5.4, 6.4 Spacing to gate 70
5.5b Spacing of poly contact to other contact
5.7b, 6.7b Spacing to active/poly for mult. Contacts
6.8b Spacing of active contact to poly contact
7.1 Width 90
Metal1

7.2 Spacing to same layer of metal 90

7.3,8.3 Overlap of contact or via 10
7.4 Spacing to metal for lines wider than 10λ 300
9.1…. Width 100
Metal2

9.2, … Spacing to same layer of metal 100

9.3, … Overlap of contact or via 10
9.4, … Spacing to metal for lines wider than 10λ 300
15.1 Width 100
Metal3

15.2 Spacing to metal3 100

15.3 Overlap of via2 10
15.4 Spacing to metal for lines wider than 10λ 300
15.1 Width 400
Metal
8 9‐

15.2 Spacing to metal3 400

15.3 Overlap of via2 100
15.4 Spacing to metal for lines wider than 10λ 500
8.1,14.1 Width (exact) 100
Via2

[Link] Spacing to via on same layer 100

Via1

8.1,14.1 Width (exact) 100

7,8
3…

[Link] Spacing to via on same layer 100

Via

Design Rules CMOS VLSI Design

6

8.1,14.1 Width (exact) 200

Via

[Link] Spacing to via on same layer 200

 A Simplified Rule System
λ Rules

Design Rules

λ Rules
A simplified, technology generations independent design rule
system:
 Express rules in terms of λ = f/2
– E.g. λ = 0.3 mm in 0.6 mm process
 Called “Lambda rules”
 Lambda rules NOT used in commercial applications
– Lambda rules need to be very conservative and thus waste
space.
 Lambda rules good for education!
– MOSIS SCMOS SUMB Rules

Design Rules CMOS VLSI Design

 Simplified Design Rules
 Conservative rules to get you started
– See Fig. 1.39 Missing Rule
Poly to Dif Contact

2λ

[Link]

Design Rules CMOS VLSI Design

Transistor Width and Length

Dimensions of Gate over Source/Drain Diffusion
This is the active area of a transistor.

Transistor Width Transistor Length

Perpendicular to Parallel to
direction carriers direction carriers
travel
travel.

Typically Width >> Length

Design Rules CMOS VLSI Design

 Substrate and Well Taps
 Substrate needs to be tied to Ground.
– Why?
 N-well needs to be tied to VDD.
– Why?

Design Rules CMOS VLSI Design

λ Rules (compared to 65 nm)

Lambda Rules
65nm Eqvt
Rule Description (nm) 65nm in λ 180 130 90 65 45 32 28 22 10
1.1 Width 500 390 12 1080 780 540 390 270 192 168 132 60
Well

1.2 Space to well at different potential 700 585 18 1620 1170 810 585 405 288 252 198 90
1.3 Space to well at same potential 700 195 6 540 390 270 195 135 96 84 66 30
2.1 Width 100 98 3 270 195 135 98 68 48 42 33 15
(diffusion)

2.2 Spacing to active 120 98 3 270 195 135 98 68 48 42 33 15

Active

2.3 Source/drain surround by well 150 195 6 540 390 270 195 135 96 84 66 30
2.4 Substrate/well contact surround by well 150 98 3 270 195 135 98 68 48 42 33 15
2.5 Spacing to active of opposite type 250 130 4 360 260 180 130 90 64 56 44 20
3.1 Width 65 65 2 180 130 90 65 45 32 28 22 10
3.2 Spacing to poly over field oxide 100 98 3 270 195 135 98 68 48 42 33 15
Poly (i.e.
Gate)

3.2a Spacing to poly over active 100 98 3 270 195 135 98 68 48 42 33 15

3.3 Gate extension beyond active 100 65 2 180 130 90 65 45 32 28 22 10
3.4 Active extension beyond poly 100 98 3 270 195 135 98 68 48 42 33 15
3.5 Spacing of poly to active 70 33 1 90 65 45 33 23 16 14 11 5
4.1 Spacing from substrate/well to gate 150 98 3 270 195 135 98 68 48 42 33 15
(n or p)
Select

4.2 Overlap by poly or active 120 65 2 180 130 90 65 45 32 28 22 10

4.3 Overlap of substrate/well contact 120 33 1 90 65 45 33 23 16 14 11 5
4.4 Spacing to select 200 65 2 180 130 90 65 45 32 28 22 10

Green: lambda rules significantly smaller

Red: lambda rules significantly larger

Design Rules CMOS VLSI

Design
 λ Rules (compared to 65 nm)
65nm Eqvt
Rule Description (nm) 65nm in λ 180 130 90 65 45 32 28 22 10
5.1, 6.1 Width (exact) 80 65 2 180 130 90 65 45 32 28 22 10

poly or active)
Contact (to 5.2b, 6.26 Overlap by poly or active 10 33 1 90 65 45 33 23 16 14 11 5
5.3, 6.3 Spacing to contact 100 98 3 270 195 135 98 68 48 42 33 15
5.4, 6.4 Spacing to gate 70 65 2 180 130 90 65 45 32 28 22 10
5.5b Spacing of poly contact to other contact 163 5 450 325 225 163 113 80 70 55 25
5.7b, 6.7b Spacing to active/poly for mult. Contacts 98 3 270 195 135 98 68 48 42 33 15
6.8b Spacing of active contact to poly contact 130 4 360 260 180 130 90 64 56 44 20
7.1 Width 90 98 3 270 195 135 98 68 48 42 33 15
Metal1

7.2 Spacing to same layer of metal 90 98 3 270 195 135 98 68 48 42 33 15

7.3,8.3 Overlap of contact or via 10 33 1 90 65 45 33 23 16 14 11 5
7.4 Spacing to metal for lines wider than 10λ 300 195 6 540 390 270 195 135 96 84 66 30
9.1…. Width 100 98 3
Metal2

9.2, … Spacing to same layer of metal 100 98 3

9.3, … Overlap of contact or via 10 33 1
9.4, … Spacing to metal for lines wider than 10λ 300 195 6
15.1 Width 100 163 5 450 325 225 163 113 80 70 55 25
Metal3

15.2 Spacing to metal3 100 98 3 270 195 135 98 68 48 42 33 15

15.3 Overlap of via2 10 65 2 180 130 90 65 45 32 28 22 10
15.4 Spacing to metal for lines wider than 10λ 300 195 6 540 390 270 195 135 96 84 66 30
15.1 Width 400 0 0 0 0 0 0 0 0 0
Metal
8 9‐

15.2 Spacing to metal3 400 0 0 0 0 0 0 0 0 0

15.3 Overlap of via2 100 0 0 0 0 0 0 0 0 0
15.4 Spacing to metal for lines wider than 10λ 500 0 0 0 0 0 0 0 0 0
8.1,14.1 Width (exact) 100 65 2 180 130 90 65 45 32 28 22 10
Via2

[Link] Spacing to via on same layer 100 98 3 270 195 135 98 68 48 42 33 15

Via1

8.1,14.1 Width (exact) 100 0 0 0 0 0 0 0 0 0

3…
7,8

[Link] Spacing to via on same layer 100 0 0 0 0 0 0 0 0 0

Design Rules CMOS VLSI Design
Via
6

8.1,14.1 Width (exact) 200 0 0 0 0 0 0 0 0 0

Via

[Link] Spacing to via on same layer 200 0 0 0 0 0 0 0 0 0