MOSFET FABRICATION

Module1
PMOS FABRICATION-METAL GATE TECHNOLOGY
PMOS FABRICATION-METAL GATE TECHNOLOGY
POLY-SILICON GATE TECHNOLOGY
LOCAL OXIDATION OF SILICON(LOCOS)
TECHNIQUE
 CMOS N-WELL TECHNOLOGY

b) N well doping through LOCOS

a) p-type substrate,(1,0,0)

c) Oxidation for Deep np junction

d) Strip oxide, creating a step e) Field oxide and area for active transistor

f) Boron Implantation and photoresist

 g) Grow thick Oxide h) Remove Silicon Nitride – oxide mask

i) gate oxidation

j) gate polysilicon deposition

k)patterning and

l) source and drain diffusion

 SECONDARY N-WELL TECHNOLOGY

a) Low doped p- substrate b) LOCOS + Boron Implantation

c) Photoresist + Phosphorous Implantation d) Low energy Boron Implantation

 TRUE TWIN-TUB TECHNOLOGY

b) Oxidation

a) Intrinsinc substrate + Oxide Nitride mask

+ Phosphorous implantation

d) Boron Implantation
c) Strip Nitride to form p well
 TRUE TWIN-TUB TECHNOLOGY

d) Formation of two wells

e) Active area definition

f) Strip oxide Nitride to form two active regions

MOSFET SCALING
 OBJECTIVES

• Motivation for Scaling

• Types of Scaling

• Basics of MOS Transistor

• Short channel effect

 Types of Scaling

Two types of scaling are common:

1) constant field scaling/Full Scaling and

2) constant voltage scaling.

After scaling, the different Mosfet parameters will be converted as given by table below:

Before Scaling, After Constant Field Scaling, After Constant Voltage Scaling
 The MOS Transistor

Polysilico Aluminu
n m

MOSFET - Metal Oxide Semiconductor Field Effect Transistor

n-channel MOSFET (nMOS) & p-channel MOSFET (pMOS)
 The MOS Transistor

Gate Oxide
Gate
Polysilicon Field-Oxide
Source Drain
(SiO2)
n+ n+

p+ stopper
p-substrate

Bulk Contact

CROSS-SECTION of NMOS Transistor

Switch Model of NMOS Transistor

| VGS | Gate

Source Drain
(of carriers) (of
carriers)

Open (off) (Gate = ‘0’) Closed (on) (Gate = ‘1’)

Ron

| VGS | < | VT | | VGS | > | VT |

 Switch Model of PMOS Transistor

| VGS | Gate

Source Drain
(of carriers) (of carriers)

Open (off) (Gate = ‘1’) Closed (on) (Gate = ‘0’)

Ron

| VGS | > | VDD – | VT | | | VGS | < | VDD – |VT| |

 MOS transistors Symbols

D D

G G

S S Channe
NMOS Enhancement NMOS Depletion l
D D

G G B

S S

PMOS Enhancement NMOS with

Bulk Contact
 MOSFET Transistor

Symb
ol

L = 0.5-10 μm
W = 0.5-500 μm

SiO2 Thickness = 0.02-0.1

μm
Device characteristics depend on L,W, Thickness, doping
levels
Two-Terminal MOS Structure

Tox is 2nm to 50nm

 ⮚The equilibrium concentrations of mobile carriers in a semiconductor always obey the
Mass Action Law

(1)

⮚n = the mobile carrier concentrations of electrons

⮚p= the mobile carrier concentrations of holes
⮚ = the intrinsic carrier concentration of silicon, which is a function of the temp T.
At room temperature, i.e., T= 300 K, =1.45 x 10^10 cm-3.

⮚Assuming that the substrate is uniformly doped with an acceptor (e.g.,Boron) concentration
, the equilibrium electron and hole concentrations in the p-type substrate are approximated by

(2)
Energy Band Diagram of p-type Silicon Substrate
⮚The band-gap between the conduction band and the valence band for silicon is approximately
1.1 eV.

⮚The location of the equilibrium Fermi level within the band-gap is determined by the
doping type and the doping concentration in the silicon substrate.

⮚The Fermi potential , which is a function of temperature and doping, denotes the difference
between the intrinsic Fermi level , and the Fermi level

(3)
⮚For a p-type semiconductor, the Fermi potential can be approximated by

(4)

⮚For an n-type semiconductor (doped with a donor concentration ), the Fermi

potential is given by

(5)

⮚The definitions given in (4) and (5) result in a positive Fermi potential for n-type
material, and a negative Fermi potential for p-type material
⮚The electron affinity of silicon, which is the potential difference between the
conduction band level and the vacuum (free-space) level, is denoted by

⮚The energy required for an electron to move from the Fermi level into free
space is called the work function , and is given by

(6)
 Energy band diagrams of the MOS system

Energy band diagrams of the components that make up the MOS system

= Work Function of Metal = Electron affinity of Silicon

= Electron affinity of Oxide layer
 Energy band diagram of the combined MOS system

⮚Flat Band Voltage:It is the voltage corresponding to the potential difference applied
externally between the gate and the substrate, so that the bending of the energy bands
near the surface can be compensated, i.e., the energy bands become "flat.”

(7)
Accumulation,Depletion,Inversion
n-channel MOSFET Basic Operation
 The Threshold Voltage

For all practical purposes, there are four physical components of the threshold
voltage:

(i) the work function difference between the gate and the channel

(ii) the gate voltage component to change the surface potential at inversion

(iii) the gate voltage component to offset the depletion region charge

(iv) the voltage component to offset the fixed charges in the gate oxide
and in the silicon-oxide interface.
 The Threshold Voltage

The work function difference between the gate and the channel reflects the built-
in potential of the MOS system, which consists of the p-type substrate, the thin silicon
dioxide layer, and the gate electrode.

The first component of the threshold voltage

The externally applied gate voltage is required to achieve surface inversion

So the second component of the threshold voltage.
 The Threshold Voltage

The depletion region charge density at surface inversion ( )

The depletion region charge density can be expressed as a function of the source-to-
substrate voltage

The third component that offsets the depletion region charge is

Where is the gate oxide capacitance per unit area.

 The Threshold Voltage

⮚Due to the influence of a nonideal physical phenomenon, there always exists a fixed
positive charge density at the interface between the gate oxide and the silicon
substrate, due to impurities and/or lattice imperfections at the interface.

The (fourth) gate voltage component that is necessary to offset this positive
charge at the interface is

Combining all of these voltage components

For zero substrate bias, the threshold voltage is expressed as follows

With source-to-substrate bias voltage

 The Threshold Voltage

The generalized form of the threshold voltage can also be written as

Where

The most general expression of the threshold voltage can be written as

(14)

is the substrate-bias (or body-effect) coefficient

 The Threshold Voltage

⮚The threshold voltage expression given can be used both for n-channel and
p-channel MOS transistors.

⮚But some of the terms and coefficients in this equation have different polarities for the n-
channel (nMOS) case and for the p-channel (pMOS) case.

⮚The reason for this polarity difference is that the substrate semiconductor is p-type in an n-
channel MOSFET and n-type in a p-channel MOSFET.

▪ The substrate Fermi potential is negative in nMOS, positive in pMOS.

▪ The depletion region charge densities and are negative in nMOS,
positive in pMOS.
▪ The substrate bias coefficient is positive in nMOS, negative in pMOS.
▪ The substrate bias voltage is positive in nMOS, negative in pMOS.

Typically, the threshold voltage of an enhancement-type n-channel MOSFET is a

positive quantity, whereas the threshold voltage of a p-channel MOSFET is negative.
Threshold Voltage(Numerical Example)
 Substrate –bias Effect on Threshold Voltage

⮚It is seen that the threshold voltage variation is about 1.3 V over this range, which
could present serious design problems if neglected.

⮚So the substrate-bias effect is unavoidable in most digital circuits and that the circuit
designer usually must take appropriate measures to account for and/or to compensate
for the threshold voltage variations.
n-channel MOSFET Basic Operation
Types of MOSFET
Channel Length
SHORT CHANNEL EFFECT
 Short-Channel Devices

• A MOSFET device is considered to be short when the channel length is on

the same order of magnitude as the depletion region thickness of the

source and drain.

• In a Short-channel device we observe the following two physical

phenomena:

A) Mobility degradation

IDSAT = ((UnCox)/2).W.(Vgs – Vt)

B) Modification of threshold voltage VT

 Short-Channel Effects

• In particular five different short-channel effects can be distinguished:

1. Drain-induced barrier lowering and “Punch through”

2. Surface scattering

3. Velocity saturation

4. Impact ionization

5. Hot electrons
Drain-induced barrier lowering and
punch through
Surface Scattering
 Velocity Saturation
• The performance short-channel devices is also affected by velocity saturation,
which reduces the transconductance in the saturation mode.
• At low ey, the electron drift velocity vde in the channel varies linearly with the
electric field intensity. However, as ey increases above 104 V/cm, the drift
velocity tends to increase more slowly, and approaches a saturation value of
vde(sat)=107 cm/s around ey =105 V/cm at 300 K.
• The drain current is limited by velocity saturation instead of pinchoff.
• This occurs in shortchannel devices when the dimensions are scaled without
lowering the bias voltages.
• Using vde(sat), the maximum gain possible for a MOSFET can be defined as gm
=WCox Vde(sat )
Velocity Saturation
Impact Ionization
 Impact Ionization
• Another undesirable short-channel effect, especially in NMOS, occurs due to
the high velocity of electrons in presence of high longitudinal fields that can
generate electron-hole (e-h) pairs by impact ionization, that is, by impacting on
silicon atoms and ionizing them.
• It happens as follow: normally, most of the electrons are attracted by the drain,
while the holes enter the substrate to form part of the parasitic substrate current.
• Moreover, the region between the source and the drain can act like the base of
an npn transistor, with the source playing the role of the emitter and the drain
that of the collector.
 Impact Ionization
• If the aforementioned holes are collected by the source, and the corresponding
hole current creates a voltage drop in the substrate material of the order of .6V,
the normally reversed-biased substrate-source pn junction will conduct
appreciably.
• Then electrons can be injected from the source to the substrate, similar to the
injection of electrons from the emitter to the base.
• They can gain enough energy as they travel toward the drain to create new eh
pairs.
• The situation can worsen if some electrons generated due to high fields escape
the drain field to travel into the substrate, thereby affecting other devices on a
chip.
Hot Electrons
 The modification of the VT due to
Short-Channel Effects (SCE)

• The threshold Voltage at Zero Bias for large MOS transistors :

• Let ΔLS and ΔLD represent the lateral extent of the depletion
regions associated with the source junction and the drain
junction, respectively.
• Then, the bulk depletion region charge contained within the
trapezoidal region is
The junction depletion region depths can be approximated by

with the junction built-in voltage

MOSFET CAPACITANCES
MOSFET CAPACITANCE
OXIDE RELATED CAPACITANCE
• voltage-independent Capacitance.

• voltage-dependent Capacitance
Cgs
Cgd
Cgb
 OXIDE RELATED CAPACITANCE
cut-off mode

Cgs = Cgd= 0

Cgb = Cox. W. L
 OXIDE RELATED CAPACITANCE
Linear mode

Cgs = Cgd= ½ Cox. W. L

Cgb = 0
 OXIDE RELATED CAPACITANCE
Saturation mode

Cgs = 2/3 Cox. W. L

Cgb = Cgd = 0
 OXIDE RELATED CAPACITANCE

Approximate oxide capacitance values for three operating

modes of the MOS Transistor
JUNCTION CAPACITANCES
JUNCTION CAPACITANCES
JUNCTION CAPACITANCES
JUNCTION CAPACITANCES
JUNCTION CAPACITANCES
JUNCTION CAPACITANCES
 The LEVEL 2 Model Equations
• The saturation condition is reached when the
channel (inversion) charge at the drain end becomes
equal to zero.
• The saturation voltage VDSAT can be calculated as

• The saturation mode current is

Thank You