Computer Organization

Lecture IV
Presented by Tandoh Lawrence (PhD)
MID TRIMESTER
1. What is the binary representation of the following denary number:
10765? Please show working. 10101000001101
2. Convert the following binary number into denary: 111010101.
Please show working.469
3. With the aid of a truth table, Karnaugh map, and a diagram, explain
how the logic gate circuit for a half adder is designed.
4. Please explain what happens when there is an overflow bit of “1”
in:
a. One’s complement
b. Two’s complement
Other logic gates under
combinational logic
• There are other logic circuits that fall under the combinational logic
that do not include circuits that implement arithmetic
• These circuits are
• Decoders
• Multiplexers
• Programmable logic arrays
• These combinational logic circuits generally have fixed structures and
therefore we will only study these without going into further details
Decoders overview
• a logic circuit that converts a coded input to a “decoded” output by converting the input
into a different format
• Binary decoders can be used to:
• Convert BCD/binary value into “denary format”, “octal format” or “hexadecimal format”
• Decoding the opcode of an instruction (Decode stage of the FDE Cycle)
• An “n” input decoder can have a maximum of 2n outputs
• Input will thus always be higher than output
• Usually however, the maximum number of outputs is used
• Usually, the value of the “ith” output node is one if the value of the n-bit input is “i” whilst
the output on all other nodes is zero
• There are four popular decoders: 2-to-4 decoder, 3-to-8 decoder and 4-to-16 decoder
• We will only consider the first two
2-to-4 binary decoder
• this decoder has 2 inputs and 4 outputs
• The truth table, block and logic gate diagram for the decoder are shown below
• Can be used to convert binary numbers (0-3) into denary
3-to-8 binary decoder
• this decoder has 3 inputs and 8 outputs
• Structure is very similar to the 2-to-4 binary decoder
• The truth table, block and logic gate diagram for the decoder are
shown below
• Can be used to convert binary numbers (0-7) into octal
Multiplexers overview
• Multiplexers are also known as MUX’s
• Accept “n” inputs and return a single (1) output
• Employ the use of select lines that have states and are used to determine
which input is forwarded to the output line
• There exists a relationship between the number of input lines “n” and the
number of select lines “m”
• 2m = n
• Hence:
• For 2 input lines m = 1
• For 4 input lines m = 2
• For 8 input lines m = 3 and so on
• In summary, a multiplexer has “n” input lines, 2m select lines and a single
output line
• Used for:
• Conversion
• Selecting a single output from several
• Converting parallel signals into serial for transmission over a single line
• Implementing a scheduler which determines which tasks in a pool should be
executed first
How the multiplexer works I
• On the inside the MUX works by simply deciding based on the value
of the select line(s) which (one) of the inputs should be connected to
the output
• Popular examples of MUX’s include 2-to-1, 4-to-1, and 8-to-1
• Just as it is the case with all logic circuits, multiplexers can also be
designed using the standard design process to which we have been
introduced
• Let us consider the design of the simplest multiplexer 2-to-1
How the multiplexer works II
(design of 2-to-1 multiplexer)
• Below we present the truth table, K-map and logic circuit diagram for a 2-to-1 multiplexer
• In this multiplexer, input “A”/I0 is transferred to the output (Y) when the select value (S) is
“0” and the “B”/I1 input value is transferred to the output when the select has a state of
“1”
Select (S) A B Output (Y) S\AB 00 01 11 10
0 0 0 0 0 0 0 1 1
0 0 1 0 1 0 1 1 0
0 1 0 1
0 1 1 1 Sum of products =
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
Beyond the 2-to-1 MUX
• The situation becomes more complex with multiplexers that have a larger number
of inputs
• The design process however remains the same
• Note that the number of select lines will increase with an increasing number of
inputs based on given relation
• Note that the output of the multiplexer will solely depend on the states of the
select lines
• For example, lets consider a 4-to-1 multiplexer with inputs (A, B, C, and D) which
will have a total of 2 select lines since 22 = 4
• When S1S2 = 00 output will be “A”
• When S1S2 = 01 output will be “B”
• When S1S2 = 10 output will be “C”
• When S1S2 = 11 output will be “D”
Programmable logic array (PLA)
• Digital circuits that consist of an array of and gates and an array of AND
gates followed by an array of OR gates
• Both the AND and OR gates are programmable
• During the design of the integrated circuit (IC) it has no specific purpose
• Purpose is determined later on when the IC is coded
• Coding/programming is hardware based and does not include any
programming language
• PLA’s take in “n” inputs and return “m” outputs
• Used as a:
• Counter
• Decoder
Structure of a PLA
• Each input of the PLA consists of the actual input value as well as its complement
• The complement is implemented with the aid of a not gate
• The output of a PLA forms a sum of products just as the output of a K-map
• The AND gates form the products whilst the OR gates form the sum
• Below is a block diagram and a logic circuit for a PLA
Reset-Set (R-S) Latch
• Consider the truth table and logic circuit below
• We start with all zeros
• Note that we can only change the state of A
• If we set input of A to 1 then the value of out will change to 1
• This will set the value of B to 1
• At this point, the value of out will still remain 1
• If we reset the value of A to 0, the value of out remains at 1 and B remains at 1
• The logic circuit will remain in this state (store the value)
• We can call this circuit a “set latch” since we are only able to set the value of the out but not
reset it
• Question: is there a way to reset the value of out to 0 without resetting the entire circuit???
A A B Out
Out
B 0 0 0
0 1 1
1 0 1
1 1 1
Reset-Set (R-S) Latch
• To address the previously encountered problem we use the R-S Latch
• R-S Latches can store states
• R-S Latches can also be set and reset
• They can be constructed using NAND or NOR gates
• We will consider NOR gates
• Our main objective here is to track the value of the topmost output (Q)
• The values of Q and not are supposed to be opposite at all times for the circuit to be valid
• Note how setting both S and R to 1 results in an illegal state (Q and are both 0 (same))
• Latch means locked in the current state and setting R to 1 will not change the stat of Q. Only setting S to
1 will
• Question: How to determine which output is taken when we set the state of the top most input to 1???
• Question: How do we eliminate the illegal state???
Storage Elements: Gated Data (D)
Latch I

•The Gated Data (D) Latch solves the problem of the illegal state
•The truth table shows the inputs and corresponding inputs of the gated d-latch
•Note how the latch stays locked and nothing happens when the value of E (enable) is 0
•The output Q however takes the state of the input D (data) when E is one
•Q will retain this state as long as E is 0
Storage Elements: Gated Data (D)
Latch II

•The gated D latch allows us to pass and store states

•It can be used in the creation of registers
•Registers are a type of computer memory used to quickly accept, store, and transfer data
and instructions that are being used immediately by the CPU
•A processor register may hold an instruction, a storage address,
or any data (such as bit sequence or individual characters)
•The computer needs processor registers for manipulating data and a
register for holding memory addresses
•The register holding the memory location is used to calculate the address of the
next instruction after the execution of the current instruction is completed.
 Storage Elements: Gated Data (D)
Latch III
•Gated d-latches can also be used to implement computer memory
•Whilst registers store data that the CPU is currently processing, memory stores data that will be
required for processing
•A memory can be defined as a large number of addressable fixed size locations
•n bit addresses allow the addressing of 2n locations
•Example: 24 bits can address 224 = 16,777,216 locations (i.e. 16M locations)
•Computers are either byte or word addressable - i.e. each memory location holds either 8 bits
(1 byte), or a full standard word for that computer (16 bits for the LC-3, more typically 32 bits,
though now many machines use 64 bit words)
•Normally, a whole word is written and read at a time:
•If the computer is word addressable, this is simply a single address location.
•If the computer is byte addressable, and uses a multi-byte word, then the word
address is conventionally either that of its most significant byte (big endian machines)
or of its least significant byte (little endian machines).
OTHER STUFF
 Memory Hierarchy

• An enhancement that organizes memory such that access time is minimized

• Was developed on a program behavior known as locality of reference
• Divides memory into two main types
• External memory
• Internal memeory
Memory Hierarchy
• External Memory or Secondary Memory – Comprising of Magnetic
Disk, Optical Disk, Magnetic Tape i.e. peripheral storage devices which
are accessible by the processor via I/O Module.
• Internal Memory or Primary Memory – Comprising of Main Memory,
Cache Memory & CPU registers. This is directly accessible by the
processor.
Memory Hierarchy
• Registers: Registers are small, high-speed memory units located in the
CPU. They are used to store the most frequently used data and
instructions. Registers have the fastest access time and the smallest
storage capacity, typically ranging from 16 to 64 bits.
• Cache Memory: Cache memory is a small, fast memory unit located
close to the CPU. It stores frequently used data and instructions that
have been recently accessed from the main memory. Cache memory
is designed to minimize the time it takes to access data by providing
the CPU with quick access to frequently used data.
Memory Hierarchy
• Main Memory: Main memory, also known as RAM (Random Access
Memory), is the primary memory of a computer system. It has a
larger storage capacity than cache memory, but it is slower. Main
memory is used to store data and instructions that are currently in
use by the CPU.
• Secondary Storage: Secondary storage, such as hard disk drives (HDD)
and solid-state drives (SSD), is a non-volatile memory unit that has a
larger storage capacity than main memory. It is used to store data and
instructions that are not currently in use by the CPU. Secondary
storage has the slowest access time and is typically the least
expensive type of memory in the memory hierarchy.
Memory Hierarchy
Other things to note
• Capacity: It is the global volume of information the memory can store. As we move
from top to bottom in the Hierarchy, the capacity increases.
• Access Time: It is the time interval between the read/write request and the
availability of the data. As we move from top to bottom in the Hierarchy, the access
time increases.
• Performance: Earlier when the computer system was designed without Memory
Hierarchy design, the speed gap increases between the CPU registers and Main
Memory due to large difference in access time. This results in lower performance of
the system and thus, enhancement was required. This enhancement was made in the
form of Memory Hierarchy Design because of which the performance of the system
increases. One of the most significant ways to increase system performance is
minimizing how far down the memory hierarchy one has to go to manipulate data.
• Cost per bit: As we move from bottom to top in the Hierarchy, the cost per bit
increases i.e. Internal Memory is costlier than External Memory.
Sequential Logic Circuits - 1
• The concept of state
• the state of a system is a “snapshot” of all relevant elements at a
moment in time.
• a given system will often have only a finite number of possible
states.
• e.g. the game of tic-tac-toe has only a certain number of
possible dispositions of Xs and Os on the 3x3 grid.
• A given game of tic-tac-toe will progress through a subset of
these possible states (until someone wins) - i.e. it traverses a
specific path through “state space”, one move at a time.
• For many systems, we can define the rule which determine
under what conditions a system can move from one state to
another.
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Sequential Logic Circuits - 2
input output
Combinational
Logic Circuit

Storage
Element

• The output is a function of the current input and the previous state
• It is computed by the combinational logic circuit
• The state is stored in the storage element
• The new state is also a function of the previous state and the current
input
• This can work only if we make transitions from one state to another at
well-defined times - this is why they are called sequential circuits.
3 - 25
Finite State Machines
• Many systems meet the following five conditions:
• A finite number of states
• A finite number of external inputs
• A finite number of external outputs
• An explicit specification of all allowed state transitions
• An explicit specification of the rules for each external output value

• A microprocessor is a perfect candidate for description as a

FSM.

3 - 26
 Structure of an operating system

OUT OF THE ABOVE STRUCTURE WE CONCENTRATED ON THE CPU AND RAM COMPONENTS
HOWEVER, IT IS IMPORTANT THAT WE BEAR IN MIND THAT A LOT MORE GOES INTO THE MACHINE CALLED THE COMPUTER