Clock Uncertainty
What is Clock Uncertainty?
Clock uncertainty represents the worst-case timing
variation between clock edges during data launch and
capture, caused by factors like clock jitter, skew, and
other external disturbances.
It defines a window within which the clock edge may
arrive at any time.
These variations can alter the clock edge arrival time at
the sink pin.
Pre-CTS
Clock Uncertainty = Jitter + Skew + Phase Error + Margin
Setup Uncertainty = Jitter + Skew + Setup Margin
Hold Uncertainty = Skew + Hold Margin
Post-CTS
Setup Uncertainty = Jitter + Setup Margin
Hold Uncertainty = Hold Margin
Set Clock Uncertainty
• set_clock_uncertainty -setup 0.15 [get_clock clk_core]
• set_clock_uncertainty -hold 0.05 [get_clock clk_core]
Setup analysis (AAT < RAT): Hold analysis (AAT > RAT):
Required Arrival Time (RAT): RAT:
= T + Skew – Setup Uncertainty – Setup = Hold time + Skew + Hold Uncertainty
= 1000ps + 100ps – 150ps – 30ps = 20ps + 100ps + 50ps
= 920ps = 170ps
Clock Skew
The difference in arrival time of the clock edge at clock
pins of different sequential elements is called clock skew.
Types of Skew
A. Based on Polarity:
1. Positive Skew
2. Negative Skew
B. Based on Scope:
1. Local Skew
2. Global Skew
Positive Clock Skew
Definition:
- Clock arrives early at capture FF (R2) than launch FF (R1).
- Negative Skew: t_clk1 > t_clk2 → δ < 0
Setup Constraint:
T + δ ≥ t_cq + t_logic + t_su
⇒ T ≥ t_cq + t_logic + t_su - δ
Hold Constraint:
t_hold + δ ≤ t_cdlogic + t_cdreg
⇒ t_hold ≤ t_cdlogic + t_cdreg - δ
Negative Clock Skew
Definition:
- Clock arrives later at capture FF (R2) than launch FF (R1).
- Positive Skew: t_clk2 > t_clk1 → δ > 0
Setup Constraint:
T + δ ≥ t_cq + t_logic + t_su
➔ T ≥ t_cq + t_logic + t_su - δ
Hold Constraint:
t_hold + δ ≤ t_cdlogic + t_cdreg
⇒ t_hold ≤ t_cdlogic + t_cdreg - δ
Types of Skew based on scope
1) Local Skew :- The clock arrival time
difference between two nearby or logically
connected flip-flops.
Skew between FFs in the same logic path
(e.g., launch and capture FF).
2) Global Skew :- The difference in arrival time
of the clock signal between the furthest flip-
flops.
Ex. Skew between FF at top-left and FF at
bottom-right corner of a chip.
Clock Jitter
• Jitter is the deviation in the timing of clock edges
from their ideal positions.
• Clock jitter is typically caused by clock generator
circuitry, noise, power supply variations, interference
from nearby circuitry etc.
• Based on how it is measured in a system, jitter is of
following types:
1) Period Jitter
2) Cycle to Cycle jitter
3) Phase Jitter
1. Period jitter
Variation in duration of each individual clock period
from its ideal value.
It can be specified an average value of of clock period
deviation over the selected cycles(RMS value) or can be
the difference between maximum deviation & minimum
deviation within the selected group
2. Cycle-to-Cycle Jitter
Difference between two adjacent clock periods.
Indicates short-term instability.
This is used to determine the high frequency jitter
3. Phase jitter
Phase Jitter refers to the variation of a clock edge from
its ideal phase position over time.
Effect of Jitter on Setup and Hold Time Equations
Setup Time Equation
Clk_to_Q [REG1] + Comb Delay ≤ Clock Period - 2Tjitter - Tsetup[REG2]
Clock Period ≥ Clk_to_Q[REG1] + Comb Delay + Tsetup[REG2] + 2Tjitter
• Here,
Required Time = Clock Period - 2Tjitter- Tsetup[REG2]
Arrival Time = Clk_to_Q [REG1] + Comb Delay
So, Setup Slack = Required Time – Arrival Time
• Clock Jitter Degrades the Performance (Setup)
Effect of Jitter on Setup and Hold Time Equations
Hold Time Equation
Clk_to_Q [REG1] + Comb Delay ≤ Hold Check[0]+
Thold[REG2]
• Here,
Required Time = Hold Check[0]+ Thold[REG2]
Arrival Time = Clk_to_Q [REG1] + Comb Delay
So, Hold Slack = Required Time – Arrival Time
• Clock Jitter Degrades the Performance (Setup) And also
make harder gto meet Hold requirements
