Unit I

Introduction to IC technology
Topics
• MOS, PMOS, NMOS, CMOS and BiCMOS
Technologies:
• Oxidation
• Lithography
• Diffusion
• Ion implantation
• Metallization
• Encapsulation
• Probe testing
• I n tegrated Resistors and
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 Acronym of VLSI
• V -> Very
• L -> Large
• S -> Scale
• I -> Integration

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 Types of Field Effect Transistors
(The Classification)
n-Channel JFET
FET p-Channel
» JFET
JFET
MOSFET (IGFET)

Enhancement Depletion
MOSFET MOSFET

n-Channel p-Channel n-Channel p-Channel

EMOSFET EMOSFET DMOSFET DMOSFET

MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor)

Primary component in high-density VLSI chips such as memories and microprocessors
JFET (Junction Field-Effect Transistor)
Finds application especially in analog and RF circuit design
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 Metal Oxide Semiconductor(MOS)
• Advantages of FET over conventional Transistors

• Unipolar device i. e. operation depends on only one type of charge carriers (h or e)

• Voltage controlled Device (gate voltage controls drain current)

• Very high input impedance (109-1012 )

• Source and drain are interchangeable in most Low-frequency applications

• Low Voltage Low Current Operation is possible (Low-power consumption)

• Less Noisy as Compared to BJT

• No minority carrier storage (Turn off is faster)

• Very small in size, occupies very small space in ICs

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 Switch Model of NMOS Transistor

| VGS | Gate

Source Drain
(of carriers) (of carriers)

Open (off) (Gate = 'O') Closed (on) (Gate = '1')

Ron

| VGS | < | VT | | VGS | > | VT |

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 Switch Model of PMOS Transistor

| VGS | Gate

Source Drain
(of carriers) (of carriers)

Open (off) (Gate = '1') Closed (on) (Gate = 'O')

Ron

| VGS | > | VDD – | VT | | | VGS | < | VDD – |VT| |

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 MOS transistors Symbols
D D

G G

S S
NMOS Enhancement NMOS Depletion Channel

D D

G G B

S S

PMOS Enhancement NMOS with

Bulk Contact

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 MOSFET Circuit Symbols
• (g) and (i) are the most
commonly used symbols
in VLSI logic design.
• MOS devices are
symmetric.
• In NMOS, n+ region at
higher voltage is the
drain.
• In PMOS p+ region at
lower voltage is the drain

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The NMOS Transistor Cross Section
n areas have been doped with donor ions
(arsenic) of concentration ND - electrons are
the majority carriers
Gate oxide
Polysilicon
W Gate
Source Drain Field-Oxide
n+ n+ (SiO2)
L
p substrate
p+ stopper

Bulk (Body)

p areas have been doped with acceptor ions

(boron) of concentration NA - holes are the
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 Carriers and Current
• Carriers always flow from the Source to Drain
• NMOS: Free electrons move from Source to
Drain.
– Current direction is from Drain to Source.
• PMOS: Free holes move from Source to
Drain.
– Current direction is from Source to Drain.

12
 The MOSFET Channel
• Under certain conditions, a thin channel can
be formed right underneath the Silicon-
Dioxide insulating layer, electrically connecting
the Drain to the Source. The depth of the
channel (and hence its resistance) can be
controlled by the Gate's voltage. The length of
the channel (shown in the figures above as L)
and the channel's width W, are important
design parameters.
14
 REGION OF OPERATION
CASE-1 (No Gate Voltage)
• Two diodes back to back exist in series.
• One diode is formed by the pn junction
between the n+ drain region and the p-type
substrate
• Second is formed by the pn junction between
the n+ source region and the p-type substrate
• These diodes prevent any flow of the current.
• There exist a very high resistance.
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 NMos Cut View

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 REGION OF OPERATION
Creating a channel
• Apply some positive voltage on the gate
terminal.
• This positive voltage pushes the holes
downward in the substrate region.
• This causes the electrons to accumulate under
the gate terminal.
• At the same time the positive voltage on the
gate also attracts the electrons from the n+
region to accumulate under the gate terminal.
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 REGION OF OPERATION
Creating a channel
• When sufficient electrons are accumulated under the
gate an n-region is created, connecting the drain and
the source
• This causes the current to flow from the drain to
source
• The channel is formed by inverting the substrate
surface from p to n, thus induced channel is also called
as the inversion layer.
• The voltage between gate and source called vgs at
which there are sufficient electron under the gate to
form a conducting channel is called threshold voltage
Vth.

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 Formation of Channel
• First, the holes are
repelled by the
positive gate voltage,
leaving behind
negative ions and
forming a depletion
region. Next,
electrons are attracted
to the interface,
creating a channel
("inversion layer").

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 MOS Transistor Current direction
• The source terminal of an n-channel(p-channel)
transistor is defined as whichever of the two terminals
has a lower(higher) voltage.
• When a transistor is turned ON, current flows from the
drain to source in an n-channel device and from source
to drain in a p-channel transistor.
• In both cases, the actual carriers travel from the source
to drain.
• The current directions are different because n-channel
carriers are negative, whereas p-channel carriers are
positive.

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 MOS I/V

For a NMOS, a necessary

condition for the channel to exist is:


VGS
VTH
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 REGION OF OPERATION
Applying small Vds
• Now we applying some small voltage between
source and drain
• The voltage Vds causes a current to flow from
drain to gate.
• Now as we increase the gate voltage, more
current will flow.
• Increasing the gate voltage above the threshold
voltage enhances the channel, hence this mode is
called as enhancement mode operation.
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 Operation – nMOS Transistor
• Accumulation Mode - If Vgs < 0, then an
electric field is established across the
substrate.
• Depletion Mode -If 0<Vgs< Vtn, the region
under gate will be depleted of charges.
• Inversion Mode – If Vgs > Vtn, the region
below the gate will be inverted.

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 Operation – nMOS Transistor

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 Operation – nMOS Transistor

V
=0

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 Operation – nMOS Transistor

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 Operation – nMOS Transistor

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 Operation – nMOS Transistor

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 Operation – nMOS Transistor

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 Voltage-Dependent Resistor
• The inversion channel
of a MOSFET can be
seen as a resistor.
• Since the charge
density inside the
channel depends on
the gate voltage, this
resistance is also
voltage-dependent.

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 Channel Potential Variation
• “ince there's a
channel resistance
between drain and
source, and if drain is
biased higher than
the source, then the
potential between
gate and channel will
decrease from
source to drain.
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 Channel Pinch-Off
• As the potential
difference between drain
and gate becomes more
positive, the inversion
layer beneath the
interface starts to pinch
off around drain.
• When VD s> VGs - Vth,
the channel at drain
totally pinches off, and
when VD s< VGs - Vth,
the channel length starts
to decrease.
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 Transistor in Saturation Mode
Assuming VGS > VT
VGS
VDS > VGS - VT
S G VDS

D ID

n+ - V -V + n+
GS T

Pinch-off

The current remains constant (saturates).

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 During "pinchoff"
 Does this mean that the current i =0 ? Actually, it does not. A MOSFET
that is "pinched off" at the drain end of the channel still conducts current:

The large E in the depletion region surrounding the drain will sweep
electrons across the end of the pinched off channel to the drain.

This is very similar to the operation of the BJT. For an npn BJT, the electric
field of the reversed biased CBJ swept electrons from the base to the
collector regions.

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 N-Channel MOSFET characteristics

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 Enhancement-Mode PMOS
Transistors: Structure
• p-type source and drain
regions in n-type substrate.
• vGS < 0 required to create p-
type inversion layer in channel
region
• For current flow, vGS < vTP
• To maintain reverse bias on
source-substrate and drain-
substrate junctions, vSB <
0 and vDB < 0
• Positive bulk-source potential
causes VTP to become more
negative

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P-channel MOSFET characteristics

saturation linear

p transistor

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 Depletion-Mode MOSFETS
• NMOS transistors with
• Ion implantation process
is used to form a built-in
n-type channel in the
device to connect source
and drain by a resistive
channel
• Non-zero drain current V TN

for vGS = 0; negative vGS 0
required to turn device
off.

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 pMOS are 2.5 time slower than
nMOS due to electron and
hole mobilities

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 Basic processes involved in fabricating
Monolithic ICs
1. Silicon wafer (substrate) preparation
2. Epitaxial growth
3. Oxidation
4. Photolithography
5. Diffusion
6. Ion implantation
7. Metallization
8. Testing
9. Assembly processing & packaging

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 Oxidation
 Formation of silicon dioxide layer on the surface of Si wafer
1. protects surface from contaminants
2. forms insulating layer between conductors
3. form barrier to dopants during diffusion or ion implantation
4. grows above and into silicon surface

 Dry oxidation: lower rate and higher quality

 Wet oxidation: higher rate and lower quality

1. SiO2 is an extremely hard protective coating & is unaffected

by almost all reagents except by hydrochloric acid. Thus it
stands against any contamination.
2. By selective etching of SiO2, diffusion of impurities through
carefully defined through windows in the SiO2 can be
accomplished to fabricate various components.

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 Oxidation
The silicon wafers are stacked up in a quartz boat & then
inserted into quartz furnace tube. The Si wafers are raised
to a high temperature in the range of 950 to 1150oC & at
the same time, exposed to a gas containing O2 or H2O or
both. The chemical action is

Si + 2H2O-----------> Si O2+ 2H2 (Wet )

Si + O2 -------------> SiO2 (Dry )

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 Photolithograph
y
• Coat wafer with photoresist
(PR)
• Shine UV light through mask
to selectively expose PR
UV Light
• Use acid to dissolve exposed Mask
PR Photoresist

• Now use exposed areas for Wafer

– Selective doping
– Selective removal of material
under exposed PR

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 Adding Materials
• Add materials on top of
silicon Added Material
– Polysilicon (e.g. Polysilicon)

– Metal
– Oxide (SiO2) - Insulator
• Methods Silicon

– Chemical deposition
– Sputtering (Metal ions)
– Oxidation

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 Oxide (Si02) - The Key Insulator
• Thin Oxide
– Add using chemical deposition
– Used to form gate insulator & block active areas
• Field Oxide (FOX) - formed by oxidation
– Wet (H20 at 900oC - 1000oC) or Dry (O2 at 1200oC)
– Used to insulate non-active areas
SiO2 Thin Oxide FOX SiN / SiO2
FOX

Silicon Wafer Silicon Wafer

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 Patterning Materials using
Photolithography
• Add material to wafer
• Coat with photoresist Added Material
(e.g. Polysilicon)
• Selectively remove
photoresist
• Remove exposed
Silicon
material
• Remove remaining
PR

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 Diffusion
• Introduce dopant via epitaxy or
ion implant e.g. Arsenic (N),
Boron (P) Blocking Material
• Allow dopants to diffuse at (Oxide)
high
temperature Diffusion
• Block diffusion in selective areas
using oxide or PR
• Diffusion spreads both vertically, Silicon
horizontally

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 Ion Implantation
Process Conditions Focus Beam trap and Neutral beam
and
Flow Rate: 5 sccm gate plate
beam path
Pressure: 10-5 gated

Torr
Accelerating Voltage: Neutral beam trap Y - axis X - axis Wafer in wafer
5 and beam gate
scanner
scanner process chamber

Gases
to 200 keV Solids
Equipment Ground
Ar Ga Resolving
Aperture 180 kV
AsH3 In
B11F3 * Acceleration Tube
He Sb 90° Analyzing
N2 Liqui Magnet Terminal

PH3 ds Ion Source Ground

20 kV

SiH4 Al(
SiF 4 C
Slide
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 Metallization
• Sputter on aluminum over whole wafer
• Pattern to remove excess metal, leaving wires

M e ta l

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+
n well
p substrate

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Slide 60
 nMOS fabrication steps
1.Processing is carried out on a thin wafer cut from a single crystal of silicon of high purity into which the
required p-impurities are introduced as the crystal is grown.
2.A layer of silicon dioxide (Si02) is grown all over the surface of the wafer to protect the surface, act as a
barrier to dopants during processing, and provide a generally insulating substrate on to which other layers
may be deposited and patterned.
3.The surface is now covered with a photoresist which is deposited onto the wafer and spun to achieve an
even distribution of the required thickness.
4.The photoresist layer is then exposed to ultraviolet light through a mask which defines those regions into
which diffusion is to take place together with transistor channels.
5.These areas are subsequently readily etched away together with the underlying silicon dioxide so that the
wafer surface is exposed in the window defined by the mask.
6.The remaining photoresist is removed and a thin layer of Si02 is grown over the entire chip surface and then
polysilicon is deposited on top of this to form the gate structure.
7.Further photoresist coating and masking allows the polysilicon to be patterned (as shown in Step 6) and
then the thin oxide is removed to expose areas into which
8.Thick oxide (Si02) is grown over all again and is then masked with photoresist and etched to expose
selected areas of the polysilicon gate and the drain and source areas where connections (i.e. contact cuts)
are to be made.
9.The whole chip then has metal (aluminium) deposited over its surface. This metal layer is then masked
and etched to form the required interconnection pattern.

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 1. Substrate
p

……………………………………… Thick oxide

2.
(1m)

3. ………………………………………
………………………………………
Photoresist

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 UV light

Mask

……………………………………
4. …………………………………………

5. ……………………
……………………………………………… Window in
oxide

………… p

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 ……………………………………………………
……
………… ……
…………………
6. …… …… … … Patterned
………… … … … Poly. (1-2 m)
………… p
On thin oxide
( 800-1000A0 )

7. ………… n+ diffusion
……………………………
…… …………
…………
…… (1 m deep)

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 …… … …… …
8. ……
……
…
……… ……
… …… ………
……
…
………
……… …………
…
… ……
…
…………
… …….
…… ………… Contact holes
……… … …
……………………………
… … (cuts)

… ………
… … p
…

…… … …… …
9. ……
……
…
…
………
……
… …… … ……
……
…
… …
…… Patterned
………
…………
…… ……
…….
…… …………
…………
…………
………… … … ……… Metallization
………
……
… (aluminum
…… ………
p … 1 m)

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 CMOS FABRICATION

• There are a number of approaches to CMOS

fabrication, including the p-well, the n-well,
the twin-tub, and the silicon-on-insulator
processes.

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 The p-well Process
In primitive terms, the structure consists of an n-
type substrate in which p-devices may
be formed by suitable masking and diffusion
and, in order to accommodate n-type devices,
a deep p-well is diffused into the n-type
substrate as shown.

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 The p-well CMOS fabrication
In all other respects-masking, patterning, and diffusion-the process is similar to
nMOS fabrication. In summary, typical processing steps are:
• Mask 1 - defines the areas in which the deep p-well diffusions are to take place.
•Mask 2 - defines the thinox regions, namely those areas where the thick oxide is
to be stripped and thin oxide grown to accommodate p- and n-transistors and wires.
• Mask 3 - used to pattern the polysilicon layer which is deposited after the thin
oxide.
•Mask 4 - A p-plus mask is now used (to be in effect "Anded" with Mask 2) to define
all areas where p-diffusion is to take place.
•Mask 5 - This is usually performed using the negative form of the p-plus mask and
defines those areas where n-type diffusion is to take place.
• Mask 6 - Contact cuts are now defined.
• Mask 7 - The metal layer pattern is defined by this mask.
Mask 8 - An overall passivation (overglass) layer is now applied and Mask 8 ts
needed to define the openings for access to bonding pads.

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 SiO2

1. …………………… … p-well
p
…………n……… (4-5 m)

Polysilicon

… …… … Thin oxide
2.
p and
n polysilicon

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 p-diffusion

P+ mask
… …… … (positive)
3.
p

P+ mask n-diffusion
(negative)

… …… …
4.
p

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 Polysilicon
Oxide
n-diffusion
P-
diffusion

Vin

Vout
VDD VSS

CMOS p-well inverter showing VDD and VSS substrate connections

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 Polysilicon
Oxide
n-diffusion
P-
diffusion

Vin

Vout
VDD VSS

CMOS n-well inverter showing VDD and VSS substrate connections

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 The n-well Process
• As indicated earlier, although the p-well process is widely used, n-well fabrication
has also gained wide acceptance, initially as a retrofit to nMOS lines.

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 The twin-tub-Tub Process

A logical extension of the p-well and n-well approaches is

the twin-tub fabrication process.

Here we start with a substrate of high resistivity n-type

material and then create both .. n-well and p-well
regions. Through this process it is possible to preserve the
performance of n-transistors without compromising the
p-transistors. Doping control is more readily achieved
and some relaxation in manufacturing tolerances results.
This is particularly important as far
as latch-up is concerned.
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 Polysilicon
Oxide
n-diffusion
P-
diffusion
Vin

Vout
VDD VSS

Epitaxial
n well p well layer

n substrate

Twin-tub structure
( A logical extension of the p-well and n-
well)
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 Bi-CMOS
Bipolar compatible CMOS(Bi-CMOS) technology:
Introduced in early 1980s
Combines Bipolar and CMOS logic

Low power dissipation High speed

High packing density High output
drive
High Noise Margin High transconductance
(gm)
High input impedance
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 Features
The objective of the Bi-CMOS is to combine bipolar and CMOS so as to
exploit the advantages of both the technologies.

Today Bi-CMOS has become one of the dominant technologies used for
high speed, low power and highly functional VLSI circuits.

The process step required for both CMOS and bipolar are almost similar

The primary approach to realize high performance Bi-CMOS devices is

the
addition of bipolar process steps to a baseline CMOS process.

The Bi-CMOS gates could be used as an effective way of speeding up

the VLSI circuits.

The applications of Bi-CMOS are vast.

Advantages of bipolar and CMOS circuits can be retained in Bi-

CMOS chips.
 Characteristics of Bipolar Technology
Higher switching speed

Higher current drive per unit area, higher gain

Generally better noise performance and better high

frequency characteristics

Improved I/O speed (particularly significant with the growing

importance
of package limitations in high speed systems).

high power dissipation

lower input impedance (high drive current)

low packing density

low delay sensitivity to load 78

It6/3is/20e15ssentially unidirectional.
 Characteristics of CMOS
Lower static power dissipation

Higher noise margins

Higher packing density

High yield with large integrated complex functions

High input impedance (low drive current)

Scalable threshold voltage

High delay load sensitivity

Low output drive current (issue when driving large capacitive loads)

Bi-directional capability (drain & source are interchangeable)

A near ideal switching device,

Low gain
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 Bi-CMOS FABRICATION PROCESS

CMOS process BI-POLAR

process
1 . N-well 1. n+ sub-collector
2. P base doping(extra
step)
3. PMOS source 3. p+ base contact
and drain 4. n+ emitter
4. NMOS source
and drain

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 npn-BJT Fabrication

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 BJT Processing
1. Implantation of the buried n+ layer

2. Growth of the epitaxial layer

3. p+ isolation diffusion
n+ layer p+ layer n+ layer
4. Base p-type diffusion p-base layer

5. Emitter n+ diffusion n+ buried layer

6. p+ ohmic contact
p-substrate
7. Contact etching

8. Metal deposition and etching

9. Passivation and bond pad opening

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 BJT Processing
1. Implantation of the buried n+ layer

2. Growth of the epitaxial layer

3. p+ isolation diffusion

4. Base p-type diffusion

5. Emitter n+ diffusion

6. p+ ohmic contact

7. Contact etching

8. Metal deposition and etching

9. Passivation and bond pad opening p-substrate

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 BJT Processing
1. Implantation of the buried n+ layer

2. Growth of the epitaxial layer

3. p+ isolation diffusion

4. Base p-type diffusion

5. Emitter n+ diffusion

6. p+ ohmic contact
n epi layer
7. Contact etching
n+ buried layer
8. Metal deposition and etching

9. Passivation and bond pad opening p-substrate

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 BJT Processing

p+ isolation layer

p+ isolation layer
1. Implantation of the buried n+ layer

2. Growth of the epitaxial layer

3. p+ isolation diffusion

4. Base p-type diffusion

5. Emitter n+ diffusion

6. p+ ohmic contact

7. Contact etching
n+ buried layer
8. Metal deposition and etching

9. Passivation and bond pad opening p-substrate

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 BJT Processing

p+ isolation layer

p+ isolation layer
1. Implantation of the buried n+ layer

2. Growth of the epitaxial layer

3. p+ isolation diffusion

4. Base p-type diffusion

5. Emitter n+ diffusion

6. p+ ohmic contact
p-base
7. Contact etching layer
n+ buried layer
8. Metal deposition and etching

9. Passivation and bond pad opening p-substrate

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 BJT Processing

p+ isolation layer

p+ isolation layer
1. Implantation of the buried n+ layer

2. Growth of the epitaxial layer

3. p+ isolation diffusion

4. Base p-type diffusion

5. Emitter n+ diffusion
n+ layer n+ layer
6. p+ ohmic contact
p-base layer
7. Contact etching
n+ buried layer
8. Metal deposition and etching

9. Passivation and bond pad opening p-substrate

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 BJT Processing

p+ isolation layer

p+ isolation layer
1. Implantation of the buried n+ layer

2. Growth of the epitaxial layer

3. p+ isolation diffusion

4. Base p-type diffusion

5. Emitter n+ diffusion
n+ layer p+ layer n+ layer
6. p+ ohmic contact
p-base layer
7. Contact etching
n+ buried layer
8. Metal deposition and etching

9. Passivation and bond pad opening p-substrate

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 BJT Processing
1. Implantation of the buried n+ layer

2. Growth of the epitaxial layer

3. p+ isolation diffusion p+ isolation layer

4. Base p-type diffusion

5. Emitter n+ diffusion
n+ layer p+ layer n+ layer
6. p+ ohmic contact
p-base layer
7. Contact etching
n+ buried layer
8. Metal deposition and etching

9. Passivation and bond pad opening p-substrate

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 BJT Processing
1. Implantation of the buried n+ layer

2. Growth of the epitaxial layer

3. p+ isolation diffusion p+ isolation layer

4. Base p-type diffusion

5. Emitter n+ diffusion
n+ layer p+ layer n+ layer
6. p+ ohmic contact
p-base layer
7. Contact etching
n+ buried layer
8. Metal deposition and etching

9. Passivation and bond pad opening p-substrate

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 BJT Processing
1. Implantation of the buried n+ layer

2. Growth of the epitaxial layer

3. p+ isolation diffusion p+ isolation layer

4. Base p-type diffusion

5. Emitter n+ diffusion
n+ layer p+ layer n+ layer
6. p+ ohmic contact
p-base layer
7. Contact etching
n+ buried layer
8. Metal deposition and etching

9. Passivation and bond pad opening p-substrate

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 Lateral view of npn BJT

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 Lateral PNP BJT

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 Doping Profiles in a BJT

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BICMOS STRUCTURE

NMOS PMOS NPN-BJT

S G D S G D C B E

N- N- P-Diff P-Diff N-Plus

Diff Diff
Emitter

N-Well (Collector)
P-
EPITAXY N Plus Buried Layer
P-SUBSTRATE
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P-SUBSTRATE IS TAKEN

P-SUBSTRATE

P-TYPE SUBSTRATE IS COVERED WITH OXIDE LAYER

P-SUBSTRATE

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A WINDOW IS OPENED THROUGH OXIDE LAYER

P-SUBSTRATE

THROUGH THE WINDOW N TYPE IMPURITIES IS HEAVILY DOPED

N Plus Buried Layer

P-SUBSTRATE

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P-EPITAXY LAYER IS GROWN ON THE ENTIRE SURFACE

P-
EPITAXY
N Plus Buried Layer
P-SUBSTRATE
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THE ENTIRE SURFACE IS COVERED WITH OXIDE LAYER AND TWO WINDOWS
ARE OPENED THROUGH THE OXIDE LAYER

P-
EPITAXY
N Plus Buried Layer
P-SUBSTRATE
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THROUGH THE TWO WINDOWS N-TYPE IMPURITIES ARE DIFFUSED TO
FORM N-WELLS

N-Well
N-Well (Collector)
P-
EPITAXY
N Plus Buried Layer
P-SUBSTRATE
6/3/2015 101
THREE WINDOWS ARE OPENED THROUGH THE OXIDE LAYER , IN THESE
THREE WINDOWS THREE ACTIVE DEVICES NMOS,PMOS AND NPN BJT
ARE FORMED

N-Well
N-Well (Collector)
P-
EPITAXY
N Plus Buried Layer
P-SUBSTRATE
6/3/2015 102
THE ENTIRE SURFACE IS COVERED WITH THINOX AND POLYSILICON
AND ARE PATTERNED TO FORM THE GATE TERMINALS OF THE NMOS
AND PMOS

N-Well
N-Well (Collector)
P-
EPITAXY
N Plus Buried Layer
P-SUBSTRATE
6/3/2015 103
THROUGH THE 3RD WINDOW THE P-IMPURITIES ARE MODERATELY
DOPED TO FORM THE BASE TERMINAL OF BJT
N-WELL ACTS LIKE THE COLLECTOR TERMINAL

N-Well P-Base
N-Well (Collector)
P-
EPITAXY
N Plus Buried Layer
P-SUBSTRATE
6/3/2015 104
THE N-TYPE IMPURITES ARE HEAVILY DOPED TO FORM

1. SOURCE AND DRAIN REGION OF NMOS

2. EMITTER TERMINAL OF BJT
3. AND INTO NWELL COLLECTOR REGION FOR CONTACT PURPOSE

N- N- N-Plus
Diff Diff
Emitter
N-Well P-Base
N-Well (Collector)
P-
EPITAXY
N Plus Buried Layer
P-SUBSTRATE
6/3/2015 105
THE P-TYPE IMPURITES ARE HEAVILY DOPED TO FORM

1. SOURCE AND DRAIN REGION OF PMOS

2. AND INTO P-BASE REGION FOR CONTACT PURPOSE

N- N- P-Diff P-Diff N-Plus

Diff Diff
Emitter
N-Well P-Base
N-Well (Collector)
P-
EPITAXY
N Plus Buried Layer
P-SUBSTRATE
6/3/2015 106
THE ENTIRE SURFACE IS COVERED WITH THICK OXIDE LAYER

N- N- P-Diff P-Diff N-Plus

Diff Diff
Emitter
N-Well P-Base
N-Well (Collector)
P-
EPITAXY
N Plus Buried Layer
P-SUBSTRATE
6/3/2015 107
THE ENTIRE SURFACE IS COVERED WITH THICK OXIDE LAYER AND IS
PATTERNED FOR CONTACT CUTS

N- N- P-Diff P-Diff N-Plus

Diff Diff
Emitter
N-Well P-Base
N-Well (Collector)
P-
EPITAXY
N Plus Buried Layer
P-SUBSTRATE
6/3/2015 108
METAL CONTACTS ARE FORMED

NMOS PMOS NPN-BJT

S G D S G D C B E

N- N- P-Diff P-Diff N-Plus

Diff Diff
Emitter

N-Well (Collector)
P-
EPITAXY
N Plus Buried Layer
P-SUBSTRATE
6/3/2015 109
 Resistors & Capacitors
fabrication

6/3/2015 110
 Ohm's Law
V  IR
• Current I in terms of Jn I  JA 
• Voltage V in terms of electric field JtW
I  JA  JtW  
tW E

EV/L
t
I  JA  JtW V
WL


– Result for R L 1 L
R R
W t  t
W
6/3/2015  111
 Sheet Resistance (Rs)
• IC resistors have a specified thickness – not
under the control of the circuit designer
• Eliminate t by absorbing it into a new
parameter: the sheet resistance
(Rs)
R
 L   L 
 R
 L 
Wt sq 
 t  W  W 
"Number of “quares"

6/3/2015 112
 ELECTRON AND HOLE MOBILITY
Carrier Mobilities versus Doping Concentration

1.60E+03

1.40E+03
Carrier Mobility (cm2/V-sec)

1.20E+03

1.00E+03
mu_n
8.00E+02

6.00E+02 mu_p

4.00E+02

2.00E+02

0.00E+00
1.0
0E
+1
4
1.0
6/3/2015
0E 113
 DIFFUSED RESISTOR
Aluminum contacts

Silicon dioxide

n-wafer Diffused p-type region

The n-type wafer is always biased positive with respect to the p-type
diffused region. This ensures that the pn junction that is formed is
in reverse bias, and there is no current leaking to the substrate.
Current will flow through the diffused resistor from one contact to
the other. The I-V characteristic follows Ohm’s Law: I = V/R

6/3/2015 114
 Layout/Mask Layer 1 - Diffusion
(green)
Top View
W

Resistor
L termination

Side View
P type Diffusion
N wafer
The resistance, R = rhos (L/W)
The sheet resistance rhos, is the resistance of each square If rhos is 100 ohms per
L/W is the number of ‘squares’ long the resistor is said to square,
be. R = 500 ohms
5 squares in this case
6/3/2015 115
 IC Fabrication: Ion Implantation
oxide

• Si substrate (p-type)
• Grow oxide (thermally)
• Add photoresist P-type Si Substrate

• Expose (visible or UV source)

N-type diffusion region
• Etch (chemical such as HF)
• Ion implantation (inject dopants)
• Diffuse (increase temperature and allow
dopants to diffuse)

6/3/2015 116
 Using Sheet Resistance (Rs)
• Ion-implanted (or "diffused") IC resistor

6/3/2015 117
 Poly Film Resistor
Polysilicon Film (N+ or P+ type) Oxide

• To lower the capacitive parasitics, we should

build the resistor further away from substrate
• We ca n d e p o s it a thin film of "poly" “i
P -typ eS iS ubs tra te

(heavily
doped) material on top of the oxide
• The poly will have a certain resistance (say 10
Ohms/sq)

6/3/2015 118
 Diffused Resistor
-Dope a region of the silicon (n-type or p-type) to an acceptable
NA or ND.
-Then place a contact at each end of the diffusion region.
-The diffusion region will have a given resistivity specified in
"Ohms / “quare"
-Then alter the geometry (L/W ration) to get the desired
resistance - typically these have a sheet resistance between 100
to 200 ohms/sq - to save space
-These are laid out using a serpentine geometry

6/3/2015 119
-The interesting thing about the l/W ratio is that if l=W, then the
shape is a square and R=Rs, this is true no matter how big the
square is.
-In fact, the l/W ratio is actually the number of squares in a given
trace geometry - We typically just count the squares and use:

R= Rs*(no.of.squares)

6/3/2015 120
-Another waP y o t
o lfy a
b s r
i ic la it c e oa r n e
si Rtoe
-Polysilicon has a high resistivity prior to Ion Implantationr i s s
-Use undoped Polysilicon to create a high value resistor
it osutsBefore
oe PrIon Implantation : Rs = 10M Ohms/Square
olysilicon.
After Ion Implantation : Rs = 20 to 40 Ohms/Square
-Typically don't even need 1 square to get our resistively so we
don't need to do a serpentine layout
-One drawback is that the resistance can vary widely with
process when using less than 1 square to get a resistor in the k-
Ohms range.
- These are typically used when we just want a BIG resistor and
don't care about the exact value

6/3/2015 121
 Metal Resistor
-Metal can also be used for very small resistors

-The M1 layer typically has sheet resistance on the order of

mohms/sq.

- Use a serpentine layout to get a small resistor (1-10 ohms)

6/3/2015 122
 Cross sections of resistors of various types available from a typical n-well CMOS process.

-n-well process is used for medium value of resistors, while the n+

and p+ diffusions are useful for low value resistors.

-The resistance value depends on the length and width of the

diffused regions, the tolerance of the resistor value is very poor
(i.e., 20 to 50 %)

6/3/2015 123
 Capacitors
• Composed of two conductive plates separated
by an insulator (or dielectric).
– Commonly illustrated as two parallel metal plates
separated by a distance, d.

– C = e A/d
– where e = er eo
– er is the relative dielectric constant
– eo is the vacuum permittivity

6/3/2015 124
 CMOS Capacitors
-There are 3 common ways to make a capacitor
1) MOS Capacitor:
-simply create a MOS structure where the Gate (Metal) terminal
is one terminal and the Body (Semiconductor) terminal is
Ground
- while this is easy to implement, the capacitance changes with
the bias voltage (i.e., VG) due to the depletion and inversion
which occurs

6/3/2015 125
 MIM Capacitor
-"Metal Insulator Metal"-this is simply a parallel plate capacitor
using two metals and an insulator
-This type of capacitor is created using an extra process step that
puts in an additional metal layer that can be very close to one of
the other metal layers to get a smaller plate-to-plate separation
-Since the plates are made of metal, the capacitance doesn't
change with bias voltage-these capacitors are not as large as MOS
capacitors

6/3/2015 126
 Interpoly and MOS capacitors in an n-well CMOS process.

6/3/2015 127
6/3/2015 128
 UNIT 2
BASIC ELECTRICAL PROPERTIES
Topics
• Basic electrical properties of MOS and BiCMOS
circuits:
• Ids-Vds relationships
• MOS transistor threshold voltage, gm, gds
• figure of merit wo
• pass transistor
• NMOS inverter
• Various pull-ups
• CMOS inverter analysis and design
• BiCMOS inverters
6/3/2015 129
 MOSFET I-V Characteristics
I-V Plots, Channel Length Modulation
-4
x 10
– Saturation 6

equation yields 5 VGS= 2.5 V

curves 4
Resistive Saturation

independent of VGS= 2.0 V

ID (A)
3 Quadratic
VDS. Not sure! So VD S = VG S - VT Relationship
we consider the 2 VGS= 1.5 V
effect of channel 1
VGS= 1.0 V
length 0

modulation.
0 0.5 1 1.5 2
VDS(V) 2.5

6/3/2015 130
 MOSFET I-V Characteristics
Channel Length Modulation
• Channel Length
Modulation
– With pinch-off the VS=0
VDS>VDSAT
channel at the point VGS>VT0  n C ox W  2
 2 L (V GS V T 0)
y such that ID
( SAT )

Vc(y)=VGS - VT0, Oxide

0 y
The effective L’ ΔL
Source L Drain (p+)
channel length is (p+) n+ n+
equal to L' = L – ΔL Channel Pinch-off point (QI=0)
– ΔL is the Depletion region
length of channel Substrate (p-Si)
segment over VB=0
which QI=0.
– Place L' in the
ID(SAT) equation:
6/3/2015 131
 MOSFET I-V Characteristics
Channel Length Modulation
– ΔL increases with an increase in VDS.
We can use

1 1 1 1 1 1 1 1  1 1  VDS
  L ΔL  L
– λ: channel length L' L  ΔL L L LΔL
1
L L 1  V
DS

modulation coefficient
– ID(SAT) can be rewritten as

– The above form produces a

discontinuity of current at VDS=VGS-
VT0. We can include the term in ID(lin)
with little error since λ is typically less
than 0.1. We will usually ignore λ in
manual calculations.  n C ox W GS
ID  2 L (V 0  V
T )2 (1  VDS
( SAT ) )

6/3/2015 132
 MOSFET I-V Characteristics
Substrate Bias Effect
– So far, VSB=0 and thus VT0 used in the equations.
– Clearly not always true – must consider body effect
– Two MOSFETs in series:
M1 D

G
S

M2 D
VSB
G
S
–
–
– V“B(M1) = VD“(M2) ≠ O. Thus, VTO in the M1 equation is
replaced
by VT = VT(VSB) as developed in the threshold voltage section.

6/3/2015 133
 MOSFET I-V Characteristics
Substrate Bias Effect (Cont.)
• The general form of ID can be written as
• ID = f (VGS,VDS,VSB)
• which due to the body effect term is
non- linear and more difficult to handle in
manual calculations

6/3/2015 134
 MOSFET I-V Characteristics
Summary of Analytical Equations
– The voltage directions and relationships for the three
modes of pMOS are in contrast to those of nMOS.
D nMOS
G B Mode ID Voltage Range
IDVSB VDS
Cut-off 0 VGS<VT
VGS
S
Linear (µnCox/2)(W/L)[2(VGS- VGSVT ， VDS< VGS
VT)VDS-VDS2] -VT
Saturatio (µnCox/2)(W/L)(VGS- VGS  VT ， VDS 
S
VGS
n VT)2(1+lVDS) VGS -VT
VSB
G
B
VDS pMOS
ID
D
Cut-off 0 VGS>VT
Linear (µnCox/2)(W/L)[2(VGS- VGS  VT ， VDS>
VT)VDS-VDS2] VGS -VT
6/3/2015
Saturatio (µ C /2)(W/L)(V -
Pass-Transistor Logic Circuits (1)
A simple approach for implementing logic functions utilizes series and
parallel combinations of switches that are controlled by input variables to
connect the input and output nodes.

Each of the switches can be implemented either

by a single NMOS transistor or by a pair of CMOS
transistors connected in CMOS transmission gate
iguration
conf Y=AC CMOS transmission gate
.

6/3/2015 136
Pass-Transistor Logic Circuits (2)
An essential requirement in the design of pass-transistor logic is
ensuring that every circuit node has at all times a low-resistance path to
VDD or to ground.
 If B is high, S1 closes and Y=A.
 Y will be VDD if A is high or ground if
A is low.

 If B is low, S1 opens and Y becomes

a high-impedance node.
 If voltage of Y is initially zero, it will
remain so.
 If voltage of Y is initially high at VDD,
then the inevitable leakage current will
discharge the C and can no longer be
considered a static circuit.
A basic design requirement of PTL circuits is that every node have, at all times, a low resistance
path to either ground or VDD. Such a path does not exist in (a) when B is low and S1 is open. It is provided in

6/3/2015 137
(b) through switch S2.
Pass-Transistor Logic Circuits (3)
The problem can be easily solved by establishing for node Y a low-
resistance path that is activated when B goes low.

 Another switch, S2, controlled by B

is connected between Y and ground.
 When B goes low, S2 closes and
establishes

low-resistance

path between Y and ground.

A basic design requirement of PTL circuits is that every node have, at all times, a low resistance
path to either ground or VDD. Such a path does not exist in (a) when B is low and S1 is open. It is provided in

(b) through switch S2.

6/3/2015 138
 MOSFET Ids-Vds

6/3/2015 139
 Terminal Voltages
• Mode of operation depends on Vg, Vd, Vs Vg
+
– Vgs = Vg – Vs +
V gs
Vgd
– Vgd = Vg – Vd - -
– Vds = Vd – Vs = Vgs - Vgd Vs
- +
Vd

• Source and drain are symmetric diffusion terminalsV ds

– By convention, source is terminal at lower voltage

– Hence Vds  0
• nMOS body is grounded.
• Three regions of operation
– Cutoff
– Linear
– Saturation

6/3/2015 140
 nMOS Cutoff
• No channel
• Ids = 0
Vgs = 0 Vgd
+ g +
- -
s d

n+ n+

p-type body
b

6/3/2015 141
 nMOS Linear
• Channel forms
• Current flows from d to Vgs
+ g +
Vgd = Vgs

s– e- from s to d
> Vt
-
s
-
d

n+ n+ Vds = 0

• Ids increases with Vds p-type body

b

• Similar to linear resistor

Vgs > Vt
Vgs > Vgd > Vt
+ g +
- -
s
d Ids
n+ n+
0 < Vds < Vgs-Vt
p-type body
b

6/3/2015 142
 nMOS Saturation
• Channel pinches off
• Ids independent of Vds
• We say current saturates
• Similar to current source
Vgs > Vt
g Vgd < Vt
+ +
- -
s
d Ids
n+ n+
Vds > Vgs-Vt
p-type body
b

6/3/2015 143
 I-V Characteristics
• In Linear region, Ids depends on
– How much charge is in the channel?
– How fast is the charge moving?

6/3/2015 144
 Channel Charge
• MOS structure looks like parallel plate
capacitor while operating in inversion
– Gate – oxide – channel
• Qchannel =
gate
Vg
polysilicon + +
gate Cg
source Vgs Vgd drain
W
Vs - - Vd
channel
tox n+ - + n+
L SiO2 gate oxide Vds
n+ n+ (good insulator,  ox = 3.9)
p-type body p-type body

6/3/2015 145
 Channel Charge
• MOS structure looks like parallel plate
capacitor while operating in inversion
– Gate – oxide – channel
• Qchannel = CV
• C=
gate
Vg
polysilicon + +
gate Cg
source Vgs Vgd drain
W
Vs - - Vd
channel
tox n+ - + n+
L SiO2 gate oxide Vds
n+ n+ (good insulator,  ox = 3.9)
p-type body p-type body

6/3/2015 146
 Channel Charge
• MOS structure looks like parallel plate
capacitor while operating in inversion
– Gate – oxide – channel
• Qchannel = CV Cox = ox / tox

• C = Cg = eoxWL/tox = CoxWL
gate

• V= polysilicon
gate
+
Vg
Cg
+

source Vgs Vgd drain

W
Vs - - Vd
channel
tox n+ - + n+
L SiO2 gate oxide Vds
n+ n+ (good insulator,  ox = 3.9)
p-type body p-type body

6/3/2015 147
 Channel Charge
• MOS structure looks like parallel plate
capacitor while operating in inversion
– Gate – oxide – channel
• Qchannel = CV
• C = Cg = eoxWL/tox = CoxWL Cox = ox / tox

• V = Vgc – Vt = (Vgs – Vds/2) – Vt

gate
Vg
polysilicon + +
gate Cg
source Vgs Vgd drain
W
Vs - - Vd
channel
tox n+ - + n+
L SiO2 gate oxide Vds
n+ n+ (good insulator,  ox = 3.9)
p-type body p-type body

6/3/2015 148
 Carrier velocity
• Charge is carried by e-
• Carrier velocity v proportional to lateral E-field
between source and drain

6/3/2015 149
 Carrier velocity
• Charge is carried by e-
• Carrier velocity v proportional to lateral E-field
between source and drain
• v = mE m called mobility
• E =energy

6/3/2015 150
 Carrier velocity
• Charge is carried by e-
• Carrier velocity v proportional to lateral E-field
between source and drain
• v = mE m called mobility
• E = Vds/L
• Time for carrier to cross channel:
–t=

6/3/2015 151
 Carrier velocity
• Charge is carried by e-
• Carrier velocity v proportional to lateral E-field
between source and drain
• v = mE m called mobility
• E = Vds/L
• Time for carrier to cross channel:
–t=L/v

6/3/2015 152
 nMOS Linear I-V
• Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross

I ds

6/3/2015 153
 nMOS Linear I-V
• Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
I ds  Qchannel
t


6/3/2015 154
 nMOS Linear I-V
• Now we know
– How much charge Qchannel is in the channel
– HoQchannel
w much time t each carrier takes to
I ds
cross t
 W  Vgs t  Vds 
ox
L  V ds
C 2
W
 V  V =
  V V 
gs t ds

 V ds ox
2 C
L
6/3/2015 155
 nMOS Saturation I-V
• If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
• Now drain voltage no longer increases current


I ds

6/3/2015 156
 nMOS Saturation I-V
• If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
• Now drain voltage no longer increases current

I ds   gs V t Vdsat  dsat
 2
V
V

6/3/2015 157
 nMOS Saturation I-V
• If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
• Now drain voltage no longer increases current
I ds   gs V t Vdsat  dsat
 
V 2
t
2
V
 gs
 2 V V

6/3/2015 158
 nMOS I-V Summary
• Shockley 1st order transistor models


 0 cutoff
 Vgs  Vt

I ds   Vds  linear

gs V t Vds ds dsat
 2 V
V 

2
 V saturation
 2 V
gs
Vt  Vds  Vdsat


6/3/2015 159
 Example
• Example: a 0.6 mm process from AMI
semiconductor
2.5
– tox = 100 Å Vgs = 5

2
– m = 350 1.5 Vgs = 4
cm2/V*s

Ids (mA)
1
– Vt = 0.7 V 0.5
Vgs = 3

Vgs = 2
• Plot Ids vs. Vds 0
0 1 2
Vgs = 1
3 4 5
– Vgs = 0, 1, 2, 3, 4, 5 Vds

– Use W/L = 4/2 l 14

W
 ox
W   3.9   W    2

100  L  120
6/3/2015 C   108
10
8.85350   A /V
L
160
L
 MOS Transistor Basics
Two Terminal Structure
• Two terminal structure (p-substrate): The MOS
capacitor VG

A D I

VB

• Important derived parameters. With VG = VB = 0:

– F – Buck Fermi Potential (Substrate)
– S – Surface Potential (Substrate)
6/3/2015 161
 MOS Transistor Basics
Two Terminal Structure (Continued)
– VSB – Flat Band Voltage (applied
external voltage to G-B to flatten bands
of substrate – equal to built-in potential
difference of MOS – equal to work
function difference GB between the
substrate (channel) and gate.
• Operation
– With VG<0, VB=0, Accumulation – Holes
accumulate at substrate-oxide interface
due to attraction of negative bias
– With VG>0, but small, VB=0,
Depletion – Holes repelled from 2 S i  S   F
substrate-oxide interface due to x d

qNA
positive bias leaving negatively charged
fixed acceptors ions behind. The result
is a region below the interface that is
depleted of mobile carriers.
• Depletion region thickness

6/3/2015 162
 MOS Transistor Basics
Two Terminal Structure (Continued)
• Depletion region charge density

– Note that this density is per unit of area.  2 S i 2 F

– With VG>0 and larger, VB=0, Inversion – x dm
qNA
A n-type inversion layer forms, a
condition known as surface inversion.
The surface is inverted when the
density of electrons at the surface
equals the density of holes in the bulk.
This implies that s has the same
magnitude but opposite sign to F. At
the point depletion depth fixed and the
maximum depletion region depth is at
s = -F. This depth is:
Q  q N A x d   2q N A  S  s   F
i

6/3/2015 163
 MOS Transistor Basics
Two Terminal Structure (Continued)
– The corresponding
depletion charge density
(per unit area) at
surface inversion is

– The inversion phenomena

is the mechanism that
forms the n-channel. The
depletion depth and the
depletion region charge Q0  q N A x d  
2q N A  S i  2  F

are critical in determining

properties of MOSFET.

6/3/2015 164
 MOS Transistor Basics
Four Terminal Structure
• p-Substrate
• The MOS n-channel
S(ource) G(ate)
D(rain)
transistor structure:

n+ L n+

B(Body, Bulk or Substrate)

6/3/2015 165
 MOS Transistor Basics
Four Terminal Structure (Continued)
• Symbols: n-channel - p-substrate; p-
channel – n-substrate
D D D D S

B
G G G G G

• S S D
N-channel (fSbubbles)
arrow or add or P-channel,
• reversSe
P-
channel
• Enhancement mode: no conducting
channel exists at VGS = 0
• Depletion mode: a conducting
channel exists at VGS = 0

6/3/2015 166
 MOS Transistor Basics
Four Terminal Structure (Continued)
• Source and drain identification
D
VDS

B
G
VSB

VGS S

6/3/2015 167
 Threshold Voltage Components
• Consider the prior 3-D drawing: Set VS=0, VDS=0,
and VSB=0.
– Increase VGS until the channel is inverted. Then a
conducting channel is formed and the depletion
region thickness (depth) is maximum as is the surface
potential.
– The value of VGS needed to cause surface inversion
(channel creation) is the threshold voltage VT0. The 0
refers to VSB=0.
– VGS< VT0: no channel implies no current flow possible.
With VGS> VT0, existence the channel implies possible
current flow.

6/3/2015 168
Threshold Voltage Components (Cont.)
• GC work function difference between gate and
channel material which is the built-in voltage that
must be offset by voltage applied to flatten the
bands at the surface.
• Apply voltage to achieve surface inversion -2F
• Additional voltage must be applied to offset the
depletion region charge due to the acceptor ions. At Q
2q N A  S i  2 F  V SB
inversion, this charge with VSB=0 is QB0= Q0.
• For VSB non-zero,

• The voltage required to offset the

depletion region charge is defined by –QB/Cox
where Cox = εox/tox with tox, the oxide thickness,
and Cox, the gate oxide capacitance per unit area.

• 4) The final component is a fixed positive

charge density that appears at the interface
between the oxide and the substrate, Qox. The
voltage to offset this charge is:

Q
ox

C ox
6/3/2015 169
Threshold Voltage Components (Cont.)
• These components together give:
V T  GC  2F  QB  Qox
• For VSB=0, VT0 has QB replaced by QB0. This
Cox ox
gives a relationship between VT and VT0
which is:
C V  T
 Q Q
T
C
B B0

V 0 ox

• Thus the actual threshold voltage VT differs

from VT0 by the term given. Going back to
the definition of QB, this term is equal to:

• In which γ is the substrate-bias (or body

effect) coefficient.
   2F V
SB  F 
2

6/3/2015 170
 Threshold Voltage Components (Cont.)
• The final expression for VT0 and VT
are  2q N A  S i

 C ox

• and V T  GC  2F Q Q B0 ox

0 Cox ox
C
– The threshold voltage depends on
the source-to-bulk voltage which is
clearly separated out. The
component is referred to as body
effect. If the source to body voltage
VSB is non-zero, the corrective term
must be applied to VT0.  
 2 F VSB  2F 
VT
0

VT

6/3/2015 171
Threshold Voltage Components (Cont.)
•
• Those parameters in the VT
equation are signed. The following
table gives their signs for nMOS and
pMOS transistor.
Parameter nMOS pMOS
F  
QB, QB0  
γ  
 
• For real designs, the threshold VSB
voltage, due to variation in oxide
thickness, impurity concentrations,
etc., VT0 and γ should be measured
from the actual process.

6/3/2015 172
 •Inverter : basic requirement for
producing a complete range of
Logic circuits

1 0 Vo

0 1

Vss

6/3/2015 173
 Vdd
Basic Inverter: Transistor with source
connected to ground and a load resistor
connected from the drain to the positive
Pull-Up Supply rail
R

Vo Output is taken from the drain and control

input connected between gate and ground

Resistors are not easily formed in silicon

Vin - they occupy too much area
Pull Down

Transistors can be used as the pull-up device

Vss

6/3/2015 174
 NMOS Depletion Mode Transistor Pull - Up
Vdd
• Pull-Up is always on – Vgs = 0; depletion
D
• Pull-Down turns on when Vin > Vt

• With no current drawn from outputs, Ids

for both transistors is equal
Vo S

V0 Vt
Vdd D
Vin

S
Non-zero output
Vss

Vi
6/3/2015 175
 Ids
Vgs=0.2VDD
Ids
Vgs=0

Vgs=-0.2

VDD Vgs=-0.4

VDD Vgs=-
Vds VDD –Vds
0.6V DD
Vin

Vgs=VDD
VDD
Ids Vgs=0.8VDD

Vgs=0.6 VDD

Vgs=0.4 VDD
Vgs=0.2VDD

Vds Vo
VDD VDD

6/3/2015 176
 Decreasing
Vin Zpu/Zpd

VDD
Increasing
Zpu/Zpd

Vo
VDD
Vinv

• Point where Vo = Vin is called Vinv

• Transfer Characteristics and Vinv can be shifted by altering ratio

of pull-up to Pull down impedances

6/3/2015 177
 NMOS Depletion Mode Inverter
Characteristics
• Dissipation is high since rail to rail current
flows when Vin = Logical 1
• Switching of Output from 1 to 0 begins when
Vin exceeds Vt of pull down device
• When switching the output from 1 to 0, the
pull up device is non-saturated initially and
this presents a lower resistance through which
to charge capacitors (Vds < Vgs – Vt)

6/3/2015 178
 NMOS Enhancement Mode Transistor Pull - Up

• Dissipation is high since current flows when Vin = 1 Vdd

D
• Vout can never reach Vdd (effect of channel)

• Vgg can be derived from a switching source (i.e. one phase

of a clock, so that dissipation can be significantly reduced Vgg
• If Vgg is higher than Vdd, and extra supply rail is required Vo S

V0
Vdd D
Vt (pull up) Vin

S
Non zero output
Vss

Vt (pull down) Vin

6/3/2015 179
 Cascading NMOS Inverters

When cascading logic devices care must be taken

to preserve integrity of logic levels

i.e. design circuit so that Vin = Vout = Vinv

Determine pull – up to pull-down ratio for driven inverter

6/3/2015 180
 Assume equal margins around inverter; Vinv = 0.5 Vdd
Assume both transistors in saturation, therefore: Ids = K (W/L) (Vgs – Vt)2/2

Depletion mode transistor has gate connected to source, i.e. Vgs = 0

Ids = K (Wpu/Lpu) (-Vtd)2/2

Enhancement mode device Vgs = Vinv, therefore
Ids = K (Wpd/Lpd) (Vinv – Vt)2/2
Assume currents are equal through both
channels (no current drawn by load)

(Wpd/Lpd) (Vinv – Vt)2 = (Wpu/Lpu) (-Vtd)2

Convention Z = L/W

Vinv = Vt – Vtd / (Zpu/Zpd)1/2

Substitute in typical values Vt = 0.2
Vdd ; Vtd = -0.6 Vdd ; Vinv = 0.5 Vdd
6/3/2015 181
This gives Zpu / Zpd = 4:1 for an nmos
 Pull-Up to Pull-Down Ratio for an nMOS inverter driven
through 1 or more pass transistors

Inverter 1 Vdd Vdd Inverter 2

A B C

Vin1 Vout2

It is often the case that two inverters are connected via a series of switches (Pass Transistors)
We are concerned that connection of transistors in series will degrade the logic levels into
Inverter 2. The driven inverter can be designed to deal with this. (Zpu/Zpd >= 8/1)

6/3/2015 182
 Complimentary Transistor Pull – Up (CMOS)

Vdd

Vout Vtn Vtp

P on N on
Vin Vo
N off P off
Both On

Vin
Vss Vdd
Vss
Logic 0 Logic 1
6/3/2015 183
Vout Vtn Vtp

1: Logic 0 : p on ; n off
P on N on
N off P 5: Logic 1: p off ; n on

Both On off
2: Vin > Vtn.
Vdsn large – n in saturation
Vdsp small – p in resistive
Small current from Vdd to Vss
Vin
4: same as 2 except reversed p and n
Vss Vdd
3: Both transistors are in saturation
Large instantaneous current flows
1 2 3 4 5

6/3/2015 184
CMOS INVERTER CHARACTERISTICS

Current through n-channel pull-down transistor n

n VDD  Vtp  Vtn
In Vin  V tn 2 Vin p
 2 n
 1
Current through p-channel pull-up transistor  p

p
If n = p and Vtp = –Vtn
Ip 2

 Vin VDD  

At logicVthreshold, In = Ip 2
tp
Vin  VDD
2

n p
2 in
V 
Vtn
2

2
 Vin  VDD  Vtp 
 pW p  W
 n n
 
 2 Lp Ln
n
Vin  Vtn 
2  2
p
 Vin  V DD   tpV
Mobilities are unequal : µn = 2.5 µp
n 
   Vin  VDD 
 p Vin  Vtn Z = L/W
Vtp
  n  n
Vin 1   Vtn  VDD  Vtp
  p  p Zpu /Z = 2.5:1 for a symmetrical CMOS inverter
pd
6/3/2015 185
 CMOS Inverter Characteristics
• No current flow for either logical 1 or logical 0
inputs
• Full logical 1 and 0 levels are presented at the
output
• For devices of similar dimensions the p –
channel is slower than the n – channel device

6/3/2015 186
 CMOS Inverter VTC
NMOS off
PMOS res
N
M
O
S
2.
s NMOS sat
(V)

52
a PMOS sat
1.
Vout

t
5
1 P
0. M
5 O NMOS res
PMOS sat NMOS res
0 0 S
0. 1 1.5 2
5 P2M.5OS
r off
e
s
Vin (V)

6/3/2015 187
 Cutoff Linear Saturation
pMOS Vin -VDD= VGS> VT Vin -VDD=VGS< VT Vin -VDD=VGS> VT

Vin -Vout=VGD< VT Vin -Vout=VGD>VT

nMOS Vin = VGS< VT Vin =VGS> VT Vin =VGS> VT

Vin -Vout =VGD> VT Vin -Vout =VGD< VT

VDD

G S
Regions of operations D
For nMOS and pMOS
In CMOS inverter Vin D Vout

G
CL
S

6/3/2015 188
 Impact of Process Variation

Good PMOS
(V)

2. Bad NMOS
Vout

5
2 Nominal
1.
1Bad PMOS
5
0.5Good NMOS
0
0 1 1. 2 2.
0.5 5 5
Vin (V)

Pprocess variations (mostly) cause a shift in the switching

threshold
6/3/2015 189
 Cmos Inverter
• Look at why our NMOS and PMOS inverters
might not be the best inverter designs
• Introduce the CMOS inverter
• Analyze how the CMOS inverter works

6/3/2015 190
 NMOS Inverter
5V
• When VIN change When s V to logic
is logic
IN 1, 0, itsransistor gets
OUT
5V
V
logic 0.
cutoff.
R ID goesConstant
to 0. nonzero current R
• ‘esistor voltaglfeowgs ohrteousghtoartznsesirot o.r.VOUT
D V Power is used even though
"pulled
up" to 5 V.
ID = 5/R OUT
no new computation is being D I =0 D V OUT

VIN 0V performed.
+ VIN 5V
+
5V
VDS 0V VDS
_
_

6/3/2015 191
 PMOS Inverter
• When V5INV changes to logic 1, transistor
cutoff.
gets5 V ID goes to 0.
V• ‘ esisto r voltage goes to zero.VOUV T
IN
- I
-
N

down"Vt o
"pulled D S
OUT
VDS
0V + When V is logic 0, V is + VOUT
OV 5 V
IN OUT
logic 1.
I = -5/R 5V
V.
D
Constant nonzero current
flows through transistor.
I =0 D 0V

R Power is used even though R

no new computation is being
performed.

6/3/2015 192
 Analysis of CMOS Inverter
• We can foVlo w(otghci e1) same procedure to solve
DD L
currents aSnd voltages in the CMOS inverter
for
as we did for the single NMOS and PMOS
circuits. D V OUT

• Remember, D
now we have two transistors so
VIN we write two I-V relationships and have twice
the number of variables.
• We can r oSughly analyze the CMOS
inverter
NMOS si g“rpaulp-ldhowc
i nadlelvyci .e”
6/3/2015 193
PMOS is “pull-up device”
 Linear KVL and KCL Equations
VDD (Logic 1) VGS(n) = VIN
S
VGS(p) = VIN – VDD

VGS(p) = VDS(n) - VDD

D
VOUT
ID(p) = -ID(n)
D +
VIN
VDS(n) = VOUT
VDS(n)
_ VDS(p) = VOUT – VDD
S
VDS(p) = VDS(n) - VDD

Use these equations

to write both I-V equations in terms of
VDS(n) and ID(n)
6/3/2015 194
 CMOS Analysis
ID(n)
As VIN goes up, VGS(n) gets bigger NMOS I-V curve
and VGS(p) gets less negative.
PMOS I-V curve
(written in terms
of NMOS
variables)

VIN = VGS(n) =
0.9 V

VDS(n)

6/3/2015 VDD 195

 CMOS Analysis
ID(n)
As VIN goes up, VGS(n) gets bigger NMOS I-V curve
and VGS(p) gets less negative.
PMOS I-V curve
(written in terms
of NMOS
variables)

VIN = VGS(n) =
1.5 V

VDS(n)

6/3/2015 VDD 196

 CMOS Analysis
ID(n)
As VIN goes up, VGS(n) gets bigger NMOS I-V curve
and VGS(p) gets less negative.
PMOS I-V curve
(written in terms
of NMOS
variables)

VIN = VGS(n) =
2.0 V

VDS(n)

6/3/2015 VDD 197

 CMOS Analysis
ID(n)
As VIN goes up, VGS(n) gets bigger NMOS I-V curve
and VGS(p) gets less negative.
PMOS I-V curve
(written in terms
of NMOS
variables)

VIN = VGS(n) =
2.5 V

VDS(n)

6/3/2015 VDD 198

 CMOS Analysis
ID(n)
As VIN goes up, VGS(n) gets bigger NMOS I-V curve
and VGS(p) gets less negative.
PMOS I-V curve
(written in terms
of NMOS
variables)

VIN = VGS(n) =
3.0 V

VDS(n)

6/3/2015 VDD 199

 CMOS Analysis
ID(n)
As VIN goes up, VGS(n) gets bigger NMOS I-V curve
and VGS(p) gets less negative.
PMOS I-V curve
(written in terms
of NMOS
variables)

VIN = VGS(n) =
3.5 V

VDS(n)

6/3/2015 VDD 200

 CMOS Analysis
ID(n)
As VIN goes up, VGS(n) gets bigger NMOS I-V curve
and VGS(p) gets less negative.
PMOS I-V curve
(written in terms
of NMOS
variables)

VIN = VGS(n) =
4.1 V

VDS(n)

6/3/2015 VDD 201

 CMOS Inverter VOUT vs. VIN
VOUT

both curve very

sat. steep here;
VDD
only in “C” for
small interval of
NMOS: VIN
cutoff
NMOS: NMOS:
PMOS:
triode triode
triode
PMOS: PMOS:
NMOS: cutoff
saturation
saturation
PMOS:
triode
VIN
6/3/2015 A B C D E
VDD 202
ID
CMOS Inverter ID

VIN
A B C D E
VDD
6/3/2015 203
 Important Points
• No ID current flow in Regions A and E if
nothing attached to output; current flows only
during logic transition
• If another inverter (or other CMOS logic)
attached toS Vo utput, transistor S
DD

gate
of V
t erminals
attached
D D
stage do not permit current:
current stillDflowVs o nly during logiDc
OU T1

tranV s i t ion
O
D
U T 2
D
VIN

S S
6/3/2015 204
 Impact of Process Variation

Good PMOS
(V)

2. Bad NMOS
Vout

5
2 Nominal
1.
1Bad PMOS
5
0.5Good NMOS
0
0 1 1. 2 2.
0.5 5 5
Vin (V)

Pprocess variations (mostly) cause a shift in the switching

threshold
6/3/2015 205
 Beta Ratio
• If bp / bn  1, switching point will move
from VDD/2
VDD
p


10n
2
Vout
1
0.5
p
 0.1
n

0
VDD
Vin
6/3/2015 206
 Unit III
VLSI CIRCUIT DESIGN PROCESSES
Topics
• VLSI design flow
• MOS layers
• Stick diagrams
• Design Rules and Layout
• 2 um CMOS design rules for wires
• Contacts and Transistors
• Layout diagrams for NMOS and
• CMOS inverters and gates, Scaling of MOS circuits

6/3/2015 207
 VLSI Design of approach of IC

26/038/2
015
 Layer Types
• p-substrate
• n-well
• n+
• p+
• Gate oxide (thin oxide)
• Gate (polycilicon)
• Field Oxide
– Insulated glass
– Provide electrical isolation

6/3/2015 209
 Stick diagram

Encodings for a simple single metal nMOS process

COLOR STICK ENCODING LAYERS MASK LAYOUT ENCODING CIF LAYER

MONOCROME MONOCROME
n-
diffusion
GREEN N
n+active

Thniox D

RED Polysilicon
NP

BLUE Metal 1
N

BLACK Contact cut M

Overglass N
GRAY NOT
APPLICABLE
nMOS
Implant C
ONLY
YELL
N
O Buried
nWMOS G
contact
ONLY NI
BROWN

NB

6/3/2015 210
 Stick Diagrams

Metal

poly

ndif
Can also draw
f in shades of
Buried Contact gray/line style.
pdif
f
Contact Cut

6/3/2015 211
 Stick Diagrams
• VLSI design aims to translate circuit concepts
onto silicon.
• Stick diagrams are a means of capturing
topography and layer information using simple
diagrams.
• Stick diagrams convey layer information through
colour codes (or monochrome encoding).
• Acts as an interface between symbolic circuit and
the actual layout.
6/3/2015 212
 Stick Diagrams

• Does show all components/vias.

• It shows relative placement of
components.
• Goes one step closer to the
layout
• Helps plan the layout and
routing

6/3/2015 213
 Stick Diagrams

• Does not show

– Exact placement of components
– Transistor sizes
– Wire lengths, wire widths, tub
boundaries.
– Any other low level details such as
parasitics..

6/3/2015 214
 Stick Diagrams

Stick Diagrams – Some rules

• Rule 1.
• When two or more 'sticks' of the same
type cross or touch each other that
represents electrical contact.

6/3/2015 215
 Stick Diagrams

Stick Diagrams – Some rules

• Rule 2.
• When two or more 'sticks' of different
type cross or touch each other there is no
electrical contact.
(If electrical contact is needed we have to
show the connection explicitly).

6/3/2015 216
 Stick Diagrams

Stick Diagrams – Some rules

• Rule 3.
• When a poly crosses diffusion it
represents a transistor.

Note: If a contact is shown then it is not a transistor.

6/3/2015 217
 Stick Diagrams

Stick Diagrams – Some rules

• Rule 4.
• In CMOS a demarcation line is drawn to
avoid touching of p-diff with n-diff. All pMOS
must lie on one side of the line and all
nMOS will have to be on the other side.

6/3/2015 218
6/3/2015 219
 NMOS INVERTER
5V 5v

Dep

Vout

Enh Vin

0V

0V

6/3/2015 220
 NMOS-NAND

6/3/2015 221
 NMOS-NOR

6/3/2015 222
 NMOS EX-OR

6/3/2015 223
 NMOS EX-NOR

6/3/2015 224
 PMOS-INVERTER

6/3/2015 225
 PMOS NAND

6/3/2015 226
 PMOS-NOR

6/3/2015 227
 Sticks design CMOS NAND:
• Start with NAND gate:

6/3/2015 228
 NAND sticks

VDD
a

out

VSS
6/3/2015 229
 Stick Diagram - Example A
OUT
B

NOR Gate

6/3/2015 230
 Stick Diagram - Example

Power

A Out

Ground

6/3/2015 231
 2 I/P OR GATE

6/3/2015 232
 2 I/P AND

6/3/2015 233
6/3/2015 234
 Y=(AB+CD)'

6/3/2015 235
 Y=(AB+CD)'
“TICK

6/3/2015 236
6/3/2015 237
 Design Rules
• Design rules are a set of geometrical
specifications that dictate the design of the layout
masks
• A design rule set provides numerical values
– For minimum dimensions
– For minimum line spacings
• Design rules must be followed to insure
functional structures on the fabricated chip
• Design rules change with technological advances
(www.mosis.org)

6/3/2015 238
 Silicon Foundry
• A standard
• A foundry allows designers to submit designs
using a state-of-the-art process
• Each foundry state simpler set of design rules
called lambda design rules
• All widths, spacings, and distances are written in
the form
– Value = m

– TSMC (Thailand Semiconductor Manufacturing
Corporation)
6/3/2015 239
 Design Rules Classification
• Minimum width
• Minimum spacing
• Surround
• Extension

6/3/2015 240
 Physical Limitations
• Line width limitation of an imaging system
– The reticle shadow projected on the photoresist
does not have sharp edges due to optical
diffraction
• Etching process problem
– Undercutting of the resist due to lateral etching
decreases the resolution

6/3/2015 241
 Etching Process Problem

Vertical etching
Lateral

Etching

Substrate Substrate

Isotropic etch

6/3/2015 242
 Depletion Region
• If depletion regions of adjacent pn junctions
touch, then
– The current blocking characteristics are altered
– Current can flow between the two

Spacing

n+ n+
Substrate

6/3/2015 Limits on n+ spacing 243

 Electrical Capacitive Coupling
• This occurs between closely spaced
conducting lines
• This leads to a problem called
crosstalk
– A portion of the electrical energy is coupled to
another causing noise
– This is a major problem in high-density design

6/3/2015 244
 Electrical Rules
• An example of an electrical rule is the allowed
width of a metal interconnect line
– To avoid electromigration effects
– The design rule set will stipulate the maximum
current flow level permitted

6/3/2015 245
 3D Perspective

Polysilic Aluminu
on m

6/3/2015 246
 Design rules and Layout
• Why we use design rules?
– Interface between designer and process engineer
– Guidelines for constructing process masks

6/3/2015 247
 Design Rules
Minimum length or width of a feature on a layer is 2

Why?
To allow for shape contraction
Minimum separation of features on a layer is 2

Why?
To ensure adequate continuity of the intervening
materials.

6/3/2015 248
 Design
Rules
Minimum width of PolySi and diffusion line 2
Minimum width of Metal line 3 as metal lines run over a more uneven
surface than other conducting layers to ensure their continuity

Metal

Diffusion


  Polysilicon

6/3/2015 249
 Design
Rules
PolySi – PolySi space 2
Metal - Metal space 2
Diffusion – Diffusion 3 To avoid the possibility of their associated
regions overlapping and conducting current

Metal

Diffusion

  Polysilicon

6/3/2015 250
 Design
Rules
Diffusion – PolySi  To prevent the lines overlapping to form
unwanted capacitor
Metal lines can pass over both diffusion and polySi without
electrical effect. Where no separation is specified, metal lines
can overlap or cross

Metal

Diffusion

 Polysilicon

6/3/2015 251
 Metal Vs PolySi/Diffusion

• Metal lines can pass over both diffusion and

polySi without electrical effect
• It is recommended practice to leave 
between a metal edge and a polySi or
diffusion line to which it is not electrically
connected
Metal


Polysilicon

6/3/2015 252
 Review
:
 poly-poly spacing 2

 diff-diff spacing 3
(depletion regions tend to spread outward)

 metal-metal spacing 2

 diff-poly spacing 

6/3/2015 253
 Note
• Two Features on different mask layers can be
misaligned by a maximum of 2l on the wafer.
• If the overlap of these two different mask
layers can be catastrophic to the design, they
must be separated by at least 2l
• If the overlap is just undesirable, they must
be separated by at least l

6/3/2015 254
 When a transistor is formed?

Gate is formed where polySi crosses diffusion with

thin oxide between these layers.

Design rules
min. line width of polySi and diffusion 2
drain and source have min. length and width of 2
And

6/3/2015 255
 PolySi extends in the gate region…

The polySi of the gate extends 2 beyond the gate area on

to the field oxide to prevent the drain and source from shorting.

diffusion
short

• Diffusion Problems

no overlap overlap

6/3/2015 256
 Depletion Transistor
We need depletion implant

An implant surrounding the Transistor by 2

Ensures that no part of the transistor remains

in the enhancement mode

A separation of 2 from the gate of an

enhancement transistor avoids affecting 2

the device.

6/3/2015 257
 Depletion Transistor

Implants are separated by 2 to prevent them from merging

2

6/3/2015 258
 Butting Contact

The gate and source of a depletion device can be

connected by a method known as butting contact. Here
metal makes contact to both the diffusion forming the
source of the depletion transistor and to the polySi
forming this device’s gate.

Advantage:
No buried contact mask required and
avoids associated processing.

6/3/2015 259
 Butting Contact
Problem: Metal descending the hole has a tendency to
fracture at the polySi corner, causing an open circuit.
Metal

Insulating
Oxide
n+ n+

Gate Oxide PolySi

6/3/2015 260
 Buried Contact

It is a preferred method. The buried contact window

defines the area where oxide is to be removed so
that polySi connects directly to diffusion.
Contact Area must be a min. of 2*2 to ensure
adequate contact area.

2
Contact Area

6/3/2015
2 261
 Buried Contact
The buried contact window surrounds this contact by  in all
directions to avoid any part of this area forming a transistor.

Separated from its related transistor gate by  to prevent gate

area from being reduced.

6/3/2015 262
 Buried Contact
Here gate length is depend upon the alignment of the
buried contact mask relative to the polySi and
therefore vary by .

PolySi
Channel length 
 2


Buried contact

2
Diffusion
6/3/2015 263
 Contact Cut
Metal connects to polySi/diffusion by contact cut.
Contact area: 22
Metal and polySi or diffusion must overlap this contact area
by  so that the two desired conductors encompass the contact
area despite any mis-alignment between conducting layers
and the contact hole

4

6/3/2015 264
 Contact Cut
Contact cut – any gate: 2 apart
Why? No contact to any part of the gate.

4

2

6/3/2015 265
 Contact Cut

Contact cut – contact cut: 2 apart

Why? To prevent holes from merging.

2

6/3/2015 266
 Rules for CMOS layout
Similar to those for NMOS except No
1. Depletion implant
2. Buried contact

Additional rules
1. Definition of n-well area
2. Threshold implant of two types of transistor
3. Definition of source and drains regions for the
NMOS and PMOS.

6/3/2015 267
 Rules for CMOS layout

To ensure the separation of the PMOS and NMOS devices,

n-well supporting PMOS is 6 away from the
active
area of NMOS transistor.
Why?
Avoids overlap n+ n-well
6
of the associated
regions

6/3/2015 268
 Rules for CMOS layout

2

N-well must completely

surround the PMOS 2
device’s active area by 2

6/3/2015 269
 Rules for CMOS layout

2

The threshold implant

mask covers all n-well
2
and surrounds the n-well
by 

6/3/2015 270
 Rules for CMOS layout
The p+ diffusion mask
defines the areas to
2
receive a p+ diffusion.
It is coincident with the
threshold mask 2
surrounding the PMOS
transistor but excludes
the n-well region to be
connected to the supply.

6/3/2015 271
 Rules for CMOS layout
A p+ diffusion is required to effect the ground connection
to the substrate. Thus mask also defines this substrate
region. It surrounds the conducting material of this
contact by 

4

6/3/2015 272
 Rules for CMOS layout

Total contact area = 24

Neither NMOS nor CMOS usually allow contact

cuts to the gate of a transistor, because of the danger
of etching away part of the gate

6/3/2015 273
 GATE LEVEL DESIGN

Topics
• Logic gates and other complex gates
• Switch logic
• Alternate gate circuits
• Time delays
• Driving large capacitive loads
• Wiring capacitances
• Fan-in and fan-out, Choice of layers

6/3/2015 274
 NMOS Gate construction
•NMOS devices in series implement a NAND function

A•B A B F
A 0 0 1
0 1 1
B
1 0 1
1 1 0

•NMOS devices in parallel implement a NOR function

A B F
A+B 0 0 1
A B
0 1 0

1 0 0

1 1 0
6/3/2015 275
 PMOS Gate construction
•PMOS devices in parallel implement a NAND function

A B F
0 0 1
A B
0 1 1
1 0 1
A•B 1 1 0

•PMOS devices in series implement a NOR function

A B F

0 0 1
B
0 1 0
A
1 0 0

A+B 1 1 0
6/3/2015 276
 Parasitics and Performance
• Consider the
following layout:
a
• What is the impact
on performance
of
parasitics b
c
– At point a (VDD rail)?
– At point b (input)?
– At Point c (output)?

6/3/2015 277
 Parasitics and Performance
• a - power supply
connections
– capacitance - no a
effect on delay
– resistance - increabses
c
delay (see p. 135)
• minimize by reducing
difffusion length
• minimize using
parallel vias
6/3/2015 278
 Parasitics and Performance
• b - gate input
– capacitance
increases delay on a
previous stage (often
transistor gates
b
dominate) c
– resistance increases
delay on previous
stage

6/3/2015 279
 Parasitics and Performance
• c - gate output
– resistance, capacitance
increase delay
– Resistance & capacitance a
"near" to output causes
additional delay
b
c

6/3/2015 280
 Driving Large Loads
• Off-chip loads, long wires, etc. have high capacitance
• Increasing transistor size increases driving ability
(and speed), but in turn increases gate capacitance
• Solution: stages of progressively larger transistors
– Use nopt = ln(Cbig/Cg).
– Scale by a factor of a=e

6/3/2015 281
 Summary: Static CMOS
• Advantages
– High Noise Margins (VOH=VDD, VOL=Gnd)
– No static power consumption (except for leakage)
– Comparable rise and fall times (with proper sizing)
– Robust and easy to use
• Disadvantages
– Large transistor counts (2N transistors for N inputs)
• Larger area
• More parasitic loading (2 transistor gates on each input)
– Pullup issues
• Lower driving capability of P transistors
• Series connections especially problematic
• Sizing helps, but increases loading on gate inputs

6/3/2015 282
 Alternatives to Static CMOS
• Switch Logic
• nmos
• Pseudo-nmos
• Dynamic Logic
• Low-Power Gates

6/3/2015 283
 Switch Logic
• Key idea: use transistors as switches
• Concern: switches are bidirectional

A B

AND

OR

6/3/2015 284
 Switch Logic - Pass Transistors
• Use n-transistor as "switches"
IN: OUT:
• "Threshold problem" VDD-Vtn

– Transistor switches off when Vgs < VVt

DD
A:
– VDD input -> VDD-Vt output VDD

• “pecial gate needed to "restore" values

6/3/2015 285
 Switch Logic - Transmission Gates
• Complementary transistors - n and p
• No threshold problem
• Cost: extra transistor, extra control input
• Not a perfect conductor!
A’
A’

A
A
6/3/2015 286
 Switch Logic Example - 2-1 MUX

IN

6/3/2015 287
 Charge Sharing
• Consider transmission gates in series
– Each node has parasitic capacitances
– Problems occur when inputs change to
redistribute charge
– Solution: design network so there is always a path
from VDD or Gnd to output

6/3/2015 288
 Aside: Transmission Gates in Analog
• Transmission Gates
work with analog values, too!
• Example:
Voltage-Scaling D/A Converter

6/3/2015 289
 NMOS Logic
• Used before CMOS was widely
available
• Uses only n transistors
– Normal n transistors in pull- Passive Pullup Device:
down network depletion Mode
n-transistor (Vt < 0)
– depletion-mode n transistor
(Vt < 0) used for pull-up OUT
Pulldown
– "ratioed logic" required Network
• Tradeoffs:
– Simpler processing
– Smaller gates
– higher power!
– Additional design
considerations
for ratioed logic

6/3/2015 290
 Pseudo-nmos Logic
• Same idea, as nmos, but use p-
transistor for pullup
• "ratioed logic" required for
proper design (more Passive Pullup Device:
about this next) P-Transistor
• Tradeoffs:
OUT
– Fewer transistors -> smaller Pulldown
gates, esp. for large number Network
of inputs
– less capacitative load on
gates
that drive inputs
– larger power consumption
– less noise margin (VOL > 0)
– additional design
considerations due to ratioed
logic
6/3/2015 291
Rationed Logic for Pseudo-nmos
• Approach:
– Assume VOUT=VOL =0.25*VDD
– Assume 1 pulldown transistor is on
OUT
– Equate currents in p, n transistors Pulldown
Idp
Network
– Solve for ratio between sizes of p, n Idn
transistors to get these conditions
– Further necessary
calculations series for
connections
W
1  I pnn
I dn
2 k' n L n V

gs,n
tn  V  2 1
Wp

2 p L p 2V
gs,p tp
V
 Vds,p  Vds,p
2  (EQ 3 
21)
Wp k'
Lp (EQ 3  22)  Assu min g DD 
Wn 
Ln V 3.3V
3.9
6/3/2015 292
 DCVS Logic
• DCVS - Differential
Cascode Voltage Switch
• Differential inputs,
outputs
• Two pulldown
networks OUT OUT’

• Tradeoffs A
OUT OUT’
A’
B’
– Lower capacitative loading B
Pulldown Pulldown
C’
than static CMOS Network Network

– No ratioed logic needed C

– Low static power

consumption
– More transistors
– More signals to
route
6/3/2015
between gates 293
 Dynamic Logic
• Key idea: Two-step operation
– precharge - charge CS to logic high
– evaluate - conditionally discharge CS CS
Storage Node

Precharge
• Control - precharge clock f Signal Pulldown
Storage
Capacitance
Network
B
A
C


Precharge Evaluate Precharge

6/3/2015 294
 Domino Logic
• Key idea: dynamic gate + inverter

• Cascaded gates - "monotonically increasing"
CS

Pulldown
Network
B

 C

in4

x1

x2

x3

6/3/2015 295
 Domino Logic Tradeoffs
• Fewer transistors -> smaller gates
• Lower power consumption than pseudo-nmos
• Clocking required
• Logic not complete (AND, OR, but no NOT)

6/3/2015 296
 More Techniques for Saving Power
• Reduce VDD (tradeoff: delay)
• Multiple Power Supplies
– High VDD for "fast" logic
– Low VDD for "slow" logic
• Dealing with leakage currents
– Multiple-Threshold CMOS (MTCMOS)
– Variable-Threshold CMOS (VTCMOS)

6/3/2015 297
 Unit III

Topics:
SRAM

DRAM
ROM
Serial
Acces
s
Mem
ories
Conte
nt
6/3/2015 Addre 338
 Semiconductor Memory Types

Semiconductor Memories

Read/Write (R/W) Memory

or Random Access Memory Read-Only Memory (ROM)
(RAM)

1. Mask (Fuse) ROM

Dynamic RAM Static RAM 2. Programmable ROM (PROM)
(DRAM) (SRAM) Erasable PROM (EPROM)
Electrically Erasable PROM
(EEPROM)
3. Flash Memory
4. Ferroelectric RAM (FRAM)

339
 Semiconductor Memory Types (Cont.)

 Design Issues
» Area Efficiency of Memory Array:  of stored data bits
per
unit area
» Memory Access Time: the time required to store and/or
retrieve a particular data bit.
» Static and Dynamic Power Consumption

• Requirements
» Easy reading
» Easy Writing
» High density
» Speed, more speed and still more speed
340
 Memory Architecture

 Stores large number of bits m × n memory

• m x n: m words of n bits each …

m words
• k = Log2(m) address input …
signals
• or m = 2k words
• e.g., 4,096 x 8 memory: n bits per word
memory external
» 32,768 bits
r/w
view
» 12 address input signals 2k × n read and write
memory
enabl
 » 8 input/output data signals
Memory access eA 0
…
• r/w: selects read or write A k-

• enable: read or write only when asserted 1 …

• multiport: multiple accesses to different locations simultanQ e n -

1ouslyQ0

341
 Semiconductor Memory Types (Cont.)

 RAM: the stored data is volatile

• DRAM
» A capacitor to store data, and a transistor to access
the capacitor
» Need refresh operation
» Low cost, and high density  it is used for main
memory

• SRAM
» Consists of a latch
» Don’t need the refresh operation
» High speed and low power consumption it is mainly used for
cache memory and memory in hand-held devices
342
 RAM: “Random-access” memory
External view
 Typically volatile memory r/w 2k × n read and write
enable memory
• bits are not held without power
 supply A0
Read and written to easily by micropro… ssor
ce
during execution
Ak-1
…
 Internal structure more complex than ROM Qn-1 Q0

• a word consists of several memory cells, each storing 1 Ibnitternal

I I I I 3 2 1 0

view 4×4 RAM

• each input and output data line connects to each cell in its column
enable
c th 2×4

• rd/wr connected to every cell

input data bit when rd/wr indicates write or ouA
s
At put 0 ed bit
• when indicates
rd/wr
when row is enabled
read by decoder, each cell has logistor at stores
1
decoder
Memory
cell
rd/wr To every cell

Q3 Q2 Q1 Q0

343
 Memory Chip Configuration

Row
M
Address 2 Cells
N bits

Memory Cell Array

Complete Address
N+M Bits

Row Dec
Cell
WL N
2 Cells
I/O Interface

DL

Din

din
I/O Control
Dout dout

Column Dec.
Control
Column Address
Signals
M
Bits

344
 Static Random Access Memory (SRAM)
• SRAM: ThebtisltionereCd data can be retained inbdtieilfnienCitely,
without any need for a periodic refresh operation.

1-bit SRAM cell

VDD

bit line C bit line C

load load

word line word line

• Complementary Column arrangement is to achieve a

more
345 reliable SRAM operation
 4T-SRAM(Resistive-Load SRAM Cell )

undoped polysilicon resistor

VDD

bit line C bit line C

R R

SRAM cell is accessed via

word line word line two bit (column) lines C
and its complement for
reliable operation

pass transistors to
activated by a row select Basic cross-coupled 2-inverter
(RS) signal to enable latch with 2 stable op points
read/write operators for storing one-bit

346
 6T-SRAM
VDD

bit line C bit line C

Full CMOS SRAM

Cell
word line word line

VDD

bit line C bit line C

Depletion-Load
SRAM Cell
word line word line

347
 SRAM Operation Principles
• RS=0: The word line is not selected. M3 and M4 are OFF
• One data-bit is held: The latch preserves one of its two stable states.
• If RS=0 for all rows: CC and CC are charged up to near VDD by pulling up
of MP1 and MP2 (both in saturation)

Pull-up transistor (one per column)

VDD VDD
VDD
MP1 MP2
bit line C R R bit line C
VC M3 V1 V2 M4 VC

CC M1 M2 CC

word line
RS

348
 SRAM Operation Principles (Cont.)
Pull-up transistor (one per column)

VDD VDD
VDD
MP1 MP2
bit line C R R bit line C
VC M3 V1 V2 M4 VC

CC M1 M2 CC

word line
RS

• RS=1: The word line is now selected. M3 and M4 are ON

• Four Operations
• Write “1” Operation (V1=VOL, V2=VOH at t=0-):
• VC  VOL by the data-write circuitry. Therefore, V2  VOL, then M1 tur
off V1VOH and M2 turns on pulling down V2  VOL.

349
 SRAM Operation Principles (Cont.)
Pull-up transistor (one per column)

VDD VDD
VDD
MP1 MP2
bit line C R R bit line C
VC M3 V1 V2 M4 VC

CC M1 M2 CC

word line
RS

• Read “1” Operation (V1=VOH, V2=VOL at t=0-):

• VC retains pre-charge level, while VC  VOL
by M2 ON. Data-read circuitry detects small
voltage difference VC – VC > 0, and amplifies it
as a “1” data output.

350
 SRAM Operation Principles (Cont.)
Pull-up transistor (one per column)

VDD VDD
VDD
MP1 MP2
bit line C R R bit line C
VC M3 V1 V2 M4 VC

CC M1 M2 CC

word line
RS
• Write “0” Operation (V1=VOH, V2=VOL at t=0-):
• VC  VOL by the data-write circuitry.
• Since V1  VOL, M2 turns off, therefore V2  VOH.

351
 SRAM Operation Principles (Cont.)
Pull-up transistor (one per column)

VDD VDD
VDD
MP1 MP2
bit line C R R bit line C
VC M3 V1 V2 M4 VC

CC M1 M2 CC

word line
RS
• Read “0” Operation (V1=VOL, V2=VOH at t=0-):
• VC retains pre-charge level, while VC  VOL by M1 ON.
• Data-read circuitry detects small voltage difference VC – VC < 0,
and
amplifies it as a “0” data output.

352
 SRAM Operation Principles (Cont.)

Pull-up transistor (one per column)

VDD VDD
VDD
MP1 MP2
bit line C R R bit line C
VC M3 V1 V2 M4 VC

CC M1 M2 CC

word line
RS

3. Write “0” Operation (V1=VOH, V2=VOL at t=0-):

VC  VOL by the data-write circuitry.
Since V1  VOL, M2 turns off, therefore V2  VOH.

353
 SRAM Operation Principles (Cont.)

Pull-up transistor (one per column)

VDD VDD
VDD
MP1 MP2
bit line C R R bit line C
VC M3 V1 V2 M4 VC

CC M1 M2 CC

word line
RS

4. Read “0” Operation (V1=VOL, V2=VOH at t=0-):

VC retains pre-charge level, while VC  VOL by M1 ON.
Data-read circuitry detects small voltage difference VC – VC < 0,
and amplifies it as a “0” data output.
354
 Circuit of CMOS SRAM Cell
Pull-up transistor (one per column)
(Column voltages can reach to full VDD)
VDD VDD
VDD
MP1 MP2
bit line C M5 M6 bit line C
VC M3 V1 V2 M4 VC

CC M1 M2 CC

word line
RS
 Advantages
• Very low standby power consumption
• Large noise margins than R-load SRAMS
• Operate at lower supply voltages than R-load SRAMS
 Disadvantages
• Larger die area: To accommodate the n-well for pMOS transistors
and polysilicon contacts. The area has been reduced by using
multi- layer polysilicon and multi-layer metal processes
• CMOS more complex process
355
 Dynamic Read-Write Memory (DRAM) Circuits
• SRAM: 4~6 transistors per bit
4~5 lines connecting as charge on capacitor
• DRAM: Data bit is stored as charge on
capacitor Reduced die area
Require periodic refresh
WL

M1 M2
M3 M4

parasitic storage
BL BL
capacitances
Four-Transistor DRAM Cell

356
 DRAM Circuits (Cont.)

WL(read)

X M2
M1 M3

parasitic storage
WL(write) capacitances
BL(write) BL(read)

Three-Transistor DRAM Cell

No constraints on device ratios
Reads are non-destructive
Value stored at node X when
357 writing a “1” = V WWL-VTn
 3T-DRAM — Layout

BLR BL GND
W

RWL
M3

M2

WWL
M1

Source: Digital Integrated Circuits 2nd

358
 One-Transistor DRAM Cell
WL

M1 explicit
storage
capacitances
BL

One-Transistor DRAM Cell

• Industry standard for high density dram arrays

• Smallest component count and silicon area per bit
• Separate or “explicit” capacitor (dual poly) per
cell

359
 Operation of Three-Transistor DRAM Cell
VDD
Precharge devices
MP1 MP2
PC
RS

M3
M1 M2
C2 C3
C1

WS

Data_in
DAT C2, C3 >> C1(>10C1)
A Data_out
• The binary information is stored as the charge in C1
• Storage transistor M2 is on or off depending on the charge in C1
• Pass transistors M1 and M3: access switches
• Two separate bit lines for “data read” and “data write”
360
 Operation of Three-Transistor DRAM Cell (Cont.)
PC write 1 PC read 1 PC write 0 PC read
VDD ① 2 0
Precharge devices
PC
③ 4 ⑤ 6 ⑦ 8
MP1 MP2
PC WS
RS

M3 DAT
M1
C2
M2
C3
A
Din
C1

WS Stored data

Data_in Data_out RS
DATA
Dout

• The operation is based on a two-phase non-overlapping clock scheme

» The precharge events are driven by 1, and the “read” and “write”
operations are driven by 2.
» Every “read” and “write” operation is preceded by a precharge
cycle, which is initiated with PC going high.

361
 Operation of Three-Transistor DRAM Cell (Cont.)
VDD
Precharge devices
MP1 MP2
PC Pre-charge Cycle
C2 C3
RS

M3
M1 M2
C2 C3
C1

WS
Data_in Data_out
DATA

• Write “1” OP: DATA = 0, WS = 1; RS = 0

» C2, C1 Share charge due to M1 ON
» Since C2 >> C1, the storage node C1 attains approximately the
same logic level.
362
 Operation of Three-Transistor DRAM Cell (Cont.)

RS
M3
M1 M2
C2 C3
C1

WS
Data_in Data_out
DATA

• Read “1” OP: DATA = 0, WS = 0; RS = 1

» M2, M3 ON  C3, C1 discharges through M2 and M3, and the
falling column voltage is interpreted bt the “data read”
circuitry as a stored logic “1”.
363
 Operation of Three-Transistor DRAM Cell (Cont.)

RS

M3
M1 M2
C2 C3
C1

WS
Data_out
Data_in
DAT
A

• Write “0” OP: DATA = 1, WS = 1; RS = 0

» M2, M3 ON  C2 and C1 discharge to 0 through M1 and data_in
nMOS.

364
 Operation of Three-Transistor DRAM Cell (Cont.)

RS
M3
M1 M2
C2 C3
C1

WS
Data_in Data_out
DATA

• Read “0” OP: DATA = 1, WS = 0; RS = 1

» C3 does not discharge due to M2 OFF, and the logic-high level
on the Data_out column is interpreted by the data read
circuitry as a stored “0” bit.
365
 Operation of One-Transistor DRAM Cell
WL

M1
Column C2 C1
capacitance
BL
1-bit DRAM Cell
C2>>C1

• Write “1” OP: BL = 1, WL = 1 (M1 ON)C1 charges to “1”

• Write “0” OP: BL = 0, WL = 1 (M1 ON)C1 discharges to “0”
• Read OP: destroys stored charge on C1  destructive refresh is
needed after every data read operation

366
 RAM

 DRAM SRAM

VDD

WL
WL
WL

DL
DL
DL

367
 Semiconductor Memory Types (Cont.)
 ROM: 1, nonvolatile memories
2, only can access data, cannot to modify data
3, lower cost: used for permanent memory in printers,
fax, and game machines, and ID cards
• Mask ROM: data are written during chip fabrication by a photo
mask
• PROM: data are written electrically after the chip is fabricated.
» Fuse ROM: data cannot be erased and modified.
» EPROM and EEPROM: data can be rewritten, but the number
of subsequent re-write operations is limited to 104-105.
• EPROM uses ultraviolet rays which can penetrate through the
crystal glass on package to erase whole data simultaneously.
• EEPROM uses high electrical voltage to erase data in 8 bit units.
• Flash Memory: similar to EEPROM

368
 ROM: “Read-Only” Memory

 Nonvolatile
 Can be read from but not written to, by a
processor in an microcomputer system External view

 Traditionally written to, “programmed”, enable 2k × n ROM

before inserting to microcomputer system A 0

…
Uses A k-1
• Store software program for general- …
purpose processor Qn-1
Q0

• Store constant data (parameters) needed by

system
• Implement combinational circuits (e.g.,
decoders)

369
 Example: 8 x 4 ROM

 Horizontal lines = words

 Vertical lines = data Internal view

 Lines connected only at circles 8 × 4 ROM

 word 0
Decoder sets word 2’s line to 1 if enabl
3×8
decoder word 1
word 2
address input is 010 Ae
0
word
A1
 Data lines Q3 and Q1 are set to 1 A2 line
because there is a “programmed” data
connection with word 2’s line programm
 able line
Word 2 is not connected with connection
Q 3 Q2 Q1 Q0

data
lines Q2 and Q0
 Output is 1010
370
 Memory – ROM

 Nonvolatile Memory
- SRAM and DRAM and attractive due to their speed

- however, they are volatile which means when the power is removed, the data
is lost

- for a microcomputer, we need a nonvolatile storage device so that upon

power-up, the computer knows what to do.

- currently, the most popular semiconductor ROM is Flash (or EEprom)

- before looking at the details of a Flash transistor, let’s first look at the
different types of ROM arrays and addressing modes

371
 Memory – ROM
 ROM Arrays
- There are two basic types of ROM arrays

1) NOR-based ROM
2) NAND-based ROM
NOR-based ROM
- All Column Lines are pulled-up using a PMOS transistor (or resistor)

- The Row Lines are connected to the gates of NMOS transistors at the intersection
of Row and Column Lines

- The presence or absence of the NMOS transistors dictates whether a 1 or a 0 is

stored

- If the NMOS transistor is present, it will pull down the Column Line when its gate is
driven high by the Row Line

- If the NMOS transistor is absent, the Column Line will not be pulled down, so it
 Memory – ROM

 NOR-based ROM
- In order to Read from the array, the Row line is asserted and the desired Column line is
observed

- a NOR-based ROM is similar to a Hex Keypad

373
 Memory – ROM

 NAND-based ROM
- NAND-based ROM is a different array architecture

- it uses a depletion-load NMOS as the pull-up transistor

- the Column NMOS’s are connected in series with the

column lines (i.e. a NAND configuration)

- If an NMOS exists in the Column line and the Row line

is asserted, the NMOS will pull the Column Line down
and represent a stored ’0’

- If an NMOS is absent on the Column line and the

Row line is asserted, the Column Line will
remain pulled high by the depletion NMOS and
represent a stored ‘1’

- since all of the NMOS’s are in series, in order to

Read
from a Row, all other Rows much be turned ON

- this means in order to distinguish the Row we are

374 asserting,
we write a ‘0’ to it
 Memory – ROM

 NAND-based ROM
- In this configuration, if an NMOS is present, it will
represent a “stored 1” since in order to address its
location, the Row line is driven to a ‘0’ and the NMOS
not turned on. This leaves the Column line pulled
HIGH

- if an NMOS is absent, it will represent a “stored 0”

since all of the other Row NMOS’s are turned on
and will pull the Column Line LOW

- this gives the opposite behavior as in a NOR-

based ROM NOR NAND
NMOS present 0 1
NMOS absent 1 0

- it also gives a complementary addressing

scheme
NOR NAND
Address Row Line by driving: 1 0
All other Row Lines driven to: 0 1
375
 Mask-programmed ROM

 Connections “programmed” at fabrication

• set of masks
 Lowest write ability
• only once
 Highest storage permanence
• bits never change unless damaged
 Typically used for final design of high-volume systems
• spread out NRE (non-recurrent engineering) cost for a low unit
cost

376
 OTP ROM: One-time programmable ROM

 Connections “programmed” after manufacture by user

• user provides file of desired contents of ROM
• file input to machine called ROM programmer
• each programmable connection is a fuse
• ROM programmer blows fuses where connections should not exist
 Very low write ability
• typically written only once and requires ROM programmer device
 Very high storage permanence
• bits don’t change unless reconnected to programmer and more
fuses
blown
 Commonly used in final products
• cheaper, harder to inadvertently modify
377
 EPROM: Erasable programmable ROM

 Programmable component is a MOS transistor

• Transistor has “floating” gate surrounded by an insulator 0V
• (a) Negative charges form a channel between source and floating gate

drain storing a logic 1 source drain

• (b) Large positive voltage at gate causes negative charges to

move out of channel and get trapped in floating gate storing
(a)
a logic 0
• (c) (Erase) Shining UV rays on surface of floating-gate causes
negative charges to return to channel from floating gate +15V
restoring the logic 1
source drain
• (d) An EPROM package showing quartz window through (b)
which UV light can pass
 Better write ability 5-30 min
• can be erased and reprogrammed thousands of times
 Reduced storage permanence source drain

• program lasts about 10 years but is susceptible to (c)

radiation and electric noise
 Typically used during design development (d)
.

378
 Sample EPROM components

379
 Sample EPROM programmers

380
 EEPROM: Electrically erasable programmable
ROM

 Programmed and erased electronically

• typically by using higher than normal voltage
• can program and erase individual words
 Better write ability
• can be in-system programmable with built-in circuit to provide higher
than normal voltage
» built-in memory controller commonly used to hide details from memory
user
• writes very slow due to erasing and programming
» “busy” pin indicates to processor EEPROM still writing
• can be erased and programmed tens of thousands of times
 Similar storage permanence to EPROM (about 10 years)
 Far more convenient than EPROMs, but more expensive
381
 FLASH

 Extension of EEPROM
• Same floating gate principle
• Same write ability and storage permanence
 Fast erase
• Large blocks of memory erased at once, rather than one word at a time
• Blocks typically several thousand bytes large
 Writes to single words may be slower
• Entire block must be read, word updated, then entire block written back
 Used with embedded microcomputer systems storing large data
items in nonvolatile memory
• e.g., digital cameras, MP3, cell phones

382
 Unit IV
SEMICONDUCTOR INTEGRATED CIRCUIT
DESIGN
 Programmable
Logic Array (PLA)
 Programmable
Array Logic(PAL)

Programmable logic
FPGAs devices (PLD)
 CPLDs
 Standard cells
 Design Approach
 Parameters influencing low power design

400
401
 PLD
Programmable logic is defined as a device with configurable
logic and flip-flops linked together with programmable
interconnect.
Why we are going for PLDs
 Problems by Using Basic Gates
 Many components on PCB:
• As no. of components rise, nodes interconnection complexity
grow exponentially
• Growth in interconnection will cause increase in interference, PCB size, PCB
design cost, and manufacturing time

402
403
404
 PROGRAMMABLE LOGIC DEVICES (PLD)

405
PLD Hierarchical
 PLD
 The purpose of a PLD device is to permit elaborate digital logic
designs to be implemented by the user in a single device.

 Can be erased electrically and reprogrammed with a new

design, making them very well suited for academic and
prototyping

 Types of Programmable Logic Devices

 SPLDs (Simple Programmable Logic Devices)
• ROM (Read-Only Memory)
• PLA (Programmable Logic Array)
• PAL (Programmable Array Logic)
• GAL (Generic Array Logic)
 CPLD (Complex Programmable Logic Device)
 FPGA (Field-Programmable Gate Array)

406
 General structure of PLDs.

407
 PLD

 The first three varieties(ROM, PLA, PAL) are

quite similar to each other:
• They all have an input connection matrix, which
connects the inputs of the device to an array of
AND- gates.
• They all have an output connection matrix, which
connect the outputs of the AND-gates to the inputs of
OR-gates which drive the outputs of the device.

 The gate array is significantly different and will be

described later.

408
 PLD
 The differences between the first three categories
are these:
• 1. In a ROM, the input connection matrix is hardwired.
The user can modify the output connection matrix.
• In a PAL/GAL the output connection matrix is
hardwired. The user can modify the input connection
matrix.
• In a PLA the user can modify both the input connection
matrix and the output connection matrix.

409
 Programming by blowing fuses.

(a) Before programming. (b) After

programming.
410
 OR - PLD Notation

411
 AND - PLD Notation

412
413
 PLA

414
 PLA

• A 3×2 PLA with 4 product

terms.
415
 JK FF implementation using PLA

416
417
 Design for PLA:
Example
• Implement the following functions using PLA
F0 = A + B' C'
F1 = A C' + A Input Side:
F
B2 = B' C' + A B
F3 = B' C + A 1 = asserted in term
0 = negated in term
- = does not
Personality Matrix participate
P roduct Inputs
Outputs term A Output Side:
B C F0 F1 F2 1 = term connected to output
F3 Reuse 0 = no connection to output
AB 1 1 - 0 1 1 0 of
BC - 01 0 0 0 1 terms
A 1 - 0 0 1 0 0
C
BC - 00 1 0 1 0
A 1 - - 1 0 0 1
418
 Example: Continued
A B C

F0 = A + B' C' AB
F1 = A C' + A B
F2 = B' C' + A B’C
B F3 = B' C
+ A AC’
B’C’

Personality Matrix A

Pr oduc Inpu s Outputs

t F F1 F2 F3
t C 0
term
A B F0 F1 F2 F3
0 1 1 0 Reus
AB 1 1 -
e of
BC - 0 1 0 0 0 1
terms
AC 1 - 0 0 1 0 0
BC - 0 0 1 0 1 0
A 1 - - 1 0 0 1

419
 BCD to Gray Code Converter
A B C D W X Y Z A A
0 0 0 0 0 0 0 0 AB AB
0 0 0 1 0 0 0 1 CD 00 01 11 10 CD 00 01 11 10
0 0 1 0 0 0 1 1 00 0 0 X 1 00 0 1 X 0
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
01 0 1 X 1 01 0 1 X 0
0 1 0 1 1 1 1 0
0 1 1 0 1 0 1 0 D D
11 0 1 X X 11 0 0 X X
0 1 1 1 1 0 1 1
1 0 0 0 1 0 0 1 C C
1 0 0 1 1 0 0 0 10 0 1 X X 10 0 0 X X
1 0 1 0 X X X X
1 0 1 1 X X X X B B
1 1 0 0 X X X X
K-map for K-map for
1 1 0 1 X X X X W X
1 1 1 0 X X X X
1 1 1 1 X X X X A A
AB AB
CD 00 01 11 10 CD 00 01 11 10

0 0 1 X 0 0 0 0 X 1
0 0
0 1 X 0
Minimized Functions: 01 01 1 0 X 0
D D
11 1 1 X X 11 0 1 X X
W=A+BD+B C C
C X = B C' 10 1 1 X X 10 1 0 X X
Y=B+C
Z = A'B'C'D + B C D + A D' + B' C B B
K-map for K-map for
D'
420 Y Z
 A B C D

A
BD

4 product terms per each OR gate BC

BC’

Product terms cannot be shared !

B
PLA achieves higher flexibility
C
at the cost of lower speed!

BCD
AD’

BCD’

421 W X Y Z
422
423
424
 PALs
 Programmable Array Logic
• a fixed OR array.

Input
s

Dense array Dense array

of AND Produc of OR
gates t gates
terms

Output
s

42
5
 A simple four-input, three-output PAL device.

426
 An example of using a PAL device to realize two
Boolean functions. (a) Karnaugh maps. (b) Realization.

427
 PAL

W = ABC + CD
X = ABC + ACD + ACD +
BCD
Y = ACD + ACD + ABD
428
 FPGA AND CPLD

1. FPGA - Field-Programmable Gate Array.

2. CPLD - Complex Programmable Logic Device
3. FPGA and CPLD is an advance PLD.
4. Support thousands of gate where as PLD only
support hundreds of gates.

429
 What is an FPGA?
 Before the advent of programmable logic, custom logic circuits were
built at the board level using standard components, or at the gate
level in expensive application-specific (custom) integrated circuits.

 FPGA is an integrated circuit that contains many (64 to over 10,000)

identical logic cells that can be viewed as standard components. Each
logic cell can independently take on any one of a limited set of
personalities.

 Individual cells are interconnected by a matrix of wires and

programmable switches. A user's design is implemented by
specifying the simple logic function for each cell and selectively
closing the switches in the interconnect matrix.

 Array of logic cells and interconnect form a fabric of basic building

blocks for logic circuits. Complex designs are created by combining
these basic blocks to create the desired circuit

430
 What does a logic cell do?
 The logic cell architecture varies between different device families.

 Each logic cell combines a few binary inputs (typically between 3 and
10) to one or two outputs according to a Boolean logic function
specified in the user program .

 In most families, the user also has the option of registering the
combinatorial output of the cell, so that clocked logic can be easily
implemented.

 Cell's combinatorial logic may be physically implemented as a small

look-up table memory (LUT) or as a set of multiplexers and gates.

 LUT devices tend to be a bit more flexible and provide more inputs
per cell than multiplexer cells at the expense of propagation delay.

431
 What does 'Field Programmable' mean?
 Field Programmable means that the FPGA's function is defined by a
user's program rather than by the manufacturer of the device.

 A typical integrated circuit performs a particular function defined at

the time of manufacture. In contrast, the FPGA's function is defined
by a program written by someone other than the device
manufacturer.

 Depending on the particular device, the program is either 'burned'

in permanently or semi-permanently as part of a board assembly
process, or is loaded from an external memory each time the device
is powered up.

 This user programmability gives the user access to complex

integrated designs without the high engineering costs associated with
application specific integrated circuits.

432
 How are FPGA programs created?
 Individually defining the many switch connections and cell
logic functions would be a daunting task.

 This task is handled by special software. The software translates a

user's schematic diagrams or textual hardware description
language code then places and routes the translated design.

 Most of the software packages have hooks to allow the user to

influence implementation, placement and routing to obtain
better performance and utilization of the device.

 Libraries of more complex function macros (eg. adders) further

simplify the design process by providing common circuits that
are already optimized for speed or area.

433
 FPGA
 FPGA applications:-
i. DSP
ii. Software-defined radio
iii. Aerospace
iv. Defense system
v. ASIC Prototyping
vi. Medical Imaging
vii. Computer vision
viii. Speech Recognition
ix. Cryptography
x. Bioinformatic
xi. And others.
434
 Xilinx Spartan-3E Starter Kit

FPGA

buttons LEDs
switches

435
 FPGA Principles

 A Field-Programmable Gate Array (FPGA) is an

integrated circuit that can be configured by the
user to emulate any digital circuit as long as there
are enough resources
 An FPGA can be seen as an array of Configurable
Logic Blocks (CLBs) connected through
programmable interconnect (Switch Boxes)

436
 FPGA structure

CLB SB CLB

SB SB SB

Configurable Logic Blocks

CLB SB CLB

Interconnection Network

I/O Signals (Pins)

437
 Simplified CLB Structure

Look-Up MUX
SET
Table D Q
(LUT)

CLR Q
CLB SB CLB

SB SB SB

Configurable Logic Blocks

CLB SB CLB
Interconnection Network

I/O Signals (Pins)

 A
Example: 4-input AND gate
O
B
C

AD B C D O
0 0 0 0 0
0 0 0 1 0 0
0
0 0 1 0 0 0

0 0 1 1 0
A 0
MUX O
0
0 SET
0 1 0 0 0 0 D Q
0
0 1 0 1 0 0
B
C 0
0 1 1 0 0 0
0 CLR Q
0 1 1 1 0 0
0
0
1 0 0 0 0 0
D 1
1 0 0 1 0
1 0 1 0 0 Configuration bits
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1
6/3/2015
1 1 1 1
 Example 2: Find the configuration
bits for the following circuit
A0
2-to-1 D SET

MUX
Q

A1

CLR Q

S A MU
Clock SE X
0 DT
A0 A1 S Q
AS
0 0 0
0 0 1 1 CLR Q
0 1 0
0 1 1
1 0 0
Configuration
1 0 1
bits
1 1 0
6 /3/
1 1 1
 Interconnection Network

Configuration
bits 0 1
0

CLB SB CLB 0
0 0

SB SB SB

Configurable Logic Blocks

CLB SB CLB

Interconnection Network

I/O Signals (Pins)

 Example 3
 Determine the configuration bits for the following circuit implementation
in a 2x2 FPGA, with I/O constraints as shown in the following figure.
Assume 2-input LUTs in each CLB.
Input1

Input2
CLB0 SB0 CLB1
Input1 D
SET
Q
Output
Input2
Input3 CLR Q
SB1 SB2 SB3

Input3
CLB2 SB4 CLB3 Output
 CLBs required
CLB 1 CLB 2
Input1 D
SET
Q
Output
Input2 CLR Q

Input3

0
0
MUX O MUX Output
SET

Input1 0 D Q D
SET
Q
O 1

0 Input3 1
CLR Q Q
Input2 1 CLR

1 0
0

Configuration bits Configuration bits

 Placement: Select CLBs
Input1

Input2
CLB0 SB0 CLB1

SB1 SB2 SB3

Input3
CLB2 SB4 CLB3 Output

444
 Routing: Select path
Input1
SB1

Configuration bits

Input2
CLB0 SB0 CLB1
0 0
0

1
0 0
SB1 SB2 SB3

SB4

Configuration bits
Input3
CLB2 SB4 CLB3 Output

0 0
1

0
0 0
445
 Configuration Bitstream
 The configuration bitstream must include ALL CLBs
and SBs, even unused ones
 CLB0: 00011
 CLB1: 01100
 CLB2: XXXXX
 CLB3: ?????
 SB0: 000000
 SB1: 000010
 SB2: 000000
 SB3: 000000
 SB4: 000001

446
 FPGA Advantages

 Long time availability

 Can be updated and upgraded at your customer's
site
 Extremely short time to market
 Fast and efficient systems
 Performance gain for software applications
 Real time applications
 Massively parallel data processing

447
 FPGA EDA Tools

 Must provide a design environment based on

digital design concepts and components (gates,
flip-flops, MUXs, etc.)
 Must hide the complexities of placement,
routing and bitstream generation from the
user. Manual placement, routing and bitstream
generation is infeasible for practical FPGA
array sizes and circuit complexities.

448
 Design of approach of IC

449
450
 Silicon Wafers: Basic unit
• Silicon Wafers Basic processing unit
• 150, 200, 300 mm disk, 0.5 mm thick
• Newest ones 300 mm (12 inches)
• Typical process 25 - 1000 wafers/run
• Each wafer: 100 - 1000's of microchips (die)
• Wafer cost $10 - $100's
• 200 mm wafer weight 0.040 Kg
• Typical processing costs $1200/wafer (200
mm)
• Typical processed wafer value $11,000
(all products, modest yield)
• Value/Mass of processed wafer $275,000/Kg

451
 CPLD
1. Complexity of CPLD is between FPGA and PLD.
2. CPLD featured in common PLD:-
i. Non-volatile configuration memory – does not need an
external configuration PROM.
ii. Routing constraints. Not for large and deeply layered
logic.
3. CPLD featured in common FPGA:-
i. Large number of gates available.
ii. Can include complicated feedback
4.
path.
CPLD application:-
i. Address coding
ii. High performance control
logic
452 iii. Complex finite state machines
 CPLD
5. CPLD architecture:-

LAB – Logic Array Block / uses PALs

PIA – Programmable Interconnect Array
453