Data Path Operation

Salahuddin Ahmed
 Basic Concept
• Generally we have n bit data that is being
processed.
• Facilitate the process using n identical
circuits (named bit slice)
• Bit slices are placed adjacent to each
other.
• Data is relayed from one operation to the
next in one direction.
• Control usually runs orthogonal to data.
Ripple Carry Adder (RCA)
CoutN CoutN
BN BN

AN
+ SN
AN
+ SN
…

…
…
Cout1 B1 Cout1
B1 ●

A1
+ S1
A1
+ S1

Cout0 B0 Cout0
B0 ●

A0
+ S0
A0
+ S0

sub/add
●
CIN CIN
 Carry Save Adder
B2 B2 B2 C2

n bit add takes

A2 A2 A2
+ S2
n stages of
pipelining
B1 B1 C1

A1 A1
+ S1 S1 has a latency of
n x clock period

C0

B0

A0
+ S0 S0 S0

CIN
Carry Save Adder (cont.)
B3 B3 C3

n bit add takes n/2 stages

A3 A3
+ S3

latency = n/2 x clock period

B2 B2
+ S2

A2 A2

C1
B1

A1
+ S1 S1

B0

A0
+ S0 S0

CIN
Carry Look Ahead Adder (CLA)
• Carry of ith stage (Ci) can be obtained by
Ci = Gi + Pi Ci-1
• Gi = Ai Bi
• Pi = Ai + Bi or Pi = Ai Bi
• Suppose Cin = 0 for 1st stage
C0 = G0 + P0 Cin = G0
C1 = G 1 + P1 C0 = G 1 + P1 G 0
C 2 = G 2 + P 2 C 1 = G 2 + P 2 G 1 + P 2 P1 G 0
C 3 = G 3 + P 3 C 2 = G 3 + P 3 G 2 + P 3 P 2 G 1 + P 3 P 2 P1 G 0
 CLA (cont.)
• Si = Ci-1  Ai  Bi
= Ci-1  Pi if Pi = Ai  Bi

• S0 = Cin  P0 = P0 (if Cin = 0)


• S1 = C 0 P 1

• S2 = C 1  P 2
• S3 = C 2 P 3
 CLA (cont.)
P3

….
…
B3 ●
A3 ● G3 C3

G2
P2 P3
G3
B2 ● G2
A2 ●

…
C2
P1 G1
P2

B1 G2
● G1
A1 ● G0
P1 C1
P0
G1
B0 ● G0 C0
A0 ●
 Carry Select Adder
A7 ~ A 4 B7 ~ B 4

4 4

+ + + + C7 (1)
S3 ~ S 0

4 4

+ + + +
C3 C7
● 4-bit 2to1 MUX S7 ~ S 4

4
4
4 4

A3 ~ A 0 B3 ~ B 0
+ + + + C7 (0)

4 4
Could be a CLA

A7 ~ A 4 B7 ~ B 4
 Multiplier
• Array Multiplier x1 x0
y0 y0
x1 x 0 + P
+ P

y1 y 0 C C

x1 x0
y1 y1
x1y0 x0y0 + +
P P

x1y1 x0y1 C C

P3 P2 P1 P0 Adder
 Serial/Parallel Multiplier
0 = w3 1 = w2 1 = w1
● ● 1, 1, 0
x 0, x 1, x 2

FA FA FA
C S C S C S

Reg

• n bit slices where n = 3

• 3 x 3 multiply in 2n clock cycles i.e. 6 clock
cycles
• fclk = 1 / ( tFA + tand + tsetup(FF) )
 Serial/Parallel Multiplier
w2 w1 w0 0 1 1
x2 x 1 x 00 1 1
0 0 0 0 1 1
0 0 0 1 1 x
0 0 1 0 0 1
Adder Inputs 0 0 0 0 0 1 0 0 1

Reg Outputs 0 0 0 1 0 1 1st Clk P0 = 1

Adder Inputs 0 0 0 0 0 1 0 1 1

Reg Outputs 0 0 0 1 1 0 2nd Clk P1 = 0

Adder Inputs 0 0 0 0 0 0 1 1 0

Reg Outputs 0 0 0 0 1 0 3rd Clk P2 = 0

Adder Inputs 0 0 0 0 0 0 1 0 0

Reg Outputs 0 0 0 0 0 1 4th Clk P3 = 1

 Misc.
A /A /A A

/B
XOR / XNOR gates
using pass transistor
B

A B A B Cross Coupled Inverter:

To bring differential outputs of
DPTL gates to full logic level

In /In

/out out FF
 I/O Pads
• Vdd / Gnd Pads
• Output Pad
• Input Pad Proper size for bonding 100 μ x 100μ
• Tri-state Pad
• I/O Pads
 1 
Output Pad I    V gs  VT Vds  Vds2  10mA
 2 

on chip TTL Load

circuit Pad
10 pF
 I/O Pads
Input Pad

R
into on
Pad chip ckt
2K CL
BIG
Cap

Tri-state Pad
E

Pad
from on D ●
chip ckt E = ‘0’  Tri-state
E = ‘1’  Output Pad
 I / O Pad

E = ‘0’  Tri-state
E = ‘1’  Output Pad

ckt
into on chip
E R

Pad
D ● 2K CL

from on chip
ckt