TEE2027 (Part1) Lecture - Topic 4 - MOSFET
TEE2027 (Part1) Lecture - Topic 4 - MOSFET
o Holes in the p-type semiconductor o Holes are pushed away from the
are pushed towards the oxide- interface creating a negative space-
semiconductor interface charge region.
o A thin channel of electrons is enhanced underneath the oxide layer if the
voltage is applied as shown in the right-side image.
o This electron inversion layer can be used as a conductor.
Introduction
Structure of n-channel MOSFET
o Three terminals: Gate, Source and Drain.
o The regions under the source and the
gate are heavily doped n-type for a p-
type substrate.
o These regions are heavily doped p-type
for an n-type substrate
Enhancement Depletion
ID
D Simplified symbol MOSFET
+
VGS: Gate voltage
Gate is insulated (used in this note)
+ VDS
- ID : Drain current
from the rest of
VGS -
G
region
o
[F (farad)] Channel
region
Non- vGS VTH vDS vGS – VTH iD = f (vDS ,vGS) CMOS Logic –
saturation ON state
20 kΩ
Large Signal Model (Saturation Region)
o For an n-channel MOSFET in the saturation region, i.e.,
𝑉 𝐺𝑆 > 𝑉 𝑇𝐻 and 𝑉 𝐷𝑆 ≥𝑉 𝐷𝑆, 𝑠𝑎𝑡 =𝑉 𝐺𝑆 −𝑉 𝑇𝐻
( )
2
10 V 𝜇 𝑛 𝑊 𝐶 𝑜𝑥 𝑉 −5 𝐴
𝐾 𝑛= = =5 × 10
2𝐿 2 𝑉
2
RD
R1 5 kW
5 kW ID D
o Since gate current is zero, you can use voltage
IG divider rule to find the gate voltage:
G 5𝑘
𝑉 𝐺𝑆 = ×10 𝑉 =5 𝑉 .
S 5 𝑘+ 5 𝑘
R2
5 kW IS o You can also use Thevenin equivalent of the gate-
biasing circuit to find
Gate-biasing circuit
DC Analysis
Example #1 (contd…) o Assume saturation mode (need to check later)
10 V o Replace MOSFET with the large-signal model
2
RD 𝐼 𝐷 = 𝐼 𝐷 , 𝑠𝑎𝑡 = 𝐾 𝑛 ( 𝑉 𝐺𝑆 −𝑉 𝑇𝐻 )
5 kW
2.5 kW IG = 0 ID 𝑉 𝐺𝑆 =5 𝑉 ,𝑉 𝑇 =1 𝑉
D
G
+ 𝐴 𝑚𝐴
𝐾 𝑛=5× 10− 5 =0.05
5V
+ VGS 𝑉2 𝑉2
- - Kn(VGS-VTH)2
IS = ID
S
𝐼 𝐷 =0.05
𝑚𝐴
𝑉 ( )
2
× ( 5 𝑉 − 𝐼 𝐷 × 5 −1 𝑉 )
2
2
𝐼 𝐷 =0.05 × ( 4 − 5 𝐼 𝐷 )
DC Analysis
Example 2 (continued) 𝐼 𝐷 =0.05 × ( 4 − 5 𝐼 𝐷 ) 2 in mA
10 V 10 V RS in kΩ
Note that the
voltage at the
RD
o Solving this quadratic equation,
R1 gate VG is 5 V, as
5 kW IG = 0. 5 kW 𝐼 𝐷 =2.09 𝑚𝐴𝑜𝑟 0.31 𝑚𝐴
ID
IG = 0
D o ID = 2.09 mA cannot be a solution because
G
+ that will require VS > 10 V
VGS
R2
5 kW - Kn(VGS-VTH)2 o ID = 0.31 mA is the solution and
IS = ID
S
𝑉 𝐷 =8.45 𝑉 ,𝑉 𝑆 =1.55 𝑉
RS
5 kW 𝑉 𝐷𝑆 = 6.90𝑉 , 𝑉 𝐺𝑆 =3.45 𝑉
Check that MOSFET is indeed in saturation: & .
Large-Signal Model for
N-MOSFET in Saturation
Small Signal Model (AC Analysis)
o Small-signal model is needed when we want to analyze MOSFET amplifier
VDD VDD = 10 V VDD = 10 V
RD ID RD RD
5 kW 5 kW id
iD 5 kW
D
RG IG
D
+
D i
=
RG i G RG g
G G
G S vs S
vs
S VGG + IS is
+ =5V -
VGG iS
-
DC Analysis AC Analysis
Find ID and VDS for Find id and vds for given vs at
𝑣 𝐺𝑆 =𝑉 𝐺𝑆 +𝑣 𝑔𝑠
given VDD & VGG the operating point (ID, VDS)
𝑣 𝐷𝑆 =𝑉 𝐷𝑆 + 𝑣 𝑑𝑠
Large-signal model Small-signal model
𝑖 𝐷= 𝐼 𝐷 +𝑖𝑑
Small Signal Model (ac analysis)
𝑖𝑑 iD
o At the operating point, =𝑠𝑙𝑜𝑝𝑒𝑜𝑓 𝑡h𝑒 𝑔𝑟𝑎𝑝h
𝑣 𝑔𝑠
Gradient at Q
o We need to find the slope of the graph Small change
in drain current. ==
𝑖 𝐷= 𝐾 𝑛 ( 𝑣 𝐺𝑆 − 𝑉 𝑇𝐻 )2 ID + i d
¿¿
id
ID Bias Point Q
Small change
in gate-to
source voltage.
vgs
𝑖𝑑
o Therefore, =2 𝐾 𝑛 ( 𝑉 𝐺𝑆 −𝑉 𝑇𝐻 ) =𝑔𝑚 vGS
𝑣 𝑔𝑠 VT VGS
𝑖𝑑 =𝑔𝑚 𝑣 𝑔𝑠 G
ig = 0 id
D
+ +
o Transconductance of MOSFET: vgs vds gmvgs
- -
𝑔 𝑚=2 𝐾 𝑛 ( 𝑉 𝐺𝑆 − 𝑉 𝑇𝐻 )
is
S
MOSFET Amplifier VDD
RD
o In the presence of an ac (small signal) source: iD 5 kW
+
𝑣 𝐺𝑆 =𝑉 𝐺𝑆 +𝑣 𝑔𝑠 RG i G
D
vDS
𝑉 𝐷𝐷 −𝑉 𝐷𝑆 𝑉 𝐷𝐷 1
𝑖 𝐷= = − 𝑉 𝐷𝑆
𝑖 𝐷= 𝐼 𝐷 +𝑖𝑑
-
𝑅𝐷 𝑅𝐷 𝑅𝐷
G
vs
S
𝑖𝑑 + iD
=𝑔𝑚 VGG
-
𝑣 𝑔𝑠
ID ID
VTH VGS
𝑣 𝐷𝑆 =𝑉 𝐷𝑆 + 𝑣 𝑑𝑠
Large Signal Model (p-MOSFET)
o In the saturation region: under dc condition -
S S
+ IS
VSG IS
VTH for P-MOSFET
G - is negative.
+
IG = 0 is equivalent to VSG
ID Kp (|VGS| - |VTH|)2
G
-
D
D IG = 0 ID
(
𝑖 𝐷= 𝐾 𝑛 ( 𝑣 𝐺𝑆 −𝑣 𝑇𝐻 )2 1+
𝑣 𝐷𝑆
𝑉𝐴 ) 2
𝑖 𝐷= 𝐾 𝑛 ( 𝑣 𝐺𝑆 − 𝑣 𝑇𝐻 ) ( 1+ 𝑣 𝐷𝑆 )
MOSFET: AC Analysis
o Suppose a MOSFET is biased to operate in the saturation mode. This mode is used for
amplifier application.
o A small ac voltage is superimposed to the gate voltage
2
𝐼 𝐷 = 𝐾 𝑛 ( 𝑉 𝐺𝑆 − 𝑉 𝑇𝐻 ) ( 1+ 𝑉 𝐷𝑆 ) N-channel
¿ 𝐼 𝐷 ∨¿ 𝐾 𝑛 ( ¿ 𝑉 𝐺𝑆 ∨−∨ 𝑉 𝑇𝐻 }) ¿ P-channel
2
𝟐𝑰𝑫
Transconductance: 𝒈 𝒎 =𝟐 𝑲 𝒏 ( 𝑽 𝑮𝑺 −𝑽 𝑻𝑯 )= =𝟐 √ 𝑲 𝒏 𝑰 𝑫
( 𝑽 𝑮𝑺 − 𝑽 𝑻𝑯 )
MOSFET: Output Resistance
o Output resistance models a small change in drain current (id) due to a small change in drain-
to-source voltage (vds)
𝑣 𝑑𝑠
𝑟𝑜=
𝑖𝑑
For ideal case, output resistance is infinity. For non-ideal case, slope of the graph is
the inverse of the output resistance.
MOSFET: Output Resistance
o The id in the non-ideal case is related to vds by the equation:
𝑖 𝐷= 𝐾 𝑛 ( 𝑣 𝐺𝑆 −𝑉 𝑇𝐻 ) 1+2
𝑉𝐴 (
𝑣 𝐷𝑆
)
2
𝜕 𝑖𝐷 𝐾 𝑛 ( 𝑣 𝐺𝑆 −𝑉 𝑇𝐻 ) 𝐼𝐷
= ≈
𝜕 𝑣 𝐷𝑆 𝑉𝐴 𝑉𝐴
𝑉𝐴
𝑟𝑜=
𝐼𝐷
For non-ideal case, slope of the graph is
the inverse of the output resistance.