Multiplexer, Demultiplexer and Decoder
WHAT IS A MULTIPLEXER (MUX) ?
A MUX is a digital switch that has
multiple inputs (Sources) and a
single output (destination).
The select lines determine which
input is connected to the output.
MUX Types
2 to 1 (1 select line)
4 to 1 (2 select lines)
8 to 1 (3 select lines) A multiplexer has
• N control inputs
16 to 1 (4 select lines)
• data inputs
• 1 output
TYPICAL APPLICATION OF MULTIPLEXER (MUX)
MULTIPLEXER (MUX)
Data
inputs
Control
input Z = A′.I0 + A.I1
4 to 1 MULTIPLEXER (MUX)
A B F
0 0 I0
0 1 I1
1 0 I2
1 1 I3
MSB LSB
Z = A′.B'.I0 + A'.B.I1 + A.B'.I2 + A.B.I3
4 to 1 MULTIPLEXER (MUX) WAVEFORMS
8 to 1 MULTIPLEXER (MUX)
A B C F
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7
MSB LSB
Z = A′.B'.C'.I0 + A'.B'.C.I1 + A'.B.C'.I2 + A'.B.C.I3 +
A.B'.C'.I0 + A.B'.C.I1 + A'.B.C'.I2 + A.B.C.I3
8 to 1 MULTIPLEXER (MUX)
Implementation of Different Gates with 2:1 Mux
Implementation of NOT gate using 2 : 1 Mux
The Not gate from 2:1 Mux can be obtained by
•Connect the input signal to one of the data input lines(I0).
•Then connect a line (0 or 1) to the other data input line(I1)
•Connect the same input line Select line S0 which is connected to D0.
Given Below is the Diagram for the Logical Representation of NOT gate using 2 : 1 Mux
Implementation of Different Gates with 2:1 Mux
Implementation of AND gate using 2 : 1 Mux
The And gate from 2:1 Mux can be obtained by
•Connect the input Y to I1.
•Connect the input X to the selection line S0.
•Connect a line(0) to I0.
Given Below is the Diagram for the Logical Representation of AND gate using 2 : 1 Mux
Implementation of Different Gates with 2:1 Mux
Implementation of OR gate using 2 : 1 Mux
The OR gate from 2:1 Mux can be obtained by
•Connect input X to the selection line S0.
•Connect input Y to I1.
•Connect Line(1) to I1.
Given Below is the Diagram for the Logical Representation of OR gate using 2 : 1 Mux
Implementation of Higher Order MUX using Lower Order MUX
4 : 1 MUX using 2 : 1 MUX
•Three 2: 1 MUX are required to implement
Implementation of Higher Order MUX using Lower Order MUX
16 : 1 MUX using 4 : 1 MUX
Five 5: 1 MUX are required to implement 16 : 1
MUX.
WHAT IS A DEMULTIPLEXER (DEMUX) ?
A DEMUX is a digital switch with
a single input (Sources) and a
multiple output (destination).
The select lines determine which
output the input is connected to
DEMUX Types
1 to 2 (1 select line)
1 to 4 (2 select lines)
1 to 8 (3 select lines)
1 to 16 (4 select lines) A demultiplexer has
N control inputs
1 data inputs
output
TYPICAL APPLICATION OF DEMULTIPLEXER (DEMUX
1 to 4 DEMULTIPLEXER (DEMUX)
W = A'.B'.I
Out0 W
Out1 X X = A.B'.I
I In Out2 Y Y = A'.B.I
Out3 Z Z = A.B.I
S1 S0
A B
A B W X Y Z
0 0 I 0 0 0
0 1 0 I 0 0
1 0 0 0 I 0
1 1 0 0 0 I
1 to 4 DEMULTIPLEXER (DEMUX)
1 to 4 DEMULTIPLEXER (DEMUX) WAVEFORMS
Demultiplexers as general-purpose logic
Cascading Demultiplexers
DECODER
Discrete quantities of information are represented in digital computers with binary
codes.
A binary code of n bits is capable of representing up to 2n distinct elements of
the coded information.
A decoder is a combinational circuit that converts binary information from the n coded
inputs to a maximum of 2n unique outputs.
If the n-bit coded information has unused bit combinations, the decoder may have less
than 2n outputs.
The decoders presented in this section are called n-to-m-line decoders, where m <= 2n.
Their purpose is to generate the 2n (or fewer) binary combinations of the n input
variables. A decoder has n inputs and m outputs and is also referred to as an n x m
decoder.
DECODER
• A decoder has
• N inputs
• 2N outputs
• A decoder selects one of 2N outputs by decoding the binary
value on the N inputs.
• The decoder generates all of the min terms of the N input
variables.
• Exactly one output will be active for each combination of the
inputs.
DECODER
W = A'.B'
Out0 W
B I0 Out1 X X = A.B'
A I1 Out2 Y Y = A'.B
Out3 Z
msb Z = A.B
Active-high outputs
A B W X Y Z
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
DECODER
W = (A'.B')'
Out0 W
B I0 Out1 X X = (A.B')'
A I1 Out2 Y Y = (A'.B)'
Out3 Z
msb Z = (A.B)'
Active-low outputs
A B W X Y Z
0 0 0 1 1 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 1 1 1 0
DECODER
msb
DECODER WITH ENABLE
Out0 W
B I0
high-level Out1 X
enable A I1
Out2 Y
Out3 Z
Enable En
En A B W X Y Z
1 0 0 1 0 0 0
1 0 1 0 1 0 0
enabled
1 1 0 0 0 1 0
1 1 1 0 0 0 1
disabled 0 x x 0 0 0 0
DECODERS WITH ENABLE
B I0
Out0 W
low-level Out1 X
enable A I1
Out2 Y
Out3 Z
Enable En
En A B W X Y Z
0 0 0 1 0 0 0
0 0 1 0 1 0 0
enabled
0 1 0 0 0 1 0
0 1 1 0 0 0 1
disabled 1 x x 0 0 0 0
DECODER EXPANSION
A technique called decoder expansion can
be utilized to construct larger decoders out
of smaller ones.
For example, two 2-to-4-line decoders
can be combined to construct a 3-to-8-
line decoder.
The Figure shows how the decoders with
enable inputs can be connected to form a
larger decoder.
As you can see that there are two 2-to-4-
line decoders are combined to achieve a 3-
to-8-line decoder.
DECODER EXPANSION
The two least significant bits of the input are
connected to both decoders.
The most significant bit is connected to the
enable input of one decoder and through an
inverter to the enable input of the other
decoder.
It is assumed that each decoder is
enabled when its E input is equal to 1.
When E is equal to 0, the decoder is
disabled and all its outputs are in the 0 level.
When A2 = 0, the upper decoder is enabled
and the lower is disabled.
DECODER EXPANSION
The lower decoder outputs become inactive
with all outputs at 0. The outputs of the upper
decoder generate outputs Do through D3,
depending on the values of A1
andA0(while A2 = 0).
When A2= 1, the lower decoder is
enabled and the upper is disabled. The
lower decoder output generates the binary
equivalent D4, through D7 since these
binary numbers have a 1 in the A2 position.
