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ORCIDThomas Canhao Xu
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2020 – today
- 2022
[j10]Tao Peng, Thomas Canhao Xu
, Yihuai Wang, Fanzhang Li:
Deep Belief Network and Closed Polygonal Line for Lung Segmentation in Chest Radiographs. Comput. J. 65(5): 1107-1128 (2022)- 2020
- [j9]Tao Peng, Thomas Canhao Xu, Yihuai Wang, Hailing Zhou, Sema Candemir, Wan Mimi Diyana Wan Zaki, Shanq-Jang Ruan, Jing Wang, Xinjian Chen:
Hybrid Automatic Lung Segmentation on Chest CT Scans. IEEE Access 8: 73293-73306 (2020)
2010 – 2019
- 2019
- [j8]Tao Peng, Yihuai Wang, Thomas Canhao Xu, Xinjian Chen:
Segmentation of Lung in Chest Radiographs Using Hull and Closed Polygonal Line Method. IEEE Access 7: 137794-137810 (2019) - 2018
- [j7]Tao Peng, Yihuai Wang, Thomas Canhao Xu, Lianmin Shi, Jianwu Jiang, Shilang Zhu:
Detection of Lung Contour with Closed Principal Curve and Machine Learning. J. Digit. Imaging 31(4): 520-533 (2018) - 2017
- [j6]Thomas Canhao Xu, Ville Leppänen:
PEN: a power law-enhanced network design for high efficiency multicore architecture. Concurr. Comput. Pract. Exp. 29(16) (2017) - 2016
- [c30]Thomas Canhao Xu, Jonne Pohjankukka, Ville Leppänen:
Analysing and Modelling the On-Chip Traffic of Parallel Applications. SEAA 2016: 275-282 - [c29]Thomas Canhao Xu, Ville Leppänen:
LUTMap: A Dynamic Heuristic Application Mapping Algorithm Based on Lookup Tables. IDCS 2016: 134-146 - 2015
- [j5]Thomas Canhao Xu, Ville Leppänen, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
PDNOC: Partially diagonal network-on-chip for high efficiency multicore systems. Concurr. Comput. Pract. Exp. 27(4): 1054-1067 (2015) - [c28]Thomas Canhao Xu, Ville Leppänen:
Cache- and Communication-aware Application Mapping for Shared-cache Multicore Processors. ARCS 2015: 55-67 - [c27]Thomas Canhao Xu, Ville Leppänen, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
Trio: A Triple Class On-chip Network Design for Efficient Multicore Processors. HPCC/CSS/ICESS 2015: 951-956 - [c26]Thomas Canhao Xu, Ville Leppänen:
DBFS: Dual Best-First Search Mapping Algorithm for Shared-Cache Multicore Processors. ICA3PP (1) 2015: 185-198 - [c25]Thomas Canhao Xu, Jonne Pohjankukka, Paavo Nevalainen, Ville Leppänen, Tapio Pahikkala:
Parallel Applications and On-chip Traffic Distributions: Observation, Implication and Modelling. ICSOFT-EA 2015: 443-449 - 2014
- [c24]Thomas Canhao Xu, Ville Leppänen, Martti Forsell:
Exploration of a Heterogeneous Concentrated-Sparse On-Chip Interconnect for Energy Efficient Multicore Architecture. CIT 2014: 204-211 - [c23]Mohammad Fattah, Amir-Mohammad Rahmani, Thomas Canhao Xu, Anil Kanduri, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
Mixed-Criticality Run-Time Task Mapping for NoC-Based Many-Core Systems. PDP 2014: 458-465 - [c22]Thomas Canhao Xu, Jussi Toivonen, Tapio Pahikkala, Ville Leppänen:
BDMap: A Heuristic Application Mapping Algorithm for the Big Data Era. UIC/ATC/ScalCom 2014: 821-828 - 2013
- [j4]Thomas Canhao Xu, Gert Schley, Pasi Liljeberg, Martin Radetzki, Juha Plosila, Hannu Tenhunen:
Optimal placement of vertical connections in 3D Network-on-Chip. J. Syst. Archit. 59(7): 441-454 (2013) - [c21]Thomas Canhao Xu, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
MMSoC: a multi-layer multi-core storage-on-chip design for systems with high integration. CompSysTech 2013: 67-74 - [c20]Thomas Canhao Xu, Tapio Pahikkala, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
Optimized multicore architectures for data parallel fast Fourier transform. CompSysTech 2013: 75-82 - [c19]Thomas Canhao Xu, Ville Leppänen, Martti Forsell:
DSNOC: A Hybrid Dense-Sparse Network-on-Chip Architecture for Efficient Scalable Computing. DASC 2013: 528-535 - [c18]Thomas Canhao Xu, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
Evaluate and optimize parallel Barnes-Hut algorithm for emerging many-core architectures. HPCS 2013: 421-428 - [c17]Thomas Canhao Xu, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
OPTNOC: An Optimized 3D Network-on-Chip Design for Fast Memory Access. PaCT 2013: 436-441 - [c16]Thomas Canhao Xu, Ville Leppänen, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
PDNOC: An Efficient Partially Diagonal Network-on-Chip Design. PPAM (1) 2013: 513-522 - 2012
- [j3]Tapio Pahikkala, Antti Airola, Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen, Tapio Salakoski:
Parallelized Online Regularized Least-Squares for Adaptive Embedded Systems. Int. J. Embed. Real Time Commun. Syst. 3(2): 73-91 (2012) - [c15]Thomas Canhao Xu, Tapio Pahikkala, Antti Airola, Pasi Liljeberg, Juha Plosila, Tapio Salakoski, Hannu Tenhunen:
Implementation and Analysis of Block Dense Matrix Decomposition on Network-on-Chips. HPCC-ICESS 2012: 516-523 - [c14]Thomas Canhao Xu, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
A high-efficiency low-cost heterogeneous 3D network-on-chip design. NoCArc@MICRO 2012: 37-42 - [c13]Thomas Canhao Xu, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
Exploration of heuristic scheduling algorithms for 3D multicore processors. Map2MPSoC/SCOPES 2012: 22-31 - 2011
- [j2]Masoud Daneshtalab, Masoumeh Ebrahimi, Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen:
A generic adaptive path-based routing method for MPSoCs. J. Syst. Archit. 57(1): 109-120 (2011) - [j1]Thomas Canhao Xu, Alexander Wei Yin, Pasi Liljeberg, Hannu Tenhunen:
A study of 3D Network-on-Chip design for data parallel H.264 coding. Microprocess. Microsystems 35(7): 603-612 (2011) - [c12]Alexander Wei Yin, Thomas Canhao Xu, Bo Yang, Pasi Liljeberg, Hannu Tenhunen:
Change Function of 2D/3D Network-on-Chip. CIT 2011: 181-188 - [c11]Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen:
Optimal memory controller placement for chip multiprocessor. CODES+ISSS 2011: 217-226 - [c10]Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen:
Optimal number and placement of Through Silicon Vias in 3D Network-on-Chip. DDECS 2011: 105-110 - [c9]Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen:
Study of Hierarchical N-Body Methods for Network-on-Chip Architectures. Euro-Par Workshops (2) 2011: 365-374 - [c8]Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen:
Process scheduling for future multicore processors. INA-OCMC@HiPEAC 2011: 15-18 - [c7]Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen:
A Minimal Average Accessing Time Scheduler for Multicore Processors. ICA3PP (2) 2011: 287-299 - [c6]Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen:
Explorations of optimal core and cache placements for Chip Multiprocessor. NORCHIP 2011: 1-6 - [c5]Tapio Pahikkala, Antti Airola, Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen, Tapio Salakoski:
A Parallel Online Regularized Least-squares Machine Learning Algorithm for Future Multi-core Processors. PECCS 2011: 590-599 - 2010
- [c4]Thomas Canhao Xu, Alexander Wei Yin, Pasi Liljeberg, Hannu Tenhunen:
Operating System Processor Scheduler Design for Future Chip Multiprocessor. ARCS Workshops 2010: 69-76 - [c3]Bo Yang, Thomas Canhao Xu, Tero Säntti, Juha Plosila:
Tree-model based mapping for energy-efficient and low-latency Network-on-Chip. DDECS 2010: 189-192 - [c2]Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen:
A Greedy Heuristic Approximation Scheduling Algorithm for 3D Multicore Processors. Euro-Par Workshops (1) 2010: 281-291
2000 – 2009
- 2009
- [c1]Alexander Wei Yin, Thomas Canhao Xu, Pasi Liljeberg, Hannu Tenhunen:
Explorations of Honeycomb Topologies for Network-on-Chip. NPC 2009: 73-79
Coauthor Index
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