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2020 – today
- 2024
[j36]Fatima Hamdar
, Jérémy Nadal, Charbel Abdel Nour, Amer Baghdadi:
Overlap-Save FBMC Receivers for Massive MIMO Systems. IEEE Trans. Wirel. Commun. 23(8): 9643-9656 (2024)- 2023
- [c65]Fatima Hamdar, Jérémy Nadal, Charbel Abdel Nour, Amer Baghdadi:
Novel transmission technique based on intentional overlapping for spectral efficiency enhancement in multicarrier systems. PIMRC 2023: 1-6 - 2022
- [j35]Oualid Mouhoubi, Charbel Abdel Nour, Amer Baghdadi:
Latency and Complexity Analysis of Flexible Semi-Parallel Decoding Architectures for 5G NR Polar Codes. IEEE Access 10: 113980-113994 (2022) - [j34]Mostafa Rizk, Amer Baghdadi, Michel Jézéquel:
A Literature Survey on Algorithms and Hardware Architectures of Max-Log-MAP Demapping. J. Circuits Syst. Comput. 31(3): 2230001:1-2230001:48 (2022) - [j33]Khaled Alhaj Ali, Amer Baghdadi, Elsa Dupraz, Mathieu Léonardon, Mostafa Rizk, Jean-Philippe Diguet:
MOL-Based In-Memory Computing of Binary Neural Networks. IEEE Trans. Very Large Scale Integr. Syst. 30(7): 869-880 (2022) - [c64]Oualid Mouhoubi, Charbel Abdel Nour, Amer Baghdadi:
Low Latency Architecture Design for Decoding 5G NR Polar Codes. DASIP 2022: 16-28 - [c63]Mostafa Rizk, Dominique Heller, R. Douguet, Amer Baghdadi, Jean-Philippe Diguet:
Optimization of Deep-Learning Detection of Humans in Marine Environment on Edge Devices. ICECS 2022 2022: 1-4 - [c62]Oualid Mouhoubi, Charbel Abdel Nour, Amer Baghdadi:
On the Latency and Complexity of Semi-Parallel Decoding Architectures for 5G NR Polar Codes. ISIVC 2022: 1-6 - [c61]Dominique Heller, Mostafa Rizk, R. Douguet, Amer Baghdadi, Jean-Philippe Diguet:
Marine Objects Detection Using Deep Learning on Embedded Edge Devices. RSP 2022: 1-7 - [c60]Z. Ning, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet:
Enhancing embedded AI-based object detection using multi-view approach. RSP 2022: 15-21 - [c59]Mostafa Rizk, Fatima Slim, Amer Baghdadi, Jean-Philippe Diguet:
Towards Real-Time Human Detection in Maritime Environment Using Embedded Deep Learning. SYSINT 2022: 583-593 - [c58]Fatima Hamdar, Jérémy Nadal, Charbel Abdel Nour, Amer Baghdadi:
Overlap-Save FBMC receivers for massive MIMO systems under channel impairments. VTC Spring 2022: 1-7 - 2021
- [j32]Mostafa Rizk, Amer Baghdadi, Michel Jézéquel, Yasser Mohanna, Youssef Atat:
No-instruction-set-computer design experience of flexible and efficient architectures for digital communication applications: two case studies on MIMO turbo detection and universal turbo demapping. Des. Autom. Embed. Syst. 25(1): 1-42 (2021) - [j31]Mostafa Rizk, Amer Baghdadi, Michel Jézéquel, Youssef Atat, Yasser Mohanna:
NISC-Based MIMO MMSE Detector. J. Circuits Syst. Comput. 30(4): 2150069:1-2150069:35 (2021) - [j30]Muhammad Najam-ul-Islam, Muhammad Nauman, Atif Raza Jafri, Jérémy Nadal, Charbel Abdel Nour, Amer Baghdadi:
Hardware Implementation of Overlap-Save-Based Fading Channel Emulator. IEEE Trans. Circuits Syst. II Express Briefs 68(3): 918-922 (2021) - [j29]Jérémy Nadal, Amer Baghdadi:
Parallel and Flexible 5G LDPC Decoder Architecture Targeting FPGA. IEEE Trans. Very Large Scale Integr. Syst. 29(6): 1141-1151 (2021) - [c57]Hugo Le Blevec, Rami Klaimi, Stefan Weithoffer, Charbel Abdel Nour, Amer Baghdadi:
Low Complexity Non-binary Turbo Decoding based on the Local-SOVA Algorithm. ISTC 2021: 1-5 - 2020
- [j28]Khaled Alhaj Ali, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet, Jalal Jomaah, Naoya Onizawa, Takahiro Hanyu:
Memristive Computational Memory Using Memristor Overwrite Logic (MOL). IEEE Trans. Very Large Scale Integr. Syst. 28(11): 2370-2382 (2020) - [j27]Jérémy Nadal, François Leduc-Primeau, Charbel Abdel Nour, Amer Baghdadi:
Overlap-Save FBMC Receivers. IEEE Trans. Wirel. Commun. 19(8): 5307-5320 (2020) - [c56]Khaled Alhaj Ali, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet, Jalal Jomaah:
Memristor Overwrite Logic (MOL) for Energy-Efficient In-Memory DNN. ISCAS 2020: 1-5 - [c55]Jérémy Nadal, Amer Baghdadi:
FPGA based design and prototyping of efficient 5G QC-LDPC channel decoding. RSP 2020: 1-7
2010 – 2019
- 2019
- [j26]Mostafa Rizk, Amer Baghdadi, Michel Jézéquel:
Computational Complexity Reduction of MMSE-IC MIMO Turbo Detection. J. Circuits Syst. Comput. 28(13): 1950228:1-1950228:26 (2019) - [c54]Khaled Alhaj Ali, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet, Jalal Jomaah:
MRL Crossbar-Based Full Adder Design. ICECS 2019: 674-677 - [c53]Khaled Alhaj Ali, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet, Jalal Jomaah:
Crossbar Memory Architecture Performing Memristor Overwrite Logic. ICECS 2019: 723-726 - 2018
- [j25]Jérémy Nadal, Charbel Abdel Nour, Amer Baghdadi:
Design and Evaluation of a Novel Short Prototype Filter for FBMC/OQAM Modulation. IEEE Access 6: 19610-19625 (2018) - [j24]Jean-Philippe Diguet, Naoya Onizawa, Mostafa Rizk, Martha Johanna Sepúlveda, Amer Baghdadi, Takahiro Hanyu:
Networked Power-Gated MRAMs for Memory-Based Computing. IEEE Trans. Very Large Scale Integr. Syst. 26(12): 2696-2708 (2018) - [j23]Jérémy Nadal, Charbel Abdel Nour, Amer Baghdadi:
Novel UF-OFDM Transmitter: Significant Complexity Reduction Without Signal Approximation. IEEE Trans. Veh. Technol. 67(3): 2141-2154 (2018) - [c52]Jérémy Nadal, François Leduc-Primeau, Charbel Abdel Nour, Amer Baghdadi:
A Block FBMC Receiver Designed for Short Filters. ICC 2018: 1-6 - [c51]Mostafa Rizk, Amer Baghdadi, Michel Jézéquel, Ali Chamas Al Ghouwayel:
NISC Design Experience of Flexible Architectures for Digital Communication Applications. ICCA 2018: 123-129 - [c50]Muhammad Waqas, Atif Raza Jafri, Amer Baghdadi, Muhammad Najam-ul-Islam:
Rapid Prototyping of Parameterized Rotated and Cyclic Q Delayed Constellations Demapper. RSP 2018: 29-35 - 2017
- [j22]Atif Raza Jafri, Amer Baghdadi, Muhammad Waqas, Muhammad Najam-ul-Islam:
High-Throughput and Area-Efficient Rotated and Cyclic Q Delayed Constellations Demapper for Future Wireless Standards. IEEE Access 5: 3077-3084 (2017) - [j21]Vianney Lapotre, Guy Gogniat, Amer Baghdadi, Jean-Philippe Diguet:
Dynamic configuration management of a multi-standard and multi-mode reconfigurable multi-ASIP architecture for turbo decoding. EURASIP J. Adv. Signal Process. 2017: 35 (2017) - [j20]Mostafa Rizk, Amer Baghdadi, Michel Jézéquel, Yasser Mohanna, Youssef Atat:
Efficient quantization and fixed-point representation for MIMO turbo-detection and turbo-demapping. EURASIP J. Embed. Syst. 2017: 33 (2017) - [j19]Atif Raza Jafri, Amer Baghdadi, Muhammad Najam-ul-Islam, Michel Jézéquel:
Heterogeneous Multi-ASIP and NoC-Based Architecture for Adaptive Parallel TBICM-ID-SSD. IEEE Trans. Circuits Syst. II Express Briefs 64-II(3): 259-263 (2017) - [c49]Khaled Alhaj Ali, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet, Jalal Jomaah:
Towards memristor-based reconfigurable FFT architecture. ICM 2017: 1-4 - [c48]Jérémy Nadal, Charbel Abdel Nour, Amer Baghdadi:
Flexible hardware platform for demonstrating new 5G waveform candidates. ICM 2017: 1-4 - [c47]Mostafa Rizk, Jean-Philippe Diguet, Naoya Onizawa, Amer Baghdadi, Martha Johanna Sepúlveda, Y. Akgul, Vincent Gripon, Takahiro Hanyu:
NoC-MRAM architecture for memory-based computing: Database-search case study. NEWCAS 2017: 309-312 - [c46]Said Medjkouh, Jérémy Nadal, Charbel Abdel Nour, Amer Baghdadi:
Reduced complexity FPGA implementation for UF-OFDM frequency domain transmitter. SiPS 2017: 1-6 - [i2]Jérémy Nadal, Charbel Abdel Nour, Amer Baghdadi:
Design and Evaluation of a Novel Short Prototype Filter for FBMC/OQAM Modulation. CoRR abs/1710.09362 (2017) - 2016
- [j18]Jérémy Nadal, Charbel Abdel Nour, Amer Baghdadi:
Low-Complexity Pipelined Architecture for FBMC/OQAM Transmitter. IEEE Trans. Circuits Syst. II Express Briefs 63-II(1): 19-23 (2016) - [j17]Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Michael Hübner, Jean-Philippe Diguet:
A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 383-387 (2016) - 2015
- [j16]Carlo Condo, Amer Baghdadi, Guido Masera:
Reducing the Dissipated Energy in Multi-standard Turbo and LDPC Decoders. Circuits Syst. Signal Process. 34(5): 1571-1593 (2015) - [j15]Mostafa Rizk, Amer Baghdadi, Michel Jézéquel, Yasser Mohanna, Youssef Atat:
NISC-Based Soft-Input-Soft-Output Demapper. IEEE Trans. Circuits Syst. II Express Briefs 62-II(11): 1098-1102 (2015) - [c45]Valentin Mena Morales, Yahia Brakni, Pierre-Henri Horrein, Amer Baghdadi:
Caasper: providing accessible FPGA-acceleration over the network. RSP 2015: 68-74 - 2014
- [j14]Carlo Condo, Amer Baghdadi, Guido Masera:
Energy-efficient multi-standard early stopping criterion for low-density-parity-check iterative decoding. IET Commun. 8(12): 2171-2180 (2014) - [c44]Valentin Mena Morales, Pierre-Henri Horrein, Amer Baghdadi, Erik Hochapfel, Sandrine Vaton:
Energy-efficient FPGA implementation for binomial option pricing using OpenCL. DATE 2014: 1-6 - [c43]Houcine Chougrani, Jean Schwoerer, Pierre-Henri Horrein, Amer Baghdadi, Francois Dehmas:
UWB-IR digital baseband architecture for IEEE 802.15.6 wireless BAN. ICECS 2014: 866-869 - [c42]Mostafa Rizk, Amer Baghdadi, Michel Jézéquel, Yasser Mohanna, Youssef Atat:
Design and prototyping flow of NISC-based flexible MIMO turbo-equalizer. RSP 2014: 16-21 - 2013
- [c41]Purushotham Murugappa, Amer Baghdadi, Michel Jézéquel:
Parameterized area-efficient multi-standard turbo decoder. DATE 2013: 109-114 - [c40]Mostafa Rizk, Amer Baghdadi, Michel Jézéquel, Yasser Mohana, Youssef Atat:
Statically-scheduled application-specific processor design: a case-study on MMSE MIMO equalization. DATE 2013: 677-680 - [c39]Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Michael Hübner, Jean-Philippe Diguet:
Stopping-Free Dynamic Configuration of a Multi-ASIP Turbo Decoder. DSD 2013: 155-162 - [c38]Carlo Condo, Amer Baghdadi, Guido Masera:
A Joint Communication and Application Simulator for NoC-Based Custom SoCs: LDPC and Turbo Codes Parallel Decoding Case Study. DSD 2013: 168-174 - [c37]Mostafa Rizk, Amer Baghdadi, Michel Jézéquel, Yasser Mohanna, Youssef Atat:
Flexible and efficient architecture design for MIMO MMSE-IC linear turbo-equalization. ICCIT 2013: 340-344 - [c36]Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Jean-Philippe Diguet, Jean-Noel Bazin, Michael Hübner:
Optimizations for an efficient reconfiguration of an ASIP-based turbo decoder. ISCAS 2013: 493-496 - [c35]Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Jean-Philippe Diguet, Jean-Noel Bazin, Michael Hübner:
A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIP context. ISVLSI 2013: 40-45 - [c34]Vianney Lapotre, Michael Hübner, Guy Gogniat, Purushotham Murugappa, Amer Baghdadi, Jean-Philippe Diguet:
An efficient on-chip configuration infrastructure for a flexible multi-ASIP turbo decoder architecture. ReCoSoC 2013: 1-8 - [c33]Purushotham Murugappa, Vianney Lapotre, Amer Baghdadi, Michel Jézéquel:
Rapid design and prototyping of a reconfigurable decoder architecture for QC-LDPC codes. RSP 2013: 87-93 - 2012
- [j13]Salim Haddad, Amer Baghdadi, Michel Jézéquel:
Complexity adaptive iterative receiver performing TBICM-ID-SSD. EURASIP J. Adv. Signal Process. 2012: 131 (2012) - [j12]Salim Haddad, Amer Baghdadi, Michel Jézéquel:
On the Convergence Speed of Turbo Demodulation With Turbo Decoding. IEEE Trans. Signal Process. 60(8): 4452-4458 (2012) - [j11]Guido Masera, Amer Baghdadi, Frank Kienle, Christophe Moy:
Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation. VLSI Design 2012: 549768:1-549768:2 (2012) - [c32]Salim Haddad, Oscar Sanchez, Amer Baghdadi, Michel Jézéquel:
Complexity reduction of shuffled parallel iterative demodulation with turbo decoding. ICT 2012: 1-6 - [c31]Rachid Al-Khayat, Amer Baghdadi, Michel Jézéquel:
Architecture efficiency of application-specific processors: A 170Mbit/s 0.644mm2 multi-standard turbo decoder. ISSoC 2012: 1-7 - [c30]Salim Haddad, Amer Baghdadi, Michel Jézéquel:
Adaptive complexity MIMO turbo receiver applying turbo demodulation. ISTC 2012: 235-239 - [c29]Vianney Lapotre, Guy Gogniat, Jean-Philippe Diguet, Salim Haddad, Amer Baghdadi:
An analytical approach for sizing of heterogeneous multiprocessor flexible platforms for iterative demapping and channel decoding. ReConFig 2012: 1-6 - [c28]Purushotham Murugappa, Jean-Noel Bazin, Amer Baghdadi, Michel Jézéquel:
FPGA prototyping and performance evaluation of multi-standard Turbo/LDPC Encoding and Decoding. RSP 2012: 143-148 - [i1]Salim Haddad, Amer Baghdadi, Michel Jézéquel:
On the Convergence Speed of Turbo Demodulation with Turbo Decoding. CoRR abs/1203.5037 (2012) - 2011
- [j10]Atif Raza Jafri, Amer Baghdadi, Michel Jézéquel:
Parallel MIMO Turbo Equalization. IEEE Commun. Lett. 15(3): 290-292 (2011) - [j9]Maurizio Martina, Guido Masera, Hazem Moussa, Amer Baghdadi:
On chip interconnects for multiprocessor turbo decoding architectures. Microprocess. Microsystems 35(2): 167-181 (2011) - [c27]Purushotham Murugappa, Rachid Al-Khayat, Amer Baghdadi, Michel Jézéquel:
A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding. DATE 2011: 228-233 - [c26]Pallavi Reddy, Fabien Clermidy, Amer Baghdadi, Michel Jézéquel:
A low complexity stopping criterion for reducing power consumption in turbo decoders. DATE 2011: 649-654 - [c25]Rachid Al-Khayat, Purushotham Murugappa, Amer Baghdadi, Michel Jézéquel:
Area and throughput optimized ASIP for multi-standard turbo decoding. International Symposium on Rapid System Prototyping 2011: 79-84 - [c24]Salim Haddad, Amer Baghdadi, Michel Jézéquel:
Reducing the number of iterations in iterative demodulation with turbo decoding. SoftCOM 2011: 1-6 - 2010
- [j8]Olivier Muller, Amer Baghdadi, Michel Jézéquel:
Parallelism Efficiency in Convolutional Turbo Decoding. EURASIP J. Adv. Signal Process. 2010 (2010) - [c23]Atif Raza Jafri, Amer Baghdadi, Michel Jézéquel:
Rapid design and prototyping of universal soft demapper. ISCAS 2010: 3769-3772 - [c22]Pallavi Reddy, Fabien Clermidy, Rasheed Al Khayat, Amer Baghdadi, Michel Jézéquel:
Power consumption analysis and energy efficient optimization for turbo decoder implementation. SoC 2010: 12-17
2000 – 2009
- 2009
- [j7]Atif Raza Jafri, Amer Baghdadi, Michel Jézéquel:
ASIP-Based Universal Demapper for Multiwireless Standards. IEEE Embed. Syst. Lett. 1(1): 9-13 (2009) - [j6]Olivier Muller, Amer Baghdadi, Michel Jézéquel:
From Parallelism Levels to a Multi-ASIP Architecture for Turbo Decoding. IEEE Trans. Very Large Scale Integr. Syst. 17(1): 92-102 (2009) - [c21]Atif Raza Jafri, Daoud Karakolah, Amer Baghdadi, Michel Jézéquel:
ASIP-based flexible MMSE-IC Linear Equalizer for MIMO turbo-equalization applications. DATE 2009: 1620-1625 - [c20]Fabrizio Vacca, Guido Masera, Hazem Moussa, Amer Baghdadi, Michel Jézéquel:
Flexible Architectures for LDPC Decoders Based on Network on Chip Paradigm. DSD 2009: 582-589 - [c19]Chafic Jaber, Andreas Kanstein, Ludovic Apvrille, Amer Baghdadi, Patricia Le Moenner, Renaud Pacalet:
High-Level System Modeling for Rapid HW/SW Architecture Exploration. IEEE International Workshop on Rapid System Prototyping 2009: 88-94 - [c18]Atif Raza Jafri, Amer Baghdadi, Michel Jézéquel:
Rapid Prototyping of ASIP-based Flexible MMSE-IC Linear Equalizer. IEEE International Workshop on Rapid System Prototyping 2009: 130-133 - [c17]Jean Saad, Amer Baghdadi, Frantz Bodereau:
FPGA-based Radar Signal Processing for Automotive Driver Assistance System. IEEE International Workshop on Rapid System Prototyping 2009: 196-199 - 2008
- [c16]Hazem Moussa, Amer Baghdadi, Michel Jézéquel:
Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder. DAC 2008: 429-434 - [c15]Hazem Moussa, Amer Baghdadi, Michel Jézéquel:
Binary de Bruijn interconnection network for a flexible LDPC/turbo decoder. ISCAS 2008: 97-100 - [c14]Olivier Muller, Amer Baghdadi, Michel Jézéquel:
From Application to ASIP-based FPGA Prototype: a Case Study on Turbo Decoding. IEEE International Workshop on Rapid System Prototyping 2008: 128-134 - 2007
- [c13]Hazem Moussa, Olivier Muller, Amer Baghdadi, Michel Jézéquel:
Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding. DATE 2007: 654-659 - 2006
- [c12]Olivier Muller, Amer Baghdadi, Michel Jézéquel:
ASIP-based multiprocessor SoC design for simple and double binary turbo decoding. DATE 2006: 1330-1335 - [c11]Olivier Muller, Amer Baghdadi, Michel Jézéquel:
On the Parallelism of Convolutional Turbo Decoding and Interleaving Interference. GLOBECOM 2006 - 2005
- [j5]Nacer-Eddine Zergainoh, Amer Baghdadi, Ahmed Amine Jerraya:
Hardware/software codesign of on-chip communication architecture for application-specific multiprocessor system-on-chip. Int. J. Embed. Syst. 1(1/2): 112-124 (2005) - 2004
- [j4]Nacer-Eddine Zergainoh, Amer Baghdadi, Ahmed Amine Jerraya:
A generic architecture model based-methodology for an efficient design of hardware/software application-specific multiprocessor System-on-Chip. Ann. des Télécommunications 59(7-8): 784-806 (2004) - [c10]Sang-Il Han, Amer Baghdadi, Marius Bonaciu, Soo-Ik Chae, Ahmed Amine Jerraya:
An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory. DAC 2004: 250-255 - [c9]Ferid Gharsalli, Amer Baghdadi, Marius Bonaciu, Giedrius Majauskas, Wander O. Cesário, Ahmed Amine Jerraya:
An Efficient Architecture for the Implementation of Message Passing Programming Model on Massive Multiprocessor. IEEE International Workshop on Rapid System Prototyping 2004: 80-87 - 2003
- [j3]Arif Sasongko, Amer Baghdadi, Frédéric Rousseau, Ahmed Amine Jerraya:
Towards SoC Validation Through Prototyping: A Systematic Approach Based on Reconfigurable Platform. Des. Autom. Embed. Syst. 8(2-3): 155-171 (2003) - [c8]Arif Sasongko, Amer Baghdadi, Frédéric Rousseau, Ahmed Amine Jerraya:
Embedded Application Prototyping on a Communication-Restricted Reconfigurable. IEEE International Workshop on Rapid System Prototyping 2003: 33-39 - 2002
- [b1]Amer Baghdadi:
Exploration et conception systématique d'architectures multiprocesseurs monopuces dédiées à des applications spécifiques = methods and tools for multiprocessor systems on chip, hardware/software co-designExploration and Systematic Design of Application-Specific Heterogeneous Multiprocessor SoC. (Exploration and Systematic Design of Application-Specific Heterogeneous Multiprocessor SoC). Grenoble Institute of Technology, France, 2002 - [j2]Amer Baghdadi, Nacer-Eddine Zergainoh, Wander O. Cesário, Ahmed Amine Jerraya:
Combining a Performance Estimation Methodology with a Hardware/Software Codesign Flow Supporting Multiprocessor Systems. IEEE Trans. Software Eng. 28(9): 822-831 (2002) - [j1]Amer Baghdadi, Nacer-Eddine Zergainoh, Wander O. Cesário, Ahmed Amine Jerraya:
Exploration de l'espace des solutions architecturales dans le codesign. Tech. Sci. Informatiques 21(1): 9-35 (2002) - [c7]Wander O. Cesário, Amer Baghdadi, Lovic Gauthier, Damien Lyonnard, Gabriela Nicolescu, Yanick Paviot, Sungjoo Yoo, Ahmed Amine Jerraya, Mario Diaz-Nava:
Component-based design approach for multicore SoCs. DAC 2002: 789-794 - 2001
- [c6]Sungjoo Yoo, Gabriela Nicolescu, Damien Lyonnard, Amer Baghdadi, Ahmed Amine Jerraya:
A generic wrapper architecture for multi-processor SoC cosimulation and design. CODES 2001: 195-200 - [c5]Damien Lyonnard, Sungjoo Yoo, Amer Baghdadi, Ahmed Amine Jerraya:
Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip. DAC 2001: 518-523 - [c4]Amer Baghdadi, Damien Lyonnard, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya:
An efficient architecture model for systematic design of application-specific multiprocessor SoC. DATE 2001: 55-63 - 2000
- [c3]Amer Baghdadi, Nacer-Eddine Zergainoh, Damien Lyonnard, Ahmed Amine Jerraya:
Generic Architecture Platform for Multiprocessor System-On-Chip Design. DIPES 2000: 53-64 - [c2]Nacer-Eddine Zergainoh, Amer Baghdadi, Ludovic Tambour, Damien Lyonnard, Lovic Gauthier, Ahmed Amine Jerraya:
Framework for System Design, Validation and Fast Prototyping of Multiprocessor System-On-Chip. DIPES 2000: 99-110 - [c1]Amer Baghdadi, Nacer-Eddine Zergainoh, Wander O. Cesário, T. Roudier, Ahmed Amine Jerraya:
Design Space Exploration for Hardware/Software Codesign of Multiprocessor Systems. IEEE International Workshop on Rapid System Prototyping 2000: 8-13
Coauthor Index
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