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2020 – today
- 2023
[j24]Kang Zhao
, Yuchun Ma, Ruining He, Jixing Zhang, Ning Xu, Jinian Bian:
Adaptive Selection and Clustering of Partial Reconfiguration Modules for Modern FPGA Design Flow. ACM Trans. Reconfigurable Technol. Syst. 16(2): 27:1-27:24 (2023)- 2022
- [j23]Lijia Ma, Yuchun Ma, Qiuzhen Lin, Junkai Ji, Carlos A. Coello Coello, Maoguo Gong:
SNEGAN: Signed Network Embedding by Using Generative Adversarial Nets. IEEE Trans. Emerg. Top. Comput. Intell. 6(1): 136-149 (2022)
2010 – 2019
- 2019
- [c67]Yihui He, Xianggen Liu, Huasong Zhong, Yuchun Ma:
AddressNet: Shift-Based Primitives for Efficient Convolutional Neural Networks. WACV 2019: 1213-1222 - 2018
- [c66]Teng Yu, Bo Feng, Mark Stillwell, Liucheng Guo, Yuchun Ma, John Thomson:
Lattice-Based Scheduling for Multi-FPGA Systems. FPT 2018: 318-321 - [i2]Huasong Zhong, Xianggen Liu, Yihui He, Yuchun Ma:
Shift-based Primitives for Efficient Convolutional Neural Networks. CoRR abs/1809.08458 (2018) - 2017
- [j22]Fei Yang, Yuchun Ma, Jin Hou, Ning Xu:
基于MPSoC并行调度的矩阵乘法加速算法研究 (Research on Acceleration of Matrix Multiplication Based on Parallel Scheduling on MPSoC). 计算机科学 44(8): 36-41 (2017) - [c65]Lin Ma, Yuchun Ma:
Intelligent Composition of Test Papers based on MOOC Learning Data. EDM 2017 - 2016
- [c64]Wenlai Zhao, Haohuan Fu, Wayne Luk, Teng Yu, Shaojun Wang, Bo Feng, Yuchun Ma, Guangwen Yang:
F-CNN: An FPGA-based framework for training Convolutional Neural Networks. ASAP 2016: 107-114 - [c63]Teng Yu, Bo Feng, Mark Stillwell, José Gabriel F. Coutinho, Wenlai Zhao, Shuang Liang, Wayne Luk, Alexander L. Wolf, Yuchun Ma:
Relation-oriented resource allocation for multi-accelerator systems. ASAP 2016: 243-244 - [c62]Fubing Mao, Wei Zhang, Bo Feng, Bingsheng He, Yuchun Ma:
Modular Placement for Interposer based Multi-FPGA Systems. ACM Great Lakes Symposium on VLSI 2016: 93-98 - 2015
- [j21]Wulong Liu, Yu Wang, Guoqing Chen, Yuchun Ma, Yuan Xie, Huazhong Yang:
Whitespace-Aware TSV Arrangement in 3-D Clock Tree Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 23(9): 1842-1853 (2015) - [j20]Yu Wang, Song Yao, Shuai Tao, Xiaoming Chen, Yuchun Ma, Yiyu Shi, Huazhong Yang:
HS3-DPG: Hierarchical Simulation for 3-D P/G Network. IEEE Trans. Very Large Scale Integr. Syst. 23(10): 2307-2311 (2015) - [c61]Chao Zhang, Yuchun Ma, Wayne Luk:
HW/SW Partitioning Algorithm Targeting MPSOC with Dynamic Partial Reconfigurable Fabric. CAD/Graphics 2015: 240-241 - 2014
- [j19]Wulong Liu, Yu Wang, Yuchun Ma, Yuan Xie, Huazhong Yang:
On-Chip Hybrid Power Supply System for Wireless Sensor Nodes. ACM J. Emerg. Technol. Comput. Syst. 10(3): 23:1-23:22 (2014) - [c60]Wenqiang Wang, Kaiyuan Guo, Mengyuan Gu, Yuchun Ma, Yu Wang:
A universal FPGA-based floating-point matrix processor for mobile systems. FPT 2014: 139-146 - [c59]Yuchun Ma, Jinglan Liu, Chao Zhang, Wayne Luk:
HW/SW partitioning for region-based dynamic partial reconfigurable FPGAs. ICCD 2014: 470-476 - [c58]Song Yao, Xiaoming Chen, Yu Wang, Yuchun Ma, Yuan Xie, Huazhong Yang:
Efficient region-aware P/G TSV planning for 3D ICs. ISQED 2014: 171-178 - [e1]Jialin Chen, Wenbo Yin, Yuichiro Shibata, Lingli Wang, Hayden Kwok-Hay So, Yuchun Ma:
2014 International Conference on Field-Programmable Technology, FPT 2014, Shanghai, China, December 10-12, 2014. IEEE 2014, ISBN 978-1-4799-6245-7 [contents] - [i1]Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto:
Network flow-based simultaneous retiming and slack budgeting for low power design. CoRR abs/1402.2460 (2014) - 2013
- [j18]Xiaoming Chen, Hong Luo, Yu Wang, Yu Cao, Yuan Xie, Yuchun Ma, Huazhong Yang:
Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits. IET Circuits Devices Syst. 7(5): 273-282 (2013) - [j17]Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yuan Xie, Tingting Huang:
Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs. Integr. 46(1): 1-9 (2013) - [j16]Ruining He, Guoqiang Liang, Yuchun Ma, Yu Wang, Jinian Bian:
Unification of PR Region floorplanning and Fine-Grained Placement for Dynamic Partially Reconfigurable FPGAs. J. Circuits Syst. Comput. 22(4) (2013) - [j15]Ning Xu, Yuchun Ma, Jia Liu, Shou-Chun Tao:
Thermal-Aware Post Layout Voltage-Island Generation for 3D ICs. J. Comput. Sci. Technol. 28(4): 671-681 (2013) - [c57]Yuanyuan Li, Ning Xu, Yuchun Ma, Jinian Bian:
Incremental 3D NoC synthesis based on physical-aware router merging algorithm. ASICON 2013: 1-4 - [c56]Jixin Zhang, Ning Xu, Yuchun Ma, Yu Wang, Jinian Bian:
Data dependency aware prefetch scheduling for Dynamic Partial reconfigurable designs. ASICON 2013: 1-4 - [c55]Shuai Tao, Xiaoming Chen, Yu Wang, Yuchun Ma, Yiyu Shi, Hui Wang, Huazhong Yang:
HS3DPG: Hierarchical simulation for 3D P/G network. ASP-DAC 2013: 509-514 - [c54]Zhongda Yuan, Yuchun Ma, Jinian Bian, Kang Zhao:
Automatic enhanced CDFG generation based on runtime instrumentation. CSCWD 2013: 92-97 - [c53]Guoqiang Liang, Yuchun Ma, Kang Zhao, Jinian Bian:
Efficient custom instruction generation based on characterizing of basic blocks. CSCWD 2013: 98-103 - [c52]Wulong Liu, Haixiao Du, Yu Wang, Yuchun Ma, Yuan Xie, Jinguo Quan, Huazhong Yang:
TSV-aware topology generation for 3D Clock Tree Synthesis. ISQED 2013: 300-307 - [c51]Xin Li, Wulong Liu, Haixiao Du, Yu Wang, Yuchun Ma, Huazhong Yang:
Whitespace-aware TSV arrangement in 3D clock tree synthesis. ISVLSI 2013: 115-120 - [c50]Qingyu Liu, Yuchun Ma, Yu Wang, Wayne Luk, Jinian Bian:
RALP: Reconvergence-aware layer partitioning for 3D FPGAs. ReConFig 2013: 1-6 - 2012
- [j14]Xiaoming Chen, Yu Wang, Yu Cao, Yuchun Ma, Huazhong Yang:
Variation-Aware Supply Voltage Assignment for Simultaneous Power and Aging Optimization. IEEE Trans. Very Large Scale Integr. Syst. 20(11): 2143-2147 (2012) - [c49]Ruining He, Guoqiang Liang, Yuchun Ma, Yu Wang, Jinian Bian:
PDPR: Fine-Grained Placement for Dynamic Partially Reconfigurable FPGAs. ARC 2012: 350-356 - [c48]Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yu Wang, Tingting Huang, Yuan Xie:
Thermal-aware power network design for IR drop reduction in 3D ICs. ASP-DAC 2012: 47-52 - [c47]Ruining He, Yuchun Ma, Kang Zhao, Jinian Bian:
ISBA: An independent set-based algorithm for automated partial reconfiguration module generation. ICCAD 2012: 500-507 - [c46]Zhongda Yuan, Yuchun Ma, Jinian Bian:
SMPP: Generic SAT Solver over Reconfigurable Hardware Accelerator. IPDPS Workshops 2012: 443-448 - [c45]Kan Wang, Sheqin Dong, Yuchun Ma, Satoshi Goto, Jason Cong:
Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs. ISQED 2012: 129-136 - [c44]Hong Luo, Yu Wang, Yu Cao, Yuan Xie, Yuchun Ma, Huazhong Yang:
Temporal Performance Degradation under RTN: Evaluation and Mitigation for Nanoscale Circuits. ISVLSI 2012: 183-188 - 2011
- [j13]Kan Wang, Sheqin Dong, Yuchun Ma, Yu Wang, Xianlong Hong, Jason Cong:
Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2490-2498 (2011) - [c43]Jia Liu, Yuchun Ma, Ning Xu, Yu Wang:
Incremental layout optimization for NoC designs based on MILP formulation. ASICON 2011: 357-360 - [c42]Wulong Liu, Yu Wang, Wei Liu, Yuchun Ma, Yuan Xie, Huazhong Yang:
On-chip hybrid power supply system for wireless sensor nodes. ASP-DAC 2011: 43-48 - [c41]Kan Wang, Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong, Jason Cong:
Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs. ASP-DAC 2011: 261-266 - [c40]Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto:
Network flow-based simultaneous retiming and slack budgeting for low power design. ASP-DAC 2011: 473-478 - [c39]Binjie Song, Shan Zeng, Yuchun Ma, Ning Xu, Yu Wang:
Tree-Based Partitioning Approach for Network-on-Chip Synthesis. CAD/Graphics 2011: 465-470 - [c38]Hong Luo, Xiaoming Chen, Jyothi Velamala, Yu Wang, Yu Cao, Vikas Chandra, Yuchun Ma, Huazhong Yang:
Circuit-level delay modeling considering both TDDB and NBTI. ISQED 2011: 14-21 - [c37]Tao Lin, Sheqin Dong, Song Chen, Yuchun Ma, Ou He, Satoshi Goto:
Novel and efficient min cut based voltage assignment in gate level. ISQED 2011: 150-155 - 2010
- [j12]Xu He, Sheqin Dong, Yuchun Ma:
Signal through-the-silicon via planning and pin assignment for thermal and wire length optimization in 3D ICs. Integr. 43(4): 342-352 (2010) - [j11]Yuchun Ma, Qiang Zhou, Pingqiang Zhou, Xianlong Hong:
Thermal Impacts of Leakage Power in 2D/3D floorplanning. J. Circuits Syst. Comput. 19(7): 1483-1495 (2010) - [c36]Shenghua Liu, Yuchun Ma, Xianlong Hong, Yu Wang:
Simultaneous slack budgeting and retiming for synchronous circuits optimization. ASP-DAC 2010: 49-54 - [c35]Li Li, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong:
PS-FPG: pattern selection based co-design of floorplan and power/ground network with wiring resource optimization. ASP-DAC 2010: 769-774
2000 – 2009
- 2009
- [j10]Yuchun Ma, Xin Li, Yu Wang, Xianlong Hong:
Thermal-Aware Incremental Floorplanning for 3D ICs Based on MILP Formulation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 2979-2989 (2009) - [c34]Xin Li, Yuchun Ma, Xianlong Hong:
A novel thermal optimization flow using incremental floorplanning for 3D ICs. ASP-DAC 2009: 347-352 - [c33]Fubing Mao, Yuchun Ma, Ning Xu, Xianlong Hong, Yu Wang:
Multi-objective Floorplanning Based on Fuzzy Logic. FSKD (4) 2009: 331-335 - [c32]Xiaoming Chen, Yu Wang, Yu Cao, Yuchun Ma, Huazhong Yang:
Variation-aware supply voltage assignment for minimizing circuit degradation and leakage. ISLPED 2009: 39-44 - [c31]Yuchun Ma, Xiang Qiu, Xiangqing He, Xianlong Hong:
Incremental power optimization for multiple supply voltage design. ISQED 2009: 280-286 - [c30]Xu He, Sheqin Dong, Yuchun Ma, Xianlong Hong:
Simultaneous buffer and interlayer via planning for 3D floorplanning. ISQED 2009: 740-745 - [c29]Li Li, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong:
Modern Floorplanning with Boundary Clustering Constraint. ISVLSI 2009: 79-84 - 2008
- [j9]Yuchun Ma, Yongxiang Liu, Eren Kursun, Glenn Reinman, Jason Cong:
Investigating the effects of fine-grain three-dimensional integration on microarchitecture design. ACM J. Emerg. Technol. Comput. Syst. 4(4): 17:1-17:30 (2008) - [c28]Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jason Cong:
LP based white space redistribution for thermal via planning and performance optimization in 3D ICs. ASP-DAC 2008: 209-212 - [c27]Jiemin Liu, Yuchun Ma, Yuan Gao:
MRAPF: Minimum RTT Asymmetric-Path First for Mobile Multi-homed End-to-End Transfer. FSKD (4) 2008: 86-90 - [c26]Xiang Qiu, Yuchun Ma, Xiangqing He, Xianlong Hong:
IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power Optimization. ISQED 2008: 873-876 - 2007
- [c25]Jiayi Liu, Sheqin Dong, Yuchun Ma, Di Long, Xianlong Hong:
Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation. ASP-DAC 2007: 191-196 - [c24]Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou:
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. ASP-DAC 2007: 920-925 - [c23]Pingqiang Zhou, Yuchun Ma, Qiang Zhou, Xianlong Hong:
Thermal Effects with Leakage Power Considered in 2D/3D Floorplanning. CAD/Graphics 2007: 338-343 - [c22]Ou He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong:
An effective buffer planning algorithm for IP based fixed-outline SOC placement. ACM Great Lakes Symposium on VLSI 2007: 564-569 - [c21]Pingqiang Zhou, Yuchun Ma, Zhuoyuan Li, Robert P. Dick, Li Shang, Hai Zhou, Xianlong Hong, Qiang Zhou:
3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits. ICCAD 2007: 590-597 - [c20]Yongxiang Liu, Yuchun Ma, Eren Kursun, Glenn Reinman, Jason Cong:
Fine grain 3D integration for microarchitecture design through cube packing exploration. ICCD 2007: 259-266 - [c19]Lingyi Zhang, Sheqin Dong, Xianlong Hong, Yuchun Ma:
A Fast 3D-BSG Algorithm for 3D Packing Problem. ISCAS 2007: 2044-2047 - [c18]Liu Yang, Sheqin Dong, Yuchun Ma, Xianlong Hong:
Interconnect Power Optimization Based on Timing Analysis. ISVLSI 2007: 119-124 - [c17]Yaoguang Wei, Sheqin Dong, Xianlong Hong, Yuchun Ma:
An accurate and efficient probabilistic congestion estimation model in x architecture. SLIP 2007: 25-32 - 2006
- [j8]Yuchun Ma, Xianlong Hong, Sheqin Dong, Chung-Kuan Cheng, Jun Gu:
General Floorplans with L/T-Shaped Blocks Using Corner Block List. J. Comput. Sci. Technol. 21(6): 922-926 (2006) - [j7]Song Chen, Sheqin Dong, Xianlong Hong, Yuchun Ma, Chung-Kuan Cheng:
VLSI Block Placement With Alignment Constraints. IEEE Trans. Circuits Syst. II Express Briefs 53-II(8): 622-626 (2006) - [c16]Liu Yang, Sheqin Dong, Xianlong Hong, Yuchun Ma:
A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints. APCCAS 2006: 792-795 - [c15]Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Reinman, Jie Wei, Yan Zhang:
An automated design flow for 3D microarchitecture evaluation. ASP-DAC 2006: 384-389 - 2005
- [j6]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng, Jun Gu:
Buffer planning as an Integral part of floorplanning with consideration of routing congestion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4): 609-621 (2005) - [c14]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng:
Performance constrained floorplanning based on partial clustering [IC layout]. ISCAS (2) 2005: 1863-1866 - [c13]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng:
VLSI block placement with alignment constraints based on corner block list. ISCAS (6) 2005: 6222-6225 - [c12]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng:
Buffer Planning Algorithm Based on Partial Clustered Floorplanning. ISQED 2005: 213-219 - [c11]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng:
Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning. ISQED 2005: 628-633 - 2004
- [j5]Xianlong Hong, Yuchun Ma, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Corner block list representation and its application with boundary constraints. Sci. China Ser. F Inf. Sci. 47(1): 1-19 (2004) - [j4]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu:
A buffer planning algorithm for chip-level floorplanning. Sci. China Ser. F Inf. Sci. 47(6): 763-776 (2004) - [j3]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng, Jun Gu:
Fast Evaluation of Bounded Slice-Line Grid. J. Comput. Sci. Technol. 19(6): 973-980 (2004) - [j2]Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Stairway compaction using corner block list and its applications with rectilinear blocks. ACM Trans. Design Autom. Electr. Syst. 9(2): 199-211 (2004) - [c10]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu:
A buffer planning algorithm with congestion optimization. ASP-DAC 2004: 615-620 - [c9]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Buffer allocation algorithm with consideration of routing congestion. ASP-DAC 2004: 621-623 - 2003
- [c8]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu:
A buffer planning algorithm based on dead space redistribution. ASP-DAC 2003: 435-438 - [c7]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Dynamic global buffer planning optimization based on detail block locating and congestion analysis. DAC 2003: 806-811 - [c6]Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Song Chen, Chung-Kuan Cheng, Jun Gu:
Arbitrary convex and concave rectilinear block packing based on corner block list. ISCAS (5) 2003: 493-496 - [c5]Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Evaluating a bounded slice-line grid assignment in O(nlogn) time. ISCAS (4) 2003: 708-711 - [c4]Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu:
An integrated floorplanning with an efficient buffer planning algorithm. ISPD 2003: 136-142 - 2002
- [c3]Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks. ASP-DAC/VLSI Design 2002: 387-392 - 2001
- [j1]Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Floorplanning with abutment constraints based on corner block list. Integr. 31(1): 65-77 (2001) - [c2]Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
VLSI floorplanning with boundary constraints based on corner block list. ASP-DAC 2001: 509-514 - [c1]Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List. DAC 2001: 770-775
Coauthor Index
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