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Tse-Yu Yeh
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2010 – 2019
- 2016
- [j4]Onur Mutlu, Rich Belgard, Thomas R. Gross, Norman P. Jouppi, John L. Hennessy, Steven A. Przybylski, Chris Rowen, Yale N. Patt, Wen-mei W. Hwu, Stephen W. Melvin, Michael Shebanow, Tse-Yu Yeh, Andy Wolfe:
Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor. IEEE Micro 36(4): 70-85 (2016) - 2014
- [c12]Tse-Yu Yeh, Deborah T. Marr, Yale N. Patt:
Author retrospective for increasing the instruction fetch rate via multiple branch prediction and a branch address cache. ICS 25th Anniversary 2014: 24-25
2000 – 2009
- 2007
- [j3]Tse-Yu Yeh:
Low-Power, High-Performance Architecture of the PWRficient Processor Family. IEEE Micro 27(2): 69-78 (2007) - 2006
- [c11]Tse-Yu Yeh:
Low-power, high-performance architecture of the PWRficient processor family. Hot Chips Symposium 2006: 1-29 - 2001
- [j2]Marius Evers, Tse-Yu Yeh:
Understanding branches and designing branch predictors for high-performance microprocessors. Proc. IEEE 89(11): 1610-1620 (2001)
1990 – 1999
- 1998
- [c10]Tse-Yu Yeh, Yale N. Patt:
Retrospective: Alternative Implementations of Two-Level Adaptive Training Branch Prediction. 25 Years ISCA: Retrospectives and Reprints 1998: 87-88 - [c9]Tse-Yu Yeh, Yale N. Patt:
Alternative Implementations of Two-Level Adaptive Branch Prediction. 25 Years ISCA: Retrospectives and Reprints 1998: 451-461 - 1996
- [j1]Po-Yung Chang, Eric Hao, Tse-Yu Yeh, Yale N. Patt:
Branch Classification: New Mechanism for Improving Branch Predictor Performance. Int. J. Parallel Program. 24(2): 133-158 (1996) - 1994
- [c8]Po-Yung Chang, Eric Hao, Tse-Yu Yeh, Yale N. Patt:
Branch classification: a new mechanism for improving branch predictor performance. MICRO 1994: 22-31 - 1993
- [b1]Tse-Yu Yeh:
Two-level adaptive branch prediction and instruction fetch mechanisms for high performance superscalar processors. University of Michigan, USA, 1993 - [c7]Tse-Yu Yeh, Deborah T. Marr, Yale N. Patt:
Increasing the Instruction Fetch Rate via Multiple Branch Prediction and a Branch Address Cache. International Conference on Supercomputing 1993: 67-76 - [c6]Tse-Yu Yeh, Yale N. Patt:
A Comparison of Dynamic Branch Predictors that Use Two Levels of Branch History. ISCA 1993: 257-266 - [c5]Tse-Yu Yeh, Yale N. Patt:
Branch history table indexing to prevent pipeline bubbles in wide-issue superscalar processors. MICRO 1993: 164-175 - 1992
- [c4]Tse-Yu Yeh, Yale N. Patt:
Alternative Implementations of Two-Level Adaptive Branch Prediction. ISCA 1992: 124-134 - [c3]Tse-Yu Yeh, Yale N. Patt:
A comprehensive instruction fetch mechanism for a processor supporting speculative execution. MICRO 1992: 129-139 - 1991
- [c2]Michael Butler, Tse-Yu Yeh, Yale N. Patt, Mitch Alsup, Hunter Scales, Michael Shebanow:
Single Instruction Stream Parallelism is Greater Than Two. ISCA 1991: 276-286 - [c1]Tse-Yu Yeh, Yale N. Patt:
Two-Level Adaptive Training Branch Prediction. MICRO 1991: 51-61
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