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Li Zhao 0002
Person information
- affiliation: Intel Corporation, Hillsboro, OR, USA
- affiliation (PhD): University of California, Riverside, CA, USA
Other persons with the same name
- Li Zhao — disambiguation page
- Li Zhao 0001 — Children's National Medical Center, Washington, DC, USA (and 2 more)
- Li Zhao 0003 — Southeast University, School of Information Science and Engineering, MOE Key Laboratory of Underwater Acoustic Signal Processing, Nanjing, China (and 1 more)
- Li Zhao 0004 — Western Sydney University, School of Business, Penrith, NSW, Australia
- Li Zhao 0005 — Wenzhou University, Zhejiang, China
- Li Zhao 0006 — Tsinghua University, Department of Computer Science and Technology, China
- Li Zhao 0007 — Microsoft Research Asia, Beijing, China (and 1 more)
- Li Zhao 0008 — Fudan University, Shanghai Institute for Advanced Communication and Data Science, Shanghai, China (and 1 more)
- Li Zhao 0009 — Jiangsu University of Science and Technology, China
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2020 – today
- 2021
- [c33]Xiaowei Wang, Charles Augustine, Eriko Nurvitadhi, Ravi R. Iyer, Li Zhao, Reetuparna Das:
Cache Compression with Efficient in-SRAM Data Comparison. NAS 2021: 1-8
2010 – 2019
- 2018
- [c32]Tanay Karnik, Dileep Kurian, Paolo A. Aseron, Richard Dorrance, Erkan Alpman, Angela Nicoara, Roman Popov, Leonid Azarenkov, Mikhail J. Moiseev, Li Zhao, Santosh Ghosh, Rafael Misoczki, Ankit Gupta, M. Akhila, Sriram Muthukumar, Saurabh Bhandari, Satish Yada, Kartik Jain, Robert Flory, Chanitnan Kanthapanit, Eduardo Quijano, Bradley Jackson, Hao Luo, Suhwan Kim, Vaibhav A. Vaidya, Adel Elsherbini, Renzhi Liu, Farhana Sheikh, Omesh Tickoo, Ilya Klotchkov, Manoj R. Sastry, Sheldon Sun, Mukesh Bhartiya, Anuradha Srinivasan, Yatin Hoskote, Hong Wang, Vivek De:
A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS. ISSCC 2018: 46-48 - 2017
- [j15]Ying Zhang, Li Zhao, Ramesh Illikkal, Ravi R. Iyer, Andrew Herdrich, Lu Peng:
QoS Management on Heterogeneous Architecture for Multiprogrammed, Parallel, and Domain-Specific Applications. IEEE Syst. J. 11(4): 2096-2107 (2017) - [c31]Huaxin Li, Li Zhao, Marcio Juliato, Shabbir Ahmed, Manoj R. Sastry, Lily L. Yang:
POSTER: Intrusion Detection System for In-vehicle Networks using Sensor Correlation and Integration. CCS 2017: 2531-2533 - [c30]Santosh Ghosh, Rafael Misoczki, Li Zhao, Manoj R. Sastry:
Lightweight Block Cipher Circuits for Automotive and IoT Sensor Devices. HASP@ISCA 2017: 5:1-5:7 - 2014
- [c29]Ying Zhang, Li Zhao, Ramesh Illikkal, Ravi R. Iyer, Andrew Herdrich, Lu Peng:
QoS management on heterogeneous architecture for parallel applications. ICCD 2014: 332-339 - 2013
- [j14]Zhen Fang, Li Zhao, Xiaowei Jiang, Shih-Lien Lu, Ravi R. Iyer, Tong Li, Seung Eun Lee:
Reducing cache and TLB power by exploiting memory region and privilege level semantics. J. Syst. Archit. 59(6): 279-295 (2013) - [c28]Chuanjun Zhang, Glenn G. Ko, Jungwook Choi, Shang-nien Tsai, Minje Kim, Abner Guzmán-Rivera, Rob A. Rutenbar, Paris Smaragdis, Mi Sun Park, Vijaykrishnan Narayanan, Hongyi Xin, Onur Mutlu, Bin Li, Li Zhao, Mei Chen:
EMERALD: Characterization of emerging applications and algorithms for low-power devices. ISPASS 2013: 122-123 - 2012
- [j13]Bin Li, Li-Shiuan Peh, Li Zhao, Ravi R. Iyer:
Dynamic QoS management for chip multiprocessors. ACM Trans. Archit. Code Optim. 9(3): 17:1-17:29 (2012) - [c27]Bin Li, Zhen Fang, Li Zhao, Xiaowei Jiang, Lin Li, Andrew Herdrich, Ravishankar R. Iyer, Srihari Makineni:
Exploiting Semantics of Virtual Memory to Improve the Efficiency of the On-Chip Memory System. Euro-Par 2012: 232-245 - [c26]Nagabhushan Chitlur, Ganapati Srinivasa, Scott Hahn, P. K. Gupta, Dheeraj Reddy, David A. Koufaty, Paul Brett, Abirami Prabhakaran, Li Zhao, Nelson Ijih, Suchit Subhaschandra, Sabina Grover, Xiaowei Jiang, Ravi R. Iyer:
QuickIA: Exploring heterogeneous architectures on real prototypes. HPCA 2012: 433-440 - [c25]Zhen Fang, Li Zhao, Xiaowei Jiang, Shih-Lien Lu, Ravi R. Iyer, Tong Li, Seung Eun Lee:
Reducing L1 caches power by exploiting software semantics. ISLPED 2012: 391-396 - 2011
- [j12]Bin Li, Li Zhao, Ravi R. Iyer, Li-Shiuan Peh, Michael Leddige, Michael Espig, Seung Eun Lee, Donald Newell:
CoQoS: Coordinating QoS-aware shared resources in NoC-based SoCs. J. Parallel Distributed Comput. 71(5): 700-713 (2011) - [j11]Xiaowei Jiang, Niti Madan, Li Zhao, Mike Upton, Ravishankar R. Iyer, Srihari Makineni, Donald Newell, Yan Solihin, Rajeev Balasubramonian:
CHOP: Integrating DRAM Caches for CMP Server Platforms. IEEE Micro 31(1): 99-108 (2011) - [j10]Sadagopan Srinivasan, Li Zhao, Ramesh Illikkal, Ravishankar R. Iyer:
Efficient interaction between OS and architecture in heterogeneous platforms. ACM SIGOPS Oper. Syst. Rev. 45(1): 62-72 (2011) - [c24]Carlos Flores Fajardo, Zhen Fang, Ravi R. Iyer, German Fabila Garcia, Seung Eun Lee, Li Zhao:
Buffer-integrated-Cache: a cost-effective SRAM architecture for handheld and embedded platforms. DAC 2011: 966-971 - [c23]Xiaowei Jiang, Asit K. Mishra, Li Zhao, Ravishankar R. Iyer, Zhen Fang, Sadagopan Srinivasan, Srihari Makineni, Paul Brett, Chita R. Das:
ACCESS: Smart scheduling for asymmetric cache CMPs. HPCA 2011: 527-538 - [c22]Zhen Fang, Li Zhao, Ravishankar R. Iyer, Carlos Flores Fajardo, German Fabila Garcia, Seung Eun Lee, Bin Li, Steve R. King, Xiaowei Jiang, Srihari Makineni:
Cost-effectively offering private buffers in SoCs and CMPs. ICS 2011: 275-284 - [c21]Sadagopan Srinivasan, Ravishankar R. Iyer, Li Zhao, Ramesh Illikkal:
HeteroScouts: hardware assist for OS scheduling in heterogeneous CMPs. SIGMETRICS 2011: 149-150 - 2010
- [j9]Fei Guo, Yan Solihin, Li Zhao, Ravishankar R. Iyer:
Quality of service shared cache management in chip multiprocessor architecture. ACM Trans. Archit. Code Optim. 7(3): 14:1-14:33 (2010) - [c20]Li Zhao, Ravi R. Iyer, Srihari Makineni, Don Newell, Liqun Cheng:
NCID: a non-inclusive cache, inclusive directory architecture for flexible and efficient cache hierarchies. Conf. Computing Frontiers 2010: 121-130 - [c19]Xiaowei Jiang, Niti Madan, Li Zhao, Mike Upton, Ravishankar R. Iyer, Srihari Makineni, Donald Newell, Yan Solihin, Rajeev Balasubramonian:
CHOP: Adaptive filter-based DRAM caching for CMP server platforms. HPCA 2010: 1-12 - [c18]Sadagopan Srinivasan, Li Zhao, Lin Sun, Zhen Fang, Peng Li, Tao Wang, Ravishankar R. Iyer, Dong Liu:
Performance characterization and acceleration of Optical Character Recognition on handheld platforms. IISWC 2010: 1-10
2000 – 2009
- 2009
- [j8]Ravi R. Iyer, Ramesh Illikkal, Omesh Tickoo, Li Zhao, Padma Apparao, Don Newell:
VM3: Measuring, modeling and managing VM shared resources. Comput. Networks 53(17): 2873-2887 (2009) - [j7]Ravi R. Iyer, Ramesh Illikkal, Li Zhao, Don Newell, Jaideep Moses:
Virtual platform architectures for resource metering in datacenters. SIGMETRICS Perform. Evaluation Rev. 37(2): 89-90 (2009) - [c17]Xiaowei Jiang, Yan Solihin, Li Zhao, Ravishankar R. Iyer:
Architecture Support for Improving Bulk Memory Copying and Initialization Performance. PACT 2009: 169-180 - [c16]Ping Zhou, Bo Zhao, Yu Du, Yi Xu, Youtao Zhang, Jun Yang, Li Zhao:
Frequent value compression in packet-based NoC architectures. ASP-DAC 2009: 13-18 - [c15]Niti Madan, Li Zhao, Naveen Muralimanohar, Aniruddha N. Udipi, Rajeev Balasubramonian, Ravishankar R. Iyer, Srihari Makineni, Donald Newell:
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy. HPCA 2009: 262-274 - [c14]Tao Wang, Qigang Wang, Dong Liu, Michael Liao, Kevin Wang, Lu Cao, Li Zhao, Ravi R. Iyer, Ramesh Illikkal, John Du, Liang Wang:
Hardware/Software Co-Simulation for Last Level Cache Exploration. NAS 2009: 371-378 - 2008
- [j6]Li Zhao, Ravi R. Iyer, Mike Upton, Don Newell:
Towards hybrid last level caches for chip-multiprocessors. SIGARCH Comput. Archit. News 36(2): 56-63 (2008) - 2007
- [j5]Li Zhao, Ravi R. Iyer, Jaideep Moses, Ramesh Illikkal, Srihari Makineni, Donald Newell:
Exploring Large-Scale CMP Architectures Using ManySim. IEEE Micro 27(4): 21-33 (2007) - [j4]Fei Guo, Hari Kannan, Li Zhao, Ramesh Illikkal, Ravi R. Iyer, Don Newell, Yan Solihin, Christos Kozyrakis:
From chaos to QoS: case studies in CMP resource management. SIGARCH Comput. Archit. News 35(1): 21-30 (2007) - [j3]Li Zhao, Laxmi N. Bhuyan, Ravi R. Iyer, Srihari Makineni, Donald Newell:
Hardware Support for Accelerating Data Movement in Server Platform. IEEE Trans. Computers 56(6): 740-753 (2007) - [c13]Li Zhao, Ravi R. Iyer, Ramesh Illikkal, Jaideep Moses, Srihari Makineni, Donald Newell:
CacheScouts: Fine-Grain Monitoring of Shared Caches in CMP Platforms. PACT 2007: 339-352 - [c12]Li Zhao, Ravi R. Iyer, Srihari Makineni, Ramesh Illikkal, Jaideep Moses, Donald Newell:
Constraint-Aware Large-Scale CMP Cache Design. HiPC 2007: 161-171 - [c11]Li Zhao, Ravi R. Iyer, Ramesh Illikkal, Donald Newell:
Exploring DRAM cache architectures for CMP server platforms. ICCD 2007: 55-62 - [c10]Seongbeom Kim, Fang Liu, Yan Solihin, Ravi R. Iyer, Li Zhao, W. Cohen:
Accelerating Full-System Simulation through Characterizing and Predicting Operating System Performance. ISPASS 2007: 1-11 - [c9]Fei Guo, Yan Solihin, Li Zhao, Ravishankar R. Iyer:
A Framework for Providing Quality of Service in Chip Multi-Processors. MICRO 2007: 343-355 - [c8]Ravi R. Iyer, Li Zhao, Fei Guo, Ramesh Illikkal, Srihari Makineni, Donald Newell, Yan Solihin, Lisa R. Hsu, Steven K. Reinhardt:
QoS policies and architecture for cache/memory in CMP platforms. SIGMETRICS 2007: 25-36 - 2006
- [j2]Li Zhao, Yan Luo, Laxmi N. Bhuyan, Ravi R. Iyer:
A Network Processor-Based, Content-Aware Switch. IEEE Micro 26(3): 72-84 (2006) - [c7]Srihari Makineni, Ravishankar R. Iyer, Partha Sarangam, Donald Newell, Li Zhao, Ramesh Illikkal, Jaideep Moses:
Receive Side Coalescing for Accelerating TCP/IP Processing. HiPC 2006: 289-300 - [c6]Ravi R. Iyer, Mahesh Bhat, Li Zhao, Ramesh Illikkal, Srihari Makineni, Michael Jones, Kumar Shiv, Donald Newell:
Exploring Small-Scale and Large-Scale CMP Architectures for Commercial Java Servers. IISWC 2006: 191-200 - 2005
- [c5]Li Zhao, Yan Luo, Laxmi N. Bhuyan, Ravi R. Iyer:
SpliceNP: a TCP splicer using a network processor. ANCS 2005: 135-143 - [c4]Li Zhao, Yan Luo, Laxmi N. Bhuyan, Ravishankar R. Iyer:
Design and Implementation of a Content-Aware Switch Using a Network Processor. Hot Interconnects 2005: 79-85 - [c3]Li Zhao, Ravi R. Iyer, Srihari Makineni, Laxmi N. Bhuyan, Donald Newell:
Hardware Support for Bulk Data Movement in Server Platforms. ICCD 2005: 53-60 - [c2]Li Zhao, Ravi R. Iyer, Srihari Makineni, Laxmi N. Bhuyan:
Anatomy and Performance of SSL Processing. ISPASS 2005: 197-206 - 2004
- [j1]Yan Luo, Jun Yang, Laxmi N. Bhuyan, Li Zhao:
NePSim: A Network Processor Simulator with a Power Evaluation Framework. IEEE Micro 24(5): 34-44 (2004) - 2003
- [c1]Haiyong Xie, Li Zhao, Laxmi N. Bhuyan:
Architectural analysis and instruction-set optimization for design of network protocol processors. CODES+ISSS 2003: 225-230
Coauthor Index
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