If you are looking for the IIC-OSIC-TOOLS (the Dockerized collection of open-source IC design tools from us) then please go to https://github.com/iic-jku/iic-osic-tools!

This repo contains various tools and examples for Open-Source IC (OSIC) Design. At this point, only the open-source PDK SKY130 from SkyWater Technologies and Google is supported.

This flow is used for the digital components:

• OpenLane/OpenROAD for the digital RTL2GDS flow,
• Icarus Verilog and Verilator for linting and digital simulation, and
• GTKWave for digital waveform viewing.

The analog/full custom components use:

• Xschem for schematic capture,
• ngspice for simulation,
• gaw3 for analog waveform viewing,
• Magic for custom layout generation, DRC, extraction, PEX, and
• Netgen for netlist compare (LVS).

A viable alternative to gaw is to use Python for waveform viewing, using Spyci.

For GDS file viewing and manipulation, KLayout is used.

Use iic-osic-setup.sh to set up or update a complete analog/digital IC design environment in Ubuntu/Xubuntu. Please see the (documented) script for usage and the installed tools.

The setup script creates also an initialization script in the user's home directory. Use it to set up the environment by running

source ./iic-init.sh

Instructions for the setup of the efabless.com Caravel SoC harness can be found at https://github.com/efabless/caravel_user_project/blob/main/docs/source/roundtrip.rst.

In the directory caravel_setup, a script can be found to set up the environment variables as needed with:

source ./iic-init-caravel.sh

A fully-automatic LVS script is prepared. Run the LVS by using

./iic-lvs.sh cellname

where cellname is the name of the schematic/Verilog and layout cell. For further documentation and usage of this script please look into the file.

A fully-automatic DRC script is prepared, which can either use magic or klayout or both. Run the DRC by using

./iic-drc.sh [-m|-k|-b|-c] cellname

where cellname is the name of the layout cell. If -m is specified, then the magic DRC check is run (default); if -k is specified, then the klayout DRC check is run; if -b is selected then both magic and klayout are run. You can clean result files by running ./iic-drc.sh -c.

Note that the klayout DRC check is used by efabless for the tape-out check! The DRC style used in magic is drc(full) with euclidean turned on, which is the most suited DRC check.

A fully-automatic PEX script for parasitic extraction is prepared. Run the PEX by using

./iic-pex.sh cellname [mode]

where cellname is the name of the layout cell cellname.mag. The PEX script supports 3 different extraction modes: 1=C-decoupled, 2=C-coupled, and 3=full-RC. If the parameter mode is not supplied, then the default mode 2 (C-coupled) will be used.

The resulting SPICE netlist, including parasitic wiring components, is called cellname.pex.spice.

The various temporary and result files and outputs can be easily removed from a directory by running

./iic-clean.sh

A combination of yosys and netlistsvg (both tools are available in IIC-OSIC-TOOLS a Verilog design can be visualized as a netlist. In order to ease the use, the script iic-v2svg.sh is available. Specify an input Verilog file (input.v) and get an SVG file (output.svg) using

./iic-v2svg.sh input.v output.svg

A script is available to use KLayout for easy conversion between GDS (this file format is widespread) and OASIS (which results in much smaller filesize).

GDS to OASIS conversion:

./iic-layconv.sh input.gds output.oas

OASIS to GDS conversion, with optional zipping of output file:

./iic-layconv.sh -z input.oas output.gds

In the folder magic-cheatsheet you can find a summary of important macros, keybindings, and mouse button operations for Magic, relating to version 8.3.

In the folder example, an analog design example (an inverter in subfolder example/ana) and a simple digital design example (a counter in subfolder example/dig) are prepared for testing the environment. In the folder example/dig/rtl, the result of the digital flow OpenLane is presented, as a powered Verilog file and a layout view.

This Python script traverses through a SPICE model file, removes empty lines and comments, and extracts the specified model corner (default is tt). It further produces a flat single model file for use with e.g., ngspice.

On my Unix machine, the time to simulation (ngspice start to actual simulation start) is 80sec using the original SPICE model files from the SKY130A PDK created by open_pdks. Using this model file reducer, the ngspice startup is improved to 5sec!

This script can also be used to check the original model file, as it reports warnings when included files are not found.

Usage:

./iic-spice-model-red.py input_file [section]

It reads the input_file and writes an output file called input_file.<section>.red. If called without parameters the script displays a help screen.

Exemplary use on the SKY130A model file:

./iic-spice-model-red.py sky130.lib.spice tt

Two scripts support the usage of DFFRAM, especially when used with the IIC-OSIC-TOOLS.

With iic-dffram-install.sh [install_dir], the DFFRAM GitHub repository is cloned into install_dir (if this optional parameter is not provided, then the default dffram is used).

Using iic-dffram.sh [parameter list] provides a wrapper script to set a few parameters correctly (running iic-dffram.sh without parameters displays the help screen).

Here is an example of creating a 32b-wide RAM with 32 entries:

iic-dffram-install.sh test1
cd test1
iic-dffram.sh -s 32x32

The wrapper script gds3d.sh is provided to simplify the usage of GDS3D, which is part of the IIC-OSIC-TOOLS collection.

Usage for 3D-viewing a GDS layout in SKY130 technology (gds3d.sh -h shows available options):

gds3d.sh -i file.gds

Two scripts support the usage of CHIP_ART, especially when used with the IIC-OSIC-TOOLS.

With iic-chipart-install.sh [install_dir], the CHIP_ART GitHub repository is cloned into install_dir (if this optional parameter is not provided, then the default chip_art is used).

Using iic-chipart.sh [parameter list] provides a wrapper script to set a few parameters correctly (running iic-chipart.sh without parameters displays the help screen).

Here is an example of creating a GDS from the provided example (chip_art.png):

iic-chipart-install.sh test1
cd test1
iic-chipart.sh chip_art.png 50

The script iic-v2sch.awk is a link to Stefan Schippers' conversion script make_sky130_sch_from_verilog.awk; see xschem_sky130. It creates a symbol and schematic view for xschem from a Powered-Verilog file. The schematic can be used to run a transistor-level simulation of a Verilog design or to run an LVS on the transistor level of a synthesized digital design.

Usage:

./iic-v2sch.awk input_file.v

The input_file is the Powered-Verilog .v file. The symbol input_file.sym and the corresponding schematic input_file.sch` is then created.

The script iic-vlint.sh is created to support the linting of Verilog files using Icarus Verilog and Verilator. Executing iic-vlint.sh without input parameters brings up a help screen.

Usage:

./iic-vlint.sh input_file.v

• The LVS script needs improvement to properly work with all kinds of netlist inputs (.sch or .spice or .spc) and layout views (.mag or .gds).
• SPICE model file reducer: Add better control of output during a run, maybe add a --verbose switch.
• Inductor/trafo flow: (Semi)automatic generation of an inductor and trafo layout, extraction of a SPICE model, adaption and support in LVS and PEX
• A (simple) GUI to set up and run verification campaigns (like DRC, LVS, and PEX on several cells, with summarized run status)? Not sure about that, as open-source tooling is generally script-heavy and GUI-light.