This library provides some "extra" bits of code that are not found in the standard VHDL libraries. With VHDL-extras you can create designs that will resize to varying data widths, compute with time, frequency, and clock cycles, include error correction, and many more commonly encountered issues in digital logic design. These packages can be used for logic simulations and, in most cases, can be synthesized to hardware with an FPGA or ASIC target.

All of the packages are designed to work with VHDL-93. Alternate packages supporting newer VHDL standards are provided where new language features provide enhanced functionality or where forward compatibility is broken. The core code should work in most VHDL-93 compliant tools. In one instance with the timing_ops package, a simplified Xilinx specific implementation is provided because of limitations with the XST synthesizer (fixed in Vivado).

You can use the VHDL-extras library files piecemeal with no tools other than the simulator or synthesizer you will process them with. If you wish to use the provided Modelsim build scripts you will need Modelsim, Python 2.x, sed, grep, and GNU make. To run the test suite you will need Python 2.7 and Modelsim. See the sections on installation and testing for more information on setting up the VHDL-extras library. You can get optional colorized output from the build and test scripts by installing the Python colorama package.

Take a look at the online documentation for more information on what you can do with VHDL-extras.

You can access the VHDL-extras Git repository from Github. Packaged source code is also available for download.

The VHDL-extras library contains the following packages:

• Core packages

  pipelining -- Pipeline registers

  sizing -- Generalized integer logarithms and array size computation

  synchronizing -- Clock domain synchronizing components

  timing_ops -- Conversions for time, frequency, and clock cycles

• Error handling

  crc_ops -- Compute CRCs

  hamming_edac -- Generalized Hamming error correction encoding and decoding

  parity_ops -- Basic parity operations

  secded_edac -- Hamming extension with double-error detection

• Encoding

  bcd_conversion -- Encode and decode packed Binary Coded Decimal

  gray_code -- Encode and decode Gray code

  muxing -- Decoder and muxing operations

• Memories

  fifos -- General purpose FIFOs

  memory -- Synthesizable memories

  reg_file -- General purpose register file

• Randomization

  lcar_ops -- Linear Cellular Automata

  lfsr_ops -- Linear Feedback Shift Registers

  random -- Simulation-only random number generation

• String and character handling

  characters_handling -- Character class identification and case conversions

  strings_fixed -- Operations on fixed length strings

  strings_maps -- Mapping character sets

  strings_unbounded -- Operations on unbounded strings

• Miscellaneous

  binaryio -- Binary file I/O

  text_buffering -- Store text files in internal buffers

  ddfs -- Direct Digital Frequency Synthesizer

  glitch_filtering -- Clean up noisy inputs

All of the source files distributed as part of VHDL-extras are made freely available under the MIT license. The license permits unrestricted use of this code for commercial and non-commercial use. You may freely mix VHDL-extras code with proprietary code. You may make any modifications necessary without any requirement to redistribute your source code. The only requirement is to maintain the copyright and licensing information in the file headers.

It is presumed that portions of the VHDL-extras library will be translated into circuitry with synthesis software. The resulting hardware implementation will be free of any requirements beyond those that apply when the code is used as software. The functions provided in VHDL-extras are all commonly known in the art and are free of any patent restrictions. It would be a nice gesture if the documentation for any hardware containing VHDL-extras code included an acknowledgement of that code and a pointer to this web site.

Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.