Intro Design First Front Timing Synthesis Back Final

ASIC Design Flow How to design your own chip

Frank K. Grkaynak u
Integrated Systems Laboratory 10. October 2006

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Overview Who

Outline of the talk

1 Introduction 2 About design 3 First steps to design 4 Front-end 5 Understanding timing constraints 6 Logic synthesis 7 Back-end
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Overview Who

Who am I ?

Frank K. Grkaynak u
Originally from Turkey Working on IC design since 1994 Studied and gave IC design courses at:
Istanbul Teknik Universitesi ( U) IT Ecole Polytechnique Fdrale de Lausanne (EPFL) e e Worcester Polytechnic Institute (WPI) Eidgenssiche Technische Hochschule Zrich (ETHZ) o u

Worked on IC design at Motorola and IBM, worked for Philips

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Overview Who

Who am I ?

Frank K. Grkaynak u
Originally from Turkey Working on IC design since 1994 Studied and gave IC design courses at:
Istanbul Teknik Universitesi ( U) IT Ecole Polytechnique Fdrale de Lausanne (EPFL) e e Worcester Polytechnic Institute (WPI) Eidgenssiche Technische Hochschule Zrich (ETHZ) o u

Worked on IC design at Motorola and IBM, worked for Philips Made enough errors designing chips to last 3 careers.

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What Tradeos Examples ASICs

What is Hardware Design ?

Physically implementing an idea, a function, a system in hardware.

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What Tradeos Examples ASICs

What is Hardware Design ?

Physically implementing an idea, a function, a system in hardware.

Find the optimal balance between:

Cost / Area Speed / Throughput Energy Consumption / Power Density Design Time

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What Tradeos Examples ASICs

Trade-os in Design

No free lunch
Depending on the design, some parameters are more important. You can generally sacrice one parameter to improve the other:

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What Tradeos Examples ASICs

Trade-os in Design

No free lunch
Depending on the design, some parameters are more important. You can generally sacrice one parameter to improve the other: Speed vs Area It is possible to speed up a circuit by using larger transistors, parallel computation blocks.

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What Tradeos Examples ASICs

Trade-os in Design

No free lunch
Depending on the design, some parameters are more important. You can generally sacrice one parameter to improve the other: Speed vs Area It is possible to speed up a circuit by using larger transistors, parallel computation blocks. Design time vs Performance Given enough time, the circuits can be optimized for higher performance

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What Tradeos Examples ASICs

What is Important for the Following Designs ?

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What Tradeos Examples ASICs

Application Specic Integrated Circuits

When to use ASICs ?

The good: Highest performance Cheap for mass production The bad Long development time Not very congurable Requires specialization

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Specs Feasibility Block Trans

Design Specication

A list of requirements
Function What is expected from the ASIC ? Perfomance What speed, power, area ? I/O requirements How will the ASIC t together with the system ?

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Specs Feasibility Block Trans

We have specications, but can we do it ?

Feasibility ?
For most of the projects: We have never done it, so we dont know exactly! We may: Have experience from earlier projects Make small experiments to estimate performance Choose appropriate technology

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Specs Feasibility Block Trans

Always Start with a Block Diagram

Da ta O De UT bu xD O g De Da bu ta De gA INx bu dd DI g r De EN INx bu xS DI gC I Mo LKx C de xS I I

Da ta IN xD I

Pe nx Ta SO xS I

Iterative Process
Identify blocks What do we need to perform the functionality?

16 128 128 128 128

32

Controller
Reg-128
128

InvShiftRows
128 32

Key Expansion

128

64 x 32 SRAM
128

AddRoundKey
128

ShiftRows
128 128

Reg-128

ShiftRows AddRoundKey

Round Key Generator

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Specs Feasibility Block Trans

Always Start with a Block Diagram

Da ta O De UT bu xD O g De Da bu ta De gA INx bu dd DI g r De EN INx bu xS DI gC I Mo LKx C de xS I I

Da ta IN xD I

Pe nx Ta SO xS I

Iterative Process
Identify blocks What do we need to perform the functionality?

16 128 128 128 128

32

Controller
Reg-128
128

InvShiftRows
128 32

Key Expansion

Visualize structure How are blocks connected?

128

64 x 32 SRAM
128

AddRoundKey
128

ShiftRows
128 128

Reg-128

ShiftRows AddRoundKey

Round Key Generator

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Specs Feasibility Block Trans

Always Start with a Block Diagram

Da ta O De UT bu xD O g De Da bu ta De gA INx bu dd DI g r De EN INx bu xS DI gC I Mo LKx C de xS I I

Da ta IN xD I

Pe nx Ta SO xS I

Iterative Process
Identify blocks What do we need to perform the functionality?

16 128 128 128 128

32

Controller
Reg-128
128

InvShiftRows
128 32

Key Expansion

Visualize structure How are blocks connected? Find critical paths Which block is most critical (speed, area, power)?

128

64 x 32 SRAM
128

AddRoundKey
128

ShiftRows
128 128

Reg-128

ShiftRows AddRoundKey

Round Key Generator

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Specs Feasibility Block Trans

Always Start with a Block Diagram

Da ta O De UT bu xD O g De Da bu ta De gA INx bu dd DI g r De EN INx bu xS DI gC I Mo LKx C de xS I I

Da ta IN xD I

Pe nx Ta SO xS I

Iterative Process
Identify blocks What do we need to perform the functionality?

16 128 128 128 128

32

Controller
Reg-128
128

InvShiftRows
128 32

Key Expansion

Visualize structure How are blocks connected? Find critical paths Which block is most critical (speed, area, power)? Divide and Conquer Draw sub-block diagrams

128

64 x 32 SRAM
128

AddRoundKey
128

ShiftRows
128 128

Reg-128

ShiftRows AddRoundKey

Round Key Generator

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Specs Feasibility Block Trans

Architectural Transformations
Area

Performance parameters: Area (mm2 ) Clock rate (MHz) Throughput (data/sec) Latency (num clock cycles)
1

Parallelization More Efficient

Pipelining

Iteration 1 Time 2 (to complete operation)

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Smaller

Eciency

Faster

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Specs Feasibility Block Trans

Parallelization

More computation
If we use 2 parallel blocks: Area doubles Clock stays same Throughput doubles Latency stays same

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Specs Feasibility Block Trans

Pipelining

Faster computation
if we introduce one pipeline stage: Area increases a little Clock doubles Throughput doubles Latency doubles

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Specs Feasibility Block Trans

Iterative Decomposition

More clock cycles

If we can perform the operation in two iterations: Area halves Clock stays same Throughput halves Latency doubles

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Modelling HDL Sim Testb. Ver. Synth. Cells

Building a Model

Make sure your system works

There are many languages that can be used for modelling: C, C++, SystemC Perl, Java, Tcl Matlab Verilog, VHDL This is not a religion, there is not one denitive answer. Choose whatever is suitable, not always whatever you are comfortable with.

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Modelling HDL Sim Testb. Ver. Synth. Cells

Model Types
Key words in modelling
bit-true The model mimicks the hardware at bit level. Numbers are actually computed at the same accuracy as the hardware cycle-true The model accurately replicates how the hardware works for every clock cycle. transaction-based A high level model that works on blocks of data. It calculates the end result of the computation, intermediate steps are not available The model is an important part of simulation environment

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Modelling HDL Sim Testb. Ver. Synth. Cells

Describing Hardware

Next Lecture
We will discuss this topic in a second lecture How to turn an idea into an architecture How to come up with a block diagram, Converting block diagram into VHDL code

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Modelling HDL Sim Testb. Ver. Synth. Cells

Simulating your Design

Does it actually work ?
Behavioral simulation no delays for processing No performance parameters only functionality is veried Hardware description Not every construct in VHDL or Verilog can be implemented in hardware. This simulation will not show this.

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Modelling HDL Sim Testb. Ver. Synth. Cells

Testbenches

Stimuli Generator stimuli DUT Clock Generator Comparator response simulation report expected response Golden Model

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Modelling HDL Sim Testb. Ver. Synth. Cells

Verication
Bug hunting
Time consuming The majority of design is verication. Exhaustive tests are not feasible A 32 bit adder has 264 possible input combinations. If we check 1.000.000.000 inputs per second it will take 200 days !! Every line we write, has a potential for error People talk about 1 bug every 20 lines of code. Golden models can be wrong Sometimes, your hardware description is correct, but your model is wrong.

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Modelling HDL Sim Testb. Ver. Synth. Cells

Synthesis

Now that we have a working code, convert into hardware

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Modelling HDL Sim Testb. Ver. Synth. Cells

Standard Cell Libraries

Collection of pre-designed gates
simple logic functions and, or, xor, not, nand, nor complex logic functions adders, and-or-invert sequential elements latches, ip-ops dierent drive strengths Each cell has at least 2-4 variations with dierent current driving capabilities

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CMOS Current Cap Delay Reg

CMOS timing basics

Icharge Cload

Idischarge

Goal: to charge the capacitor as fast as possible

Decrease load capacitance Increase driving (strength) current

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CMOS Current Cap Delay Reg

MOS Transistor Equations

ID,lin = Cox

W VDS 2 [(VGS VT ) VDS ] L 2 W (VGS VT )2 L 2

ID,sat = Cox

Driving Current
The geometric parameters directly determine the amount of current that can ow through he transistor. If length (L) is constant, transistors that are wider (W), have more current. Larger transistors are faster

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CMOS Current Cap Delay Reg

Capacitive Loads

Input Capacitance

Interconnect Capacitance Fanout

Capacitive load sources

Input capacitance of gates Interconnect capacitance

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CMOS Current Cap Delay Reg

Input Capacitance

Mos capacitance
The dominant capacitance is the gate capacitance. The capacitance is proportional to the gate area. The wider the transistor the more capacitance it has
Gate Drain
Length n+

n+

Source + +
n n

p-

Bulk

p-

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id

th

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CMOS Current Cap Delay Reg

Timing Basics
Summary
If the load stays constant, making a transistor wider, will make it faster.

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CMOS Current Cap Delay Reg

Timing Basics
Summary
If the load stays constant, making a transistor wider, will make it faster. A larger transistor will have a higher input capacitance

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CMOS Current Cap Delay Reg

Timing Basics
Summary
If the load stays constant, making a transistor wider, will make it faster. A larger transistor will have a higher input capacitance It will be harder to drive this transistor

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CMOS Current Cap Delay Reg

Timing Basics
Summary
If the load stays constant, making a transistor wider, will make it faster. A larger transistor will have a higher input capacitance It will be harder to drive this transistor Find a balance between driving strength and input capacitance

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CMOS Current Cap Delay Reg

Timing Basics
Summary
If the load stays constant, making a transistor wider, will make it faster. A larger transistor will have a higher input capacitance It will be harder to drive this transistor Find a balance between driving strength and input capacitance The fanout (number of driven gates) of a transistor and the length of the interconnections determines the switching speed. Exact contribution of interconnect is not known at early stages, has to be estimated.

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CMOS Current Cap Delay Reg

Constraining your Circuit

The synthesizer is lazy, if you dont set the proper constraints it will select constraints that will make him work less. Always set proper constraints

Synthesis Constraints
max delay combinational delay max area total circuit area setting the constraint does not guarantee the result

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CMOS Current Cap Delay Reg

Sequential Timing

comb. circuit

comb. circuit

comb. circuit

Timing paths
In a sequential circuit there are 4 dierent timing paths: Register to register

comb. circuit

tpd,reg2reg

tpd,FF

tsetup,FF

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CMOS Current Cap Delay Reg

Sequential Timing

comb. circuit

comb. circuit

comb. circuit

Timing paths
In a sequential circuit there are 4 dierent timing paths: Register to register Input to register

tinput

comb. circuit

tpd,in2reg

tsetup,FF

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CMOS Current Cap Delay Reg

Sequential Timing

comb. circuit

comb. circuit

comb. circuit

Timing paths
In a sequential circuit there are 4 dierent timing paths: Register to register Input to register Register to output

comb. circuit

tpd,reg2out

toutput

tpd,FF

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CMOS Current Cap Delay Reg

Sequential Timing

comb. circuit

comb. circuit

comb. circuit

Timing paths
In a sequential circuit there are 4 dierent timing paths: Register to register Input to register Register to output Input to output

tinput

comb. circuit

tpd,in2out

toutput

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CMOS Current Cap Delay Reg

Sequential Timing
Timing paths
comb. circuit comb. circuit comb. circuit

In a sequential circuit there are 4 dierent timing paths: Register to register Input to register Register to output Input to output One of these paths will limit the performance of the system.

tinput

comb. circuit

tpd

toutput

tpd,FF

tsetup,FF

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Goal Results Surprises

Logic Synthesis Results

Synthesis is just a tool

Synthesis tools do not magically generate circuits They are supposed to generate exactly the circuit that you want You must have a good idea of what the synthesis result will be

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Goal Results Surprises

Logic Synthesis Results

Synthesis is just a tool

Synthesis tools do not magically generate circuits They are supposed to generate exactly the circuit that you want You must have a good idea of what the synthesis result will be If the result is not as you expect, you should convince the synthesizer to produce the correct result.

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Goal Results Surprises

Dierent constraints, dierent circuits

Area vs Propagation Delay 40.0k
t ns Co tA an

Look-up Table Algorithmic Decomposition

t uc od pr

35.0k

30.0k

25.0k Area [squm]

20.0k ROM solution space

60.0
50.0

00 2 m .n
m 2.n s

15.0k

00

40.0 0
30.00

0 m 2 .ns

10.0k

0 m 2 .ns

5.0k

0.0 1 1.5 2 2.5 3 3.5 Propagation Delay [ns] 4 4.5 5

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Goal Results Surprises

Dont trust the synthesizer too much

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Goal Results Surprises

Dont trust the synthesizer too much

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Goal Results Surprises

Dont trust the synthesizer too much

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Goal Results Surprises

Dont trust the synthesizer too much

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Goals Fplan Cells Pwr Place Clk Route Ext Opt DRC L

Back-end Design

Now that we have a netlist, let us convert it to a physical layout

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Goals Fplan Cells Pwr Place Clk Route Ext Opt DRC L

Floorplaning
How will the chip look
Determine the total area/geometry of the chip Place the I/O cells Place pre-designed macro blocks Leave room for routing, optimizations, power connections

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Goals Fplan Cells Pwr Place Clk Route Ext Opt DRC L

Floorplaning
How will the chip look
Determine the total area/geometry of the chip Place the I/O cells Place pre-designed macro blocks Leave room for routing, optimizations, power connections iterative process, can not determine the perfect oorplan from the beginning
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Goals Fplan Cells Pwr Place Clk Route Ext Opt DRC L

Standard Cells - 2

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Standard Cell Rows

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Power Planning
VDD

GND

Standard Cell Power Connections Standard Cell Row

Power Stripe

Block Power Ring I/O to Core Spacing

Standard Cells I/O and Corner Pads Placed on the Padframe Power Pad Connections

Macro Cell (RAM)

Block Halo

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Goals Fplan Cells Pwr Place Clk Route Ext Opt DRC L

Placing Standard Cells

NP hard problem
What is the best way of placing the cells within a given area so that: Critical path is minimum Long interconnections on the critical path add capacitance The design is routable Not all placements can be routed. The area is minimum The routing overhead inreases area.

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Goals Fplan Cells Pwr Place Clk Route Ext Opt DRC L

Clock Distribution
Clock is the most critical signal
Standard digital systems rely on the clock signal being present everywhere on the chip at the same time: skew Clock signal has to be connected to all ip-ops: high fan out Specialized tools insert multi level buers (to drive the load) and balance the timing by ensuring the same wirelength for all connection.

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Goals Fplan Cells Pwr Place Clk Route Ext Opt DRC L

Clock Distribution
Clock is the most critical signal
Standard digital systems rely on the clock signal being present everywhere on the chip at the same time: skew Clock signal has to be connected to all ip-ops: high fan out Specialized tools insert multi level buers (to drive the load) and balance the timing by ensuring the same wirelength for all connection. The following example is a 200 MHz 3D image renderer with roughly 3 million transistors. The clock distribution has:
10.928 ip-ops 9 level clock tree 478 buers in the clock tree 34 cm total clock wiring
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Goals Fplan Cells Pwr Place Clk Route Ext Opt DRC L

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Goals Fplan Cells Pwr Place Clk Route Ext Opt DRC L

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Goals Fplan Cells Pwr Place Clk Route Ext Opt DRC L

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Goals Fplan Cells Pwr Place Clk Route Ext Opt DRC L

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Goals Fplan Cells Pwr Place Clk Route Ext Opt DRC L

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Goals Fplan Cells Pwr Place Clk Route Ext Opt DRC L

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Goals Fplan Cells Pwr Place Clk Route Ext Opt DRC L

Routing
Determine interconnection
Multiple (3-9) metal routing layers. Signals on dierent layers do not intersect. Vias to interconnect metals on adjacent layers. The longer the interconnection:
The more the capacitance The slower the connection The more the power consumption

Thin wires, vias add resistance

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Extraction

Timing information depends on interconnect

Once the physical design is complete, everything about the interconnection network is known. It is possible to extract parasitic capacitance for the interconnection Wire capacitance Wire to wire capacitance Wire - via resistance The extracted information can be used to extract timing information. It can be stored in special les (SDF, SPEF) and can be used by circuit simulators.

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Goals Fplan Cells Pwr Place Clk Route Ext Opt DRC L

Optimization

Final timing with parasitics

Parasitics may inuence timing severely. It is possible to make local optimizations to combat additional capacitance: Buers are added to long connections Driver strength of the standard cells is adjusted Incremental change of placement Critical paths are resynthesized

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Design Rule Check

vdd! 0.35 0.25 0.25 0.25 0.1 N-Substrate 0.5 Contact 0.6

Production rules
Every physical layer has limits that are determined by the production ow. These include Minimum spacing Minimum width
0.6 0.25

PMOS transistor

0.6

0.4 0.5

Minimum coverage Minimum area

NMOS transistor

gnd!

P-Substrate Contact

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Goals Fplan Cells Pwr Place Clk Route Ext Opt DRC L

Layout Versus Schematic

Is the layout equivalent to schematic

The physical layout contains only geometric information The devices (transistors) and interconnections are extracted. This is the extracted netlist The extracted netlist is compared to the initial netlist that we started with. Shorts between layers can be detected in this stage. Very important step, this step tells us that the chip is good to go.

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Goals Fplan Cells Pwr Place Clk Route Ext Opt DRC L

Chip is Finished, Now Time For Fun

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Tape-out

Final stage of the design

In old times, the design data was transferred using magnetic tapes, hence the name The geometric data is electronically transfered to the production site Usually there will be an independent DRC check if problems are found, we get asked to correct the problems Then we wait 10-14 weeks for production. Tape-out dates are well-known in advance, and are not negotiable. You have to nish by the given date, no mercy!

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Chip Test Summary Nice

Your Very Own Chip

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Chip Test Summary Nice

Testing

Now that we have our chip back

Does it really work ? The topic of a following lecture

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Chip Test Summary Nice

Summary of the Design Flow

RTL Design RTL Simulation

Synthesis

Gate-level Sim.

Synopsys

Modelsim

Test Insertion

Fault Grading

Placement

Timing

Silicon Encounter

ClockTree

Gate-level Sim.

Timing

Routing

DRC

LVS

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Calibre

Pearl

Tetramax

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Chip Test Summary Nice

A Good Looking Chip Will Always Work

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