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Serial Adder VHDL Code

This document describes a VHDL module for performing serial addition of two binary vectors. It contains: 1) Generic and port definitions for a serial entity that takes in two binary vectors A and B of length N, a clock and reset signal, and outputs the sum vector. 2) Internal signals and components including shift registers to shift in A and B, a finite state machine to control the addition process, and an adder. 3) The finite state machine transitions between states G and H based on the least significant bits of the shifted A and B vectors to sequentially perform addition.

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Rohith Raj
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© Attribution Non-Commercial (BY-NC)
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5K views

Serial Adder VHDL Code

This document describes a VHDL module for performing serial addition of two binary vectors. It contains: 1) Generic and port definitions for a serial entity that takes in two binary vectors A and B of length N, a clock and reset signal, and outputs the sum vector. 2) Internal signals and components including shift registers to shift in A and B, a finite state machine to control the addition process, and an adder. 3) The finite state machine transitions between states G and H based on the least significant bits of the shifted A and B vectors to sequentially perform addition.

Uploaded by

Rohith Raj
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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LIBRARY ieee ; USE ieee.std_logic_1164.

all ; ENTITY serial IS GENERIC ( length : INTEGER := 8 ) ; PORT ( Clock : IN STD_LOGIC ; Reset : IN STD_LOGIC ; A, B : IN STD_LOGIC_VECTOR(length-1 DOWNTO 0) ; Sum : BUFFER STD_LOGIC_VECTOR(length-1 DOWNTO 0) ); END serial ; ARCHITECTURE Behavior OF serial IS COMPONENT shiftrne GENERIC ( N : INTEGER := 4 ) ; PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; L, E, w : IN STD_LOGIC ; Clock : IN STD_LOGIC ; Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END COMPONENT ; SIGNAL QA, QB, Null_in : STD_LOGIC_VECTOR(length-1 DOWNTO 0) ; SIGNAL s, Low, High, Run : STD_LOGIC ; SIGNAL Count : INTEGER RANGE 0 TO length ; TYPE State_type IS (G, H) ; SIGNAL y : State_type ; BEGIN Low <= 0 ; High <= 1 ; ShiftA: shiftrne GENERIC MAP (N => length) PORT MAP ( A, Reset, High, Low, Clock, QA ) ; ShiftB: shiftrne GENERIC MAP (N => length) PORT MAP ( B, Reset, High, Low, Clock, QB ) ; AdderFSM: PROCESS ( Reset, Clock ) BEGIN IF Reset = 1 THEN y <= G ; ELSIF Clock EVENT AND Clock = 1 THEN CASE y IS WHEN G => IF QA(0) = 1 AND QB(0) = 1 THEN y <= H ; ELSE y <= G ; END IF ; WHEN H => IF QA(0) = 0 AND QB(0) = 0 THEN y <= G ; ELSE y <= H ; END IF ; END CASE ; END IF ; END PROCESS AdderFSM ;

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