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E1-Vlsi Signal Processing

This document outlines the syllabus for the elective course "VLSI Signal Processing". The course is a 3 hour credit course with 20 marks for college assessment and 80 marks for university assessment. The course code is BEECE705T/BEETE705T. The objectives of the course are to learn pipelining and parallel processing techniques, understand folding and unfolding techniques in multirate systems, and address folding techniques used to design time multiplexed architectures. By the end of the course, students will be able to optimize power, delay and area of VLSI designs, build real-time processing systems, and design algorithm structures for DSP algorithms based on algorithm transformation. The course contains 6 units that cover topics like p

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245 views2 pages

E1-Vlsi Signal Processing

This document outlines the syllabus for the elective course "VLSI Signal Processing". The course is a 3 hour credit course with 20 marks for college assessment and 80 marks for university assessment. The course code is BEECE705T/BEETE705T. The objectives of the course are to learn pipelining and parallel processing techniques, understand folding and unfolding techniques in multirate systems, and address folding techniques used to design time multiplexed architectures. By the end of the course, students will be able to optimize power, delay and area of VLSI designs, build real-time processing systems, and design algorithm structures for DSP algorithms based on algorithm transformation. The course contains 6 units that cover topics like p

Uploaded by

tariq76
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© © All Rights Reserved
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B. E.

Seven Semester
(Electronics & Communication/ Electronics & Telecommunication Engg)

ELECTIVE 1 - VLSI SIGNAL PROCESSING


Duration : 3 Hr.
College Assessment : 20 Marks
University Assessment : 80 Marks
Subject Code : BEECE705T/ BEETE705T
[ 3 0 1 4]

Objectives :
1. To learn pipelining & parallel processing techniques.
2. To understand folding & unfolding techniques in multirate system
3. To address folding techniques used to design time multiplexed
architecture .
Outcome : By the end of the course, the students shall be able to
1. Learn various methodologies to optimize power delay and area of
VLSI design.
2. Build Real Time processing system .
3. Design of algorithm structure for DSP algorithms based on algorithm
transformation .

Unit I : Pipeling and Parallel Processing


(08)
Introduction, pipeling of FIR Digital filters Parallel processing, Pipelining and
parallel processing for low power.
Unit II : Retiming
(06)
Introduction, Definition and properties, Solving system of inequalities, retiming
techniques.
Unit III : Unfolding
(08)
Introduction, algorithms for unfolding, Properties of unfolding, Critical path,
unfolding and retiming Application of unfolding.
Unit IV: Folding
(08)
Introduction Folding Transformation, Register minimization in folded architectures,
Folding in Multirate systems.
Unit V : Fast Convolution
(08)
Introduction, Cook- Toom algorithm, Winogard algorithm.

Unit VI :
(07)
Iterated convolution, Cyclic Convolution, Design of Fast Convolution Algorithm by
Inspection.

Text Books:
1. Keshab K. Parhi. VLSI Digital Signal Processing Systems Wiley-Inter Sciences.
1999
2. Mohammed Ismail, Terri, Fiez, Analog VLSI signal and information processing,
McGraw Hill ,1994.
3. Keshab. Parthi, VLSI Digital signal processing system Design and
implementation WileyInter science, 1999.
4. kung. S.Y., H.J. While house T.Kailath VLSI and Modern singal processing,
prentice hall,
1985.
5. Jose E. France, Yannis Tsividls Design of Analog Digital VLSI circuits for
telecommunications and
signal processing prentice Hall, 19994.

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