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21 FSM Examples

The document describes a finite state machine (FSM) that reduces a stream of binary inputs to a single output bit by detecting when at least two consecutive 1s have occurred in the input stream. The FSM uses one bit of state to track whether zero, one, or two or more 1s have been seen. It provides state transition diagrams and logic expressions for the next state logic and output logic. Verilog code is presented to implement the FSM with one or two state bits and with the next state logic and output logic combined or separated.

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vikramkolanu
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33 views4 pages

21 FSM Examples

The document describes a finite state machine (FSM) that reduces a stream of binary inputs to a single output bit by detecting when at least two consecutive 1s have occurred in the input stream. The FSM uses one bit of state to track whether zero, one, or two or more 1s have been seen. It provides state transition diagrams and logic expressions for the next state logic and output logic. Verilog code is presented to implement the FSM with one or two state bits and with the next state logic and output logic combined or separated.

Uploaded by

vikramkolanu
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
Download as pdf or txt
Download as pdf or txt
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always @(in or state)

`define zero 0
`define one1 1
`define two1s 2

case (state)
`zero:
// last input was a zero
begin
if (in) next_state = `one1;
else
next_state = `zero;
end
`one1:
// we've seen one 1
begin
if (in) next_state = `two1s;
else
next_state = `zero;
end
`two1s:
// we've seen at least 2 ones
begin
if (in) next_state = `two1s;
else
next_state = `zero;
end
endcase

module reduce (clk, reset, in, out);


input clk, reset, in;
output out;
reg out;
reg [2:1] state;
// state variables
reg [2:1] next_state;
always @(posedge clk)
if (reset) state = `zero;
else
state = next_state;

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always @(state)
case (state)
`zero: out = 0;
`one1: out = 0;
`two1s: out = 1;
endcase
endmodule

!+

*)

module reduce (clk, reset, in, out);


input clk, reset, in;
output out;
reg out;
reg state;
// state variables
reg next_state;
always @(posedge clk)
if (reset) state = `zero;
else
state = next_state;
always @(in or state)
case (state)
`zero:
// last input was a zero
begin
out = 0;
if (in) next_state = `one;
else
next_state = `zero;
end
`one:
// we've seen one 1
if (in) begin
next_state = `one; out = 1;
end else begin
next_state = `zero; out = 0;
end
endcase
endmodule

module reduce (clk, reset, in, out);


input clk, reset, in;
output out;
reg out;
reg state; // state variables
always @(posedge clk)
if (reset) state = `zero;
else
case (state)
`zero:
// last input was a zero
begin
out = 0;
if (in) state = `one;
else
state = `zero;
end
`one:
// we've seen one 1
if (in) begin
state = `one; out = 1;
end else begin
state = `zero; out = 0;
end
endcase
endmodule

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