Microprocessor and Programming

Chapter No.
1
Basics of
Microprocessor
8085
Memory
basics
To address any
location or to
select any
location we
require
address lines.
No of address
lines =
Control inputs
Data input
lines used for
DATA BUS
writing
operation
Address lines
Every location consist

of N bit data (in
general 8 bit data)
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To select the chip,

whether read or
write operation
0000 1111 (0FH)

0010 0100 (24H)
1010 1110 (AEH)
0001 1010 (1AH)
0101 0111 (57H)
D
Data output
lines used for
A
reading
T
operation
A
B
U
S
BY UBAID SAUDAGAR
No. of
locations =M
Eg: 3 bit address lines
are therefore = 8
locations and address
varies as:
000
001
010
111
and at every location
8 bit data present
What is a Microprocessor (p) ?

As we know that to perform logical operations like AND,OR,NOT etc. we have digital ICs like IC
7400,7408 etc.
Simple addition operation we require half adders and full adders, for subtraction we require half and
full subtractor, which can be constructed using digital ICs.
In general for performing any arithmetic and logical operation we require we require n number of ICs
and bulky circuitry.
Now integrating all this circuitry onto a single chip is called a microprocessor.
Integrating all this circuitry on a single chip is done with the help of a technology called as VLSI
technology i.e. Very large scale integration.
The added advantage is that we can control all this circuitry with the help of commands.
Eg. For adding two 8 bit numbers we require is one half adder and seven full adders and we get the o/p
by switching on and off the switches but now we will give the instruction to the microprocessor as ADD
A,B which will add content of A and B which are both 8 bits.
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What is a Microprocessor (p) ? Cont.
Therefore,
A microprocessor is an integrated circuit on a tiny silicon chip that contains thousands or
millions of tiny on/off switches, known as transistors.
The transistors are laid out such that they store or manipulate data. These circuits
manipulate data in certain patterns, patterns that can be programmed by software to
make machines do many useful tasks.
One of the biggest tasks microprocessors perform is acting as the brains inside a personal
computer. The number of transistors on a chip has grown from 2,300 on the 4004 in 1971
to 5.5 million on today's Pentium Pro processor. These advances have made today's
microprocessors 1,000 faster than their predecessors.
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Microprocessor Based System

(Microcomputer)
A microprocessor can itself do nothing on its own, it requires some supporting devices do
complete a particular task called as peripherals.
Eg. Our brain can thinks of picking up a book but it is not the job of the brain to pick up a
book, it has a supporting device i.e. its hand which when gets an impulse from the brain
picks up the book.
Similarly p has peripherals
i/p o/p attached to it like memory, i/p devices, o/p devices, io ports
etc.
devices
Microprocess
or
Ports
Memory
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8085 Microprocessor
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Features of 8085 microprocessor

It is a 8 bit microprocessor.
It is manufactured with N-MOS technology.
It has 16-bit address bus and hence can address up to 2^16 = 65536 bytes (64KB) memory
locations through A0 -A15
The first 8 lines of address bus and 8 lines of data bus are multiplexed AD0 AD7
Data bus is a group of 8 lines D0 D7
It supports external interrupt request.
A 16 bit program counter (PC)
A 16 bit stack pointer (SP)
Six 8-bit general purpose register arranged in pairs: BC, DE, HL.
It requires a signal +5V power supply and operates at 3.2 MHZ single phase clock.
It is enclosed with 40 pins DIP (Dual in line package).
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ARCHITECTURE OF 8085
The internal hardware design of the p
is called the Architecture of that p.
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Register Organization
In the architecture above we see many registers. The basic use of the register is temporary storage of
data.
But there are also some registers which are used for special purpose as well which will be defined later.
There are some registers which are accessible to the user and some are those which are not accessible to
the user.
Since the microprocessor is an 8 bit microprocessor hence all the general purpose registers are 8 bit in
size. It means that it can store 8 bit data.
These are six general purpose registers namely B,C,D,E,H,L all 8 bit in size.
They are used in general to store 8 bit data temporarily. Sometimes during calculations to
store the intermediate value, sometimes to store the result of any calculations etc.
These six registers can also be used to store 16 bit data by using them in pairs as BC, DE, HL.
When used in pairs they are also used to store addresses of memory locations which are 16 bits.
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Register organization cont..

Accumulator is also an 8 bit register which is used to store temporary data.
But it has also other tasks
It is the most important register of a microprocessor and every microprocessor consists of
an accumulator.
It is used by the ALU (arithmetic logic unit). During addition or subtraction operation the
result is stored in the accumulator. After which we store it anywhere we want.
Eg. ADD B instruction will add the content of register B (where temporary data is stored)
and accumulator and store the result in the accumulator itself.
Also when the microprocessor is sending some data to the io devices the data must be
stored first in the accumulator and then transferred.
This is an 8 bit temporary register which is not used by the user but only used by
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11
the microprocessor
itself to store temporary
data.
Register organization cont..

This an 8 bit flag register. Flag register is normally used to reflect the result of some operations or
to
control some operations. Out of the 8 bits only 5 bits are used. Each bit is called as a flag which reflects
the result of some operation or controls some operations.
These are two registers which actually act as pointers .
Program counter points to the next memory address while current instruction is in execution stage.
Eg. 2000H: MOV A,B
2001H: MVI B,32H
When the instruction at the address 2000H is being executed the program counter points to the next
memory address i.e. 2001H.
Stack pointer is also a 16 bit pointer which points to the stack memory. What is stack memory we will
see later
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Basic concepts about Opcode and

Operand
Note: An instruction is actually a command which we give to the microprocessor which it
follows and performs the tasks as instructed.
Opcode indicates what operation is to be performed.
Operand indicates on which the operation is to be performed.
How the operation is to be performed we come to know by addressing mode.
Lets understand by an example:
MVI A,32H is an instruction which the microprocessor does not understand directly. Hence
what we do is we write its hex codes.
The above is a two byte instruction and hex codes are written as
2000 : 3EH
2001 : 32H
Where 2000 and 2001 are the addresses where the hex codes are stored.
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Basic concepts about Opcode and

Operand
As we can see above there are 2 hex codes namely 3EH and 32H
Now this 3EH is actually 1 byte i.e. 0011 1101 B
Now this byte is the first byte which will enter the microprocessor
Now this byte when decoded will give two information's viz. what operation is to be
performed and the size of the instruction.
Hence we call this first byte as opcode or operational code which tells the microprocessor
what operation is to be performed.
The second thing which the microprocessor understands is that it is a 2 byte instruction
hence when the next byte i.e. 32H i.e. 0011 0010 B goes into the microprocessor, instead
of decoding it will treat is as data and move into the accumulator as directed by the
opcode.
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Working overview of the

microprocessor
A bus
AD bus
Control bus
Microprocess
or
2000: 32H
2001: 3EH
2002: 47H
Memory
Let's understand the working by considering a memory attached to the microprocessor.

Consider a read operation takes place. Now a control signal goes low controlled by the timing and control unit
i.e. RD
Note: The timing and control unit is used to generate timing signals for proper working of the microprocessor
and also it generates control signals to control the different operations and peripherals of the microprocessor.
It is not that the operations are working randomly in any manner, they are working in a sequence. Eg. Lectures
and practical's are going in a sequence, if there is no time table the department would not run properly.
Similarly the timing and control unit gives a proper sequence to the processor and controls different operations
with the help of control signals.
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microprocessor cont..
RD is connected to the memory chip at OE pin which is also active low. The memory is
now ready for read operation. Now this RD signal from the timing and control unit goes
low indicating read operation. IO/M also goes low indicating memory operation.
Now we require the address of the memory location from where we need to access data
which is available in the program counter.
Note: The program counter is a 16 bit register which holds the next address of the
memory location to be accessed or in other words it indirectly points to the next memory
address as shown below.
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Now this 16 bit address available in the PC is given to the address buffers. Both these address buffers are 8 bit in
size, therefore the address is divided into two parts i.e. upper address and lower address.
For Eg: consider address 2001H, now this address is divided as 20H
1
and 01H. Now this 20H is called as upper address or higher order
address and 01H is called as lower order address.
The higher order address from the address buffer (1) is transferred to the higher order address bus and the lower
order address from the address buffer (2) is transferred to the multiplexed lower order address/data bus.
The ALE signal from the timing and control unit goes high making address available on the multiplexed AD bus.
Both the addresses gets transferred on the address bus and the particular memory location is selected.
After that the data on that particular location is transferred on the multiplexed AD bus which is 8 bit wide. The
ALE signal now goes low i.e. ALE = 0 and the data from the memory now gets transferred from the memory to
the microprocessor.
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Since the size of the AD bus is 8 bits hence the microprocessor can process only 8 bit data at a time.
This 8 bit data which enters the microprocessor gets loaded to the instruction register and then goes to the instruction
decoder where it is decoded.
Once it is decoded the microprocessor comes to know two things viz. what task is to be performed and the size of the
instruction.
Eg. MVI A,32H is an instruction which is stored in the memory as 3EH, 32H
3EH = 0011 1101 = 1 byte
32H = 0011 0010 = 1 byte
Always the first byte is opcode and then is the operand (data).
Opcode: Operational code is a binary code which has a specific meaning understood by the microprocessor. Opcode
gives two information viz. what task is to performed and what is the size of the instruction.
Eg. Consider two instructions MOV A,B and MVI A,32H
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The first instruction is one byte instruction for which the opcode is 78H i.e. 0111 0100
when this opcode is decoded by the instruction decoder, the p comes to know that it is a
1 byte instruction, and it has to move the content present in B register to the A register.
But when the second instruction is executed, the first byte of that instruction i.e. 3EH =
0011 1101 when decoded by the p, it comes to know that it is a 2 byte instruction and it
has to move the immediate value 32H in the accumulator.
After which it goes to the next memory address where the second byte is present i.e. 32H
and moves this byte into the p. Now this byte is not treated as opcode but treated as
operand (data) which will we added to the contents of the accumulator and the result will
be stored in the accumulator itself.
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About Address And Data Bus

The address bus has 8 signal lines A8 A15 which are unidirectional.
The other 8 address bits are multiplexed (time shared) with the 8 data bits.
So, the bits AD0 AD7 are bi-directional and serve as A0 A7 and D0 D7 at the same
time.
During the execution of the instruction, these lines carry the address bits during the early
part, then during the late parts of the execution, they carry the 8 data bits.
In order to separate the address from the data, we can use a latch to save the value
before the function of the bits changes.
There is a control signal called as ALE which when goes high, the address is available on
the multiplexed AD bus and it gets latched otherwise this address gets lost
When ALE goes low data is available on the AD bus and this data either goes to the io
device or to the memory as per the address
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How address and data are separated ?
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Interrupt control
Interrupts are those which break the normal sequence of operation of the microprocessor.
There are 6 hardware interrupts out of which 5 are input and one output interrupt pin.
There are maskable and nonmaskable interrupts.
Maskable interrupts are those which can be avoided.
Eg. Mobile phone, when the phone bell rings, if I am busy I can avoid the phone call by not picking it up.
Similarly when an interrupt which is maskable arrives at the microprocessor, if the microprocessor is busy it can avoid
this interrupt and respond to it at any other time.
Non maskable interrupts are those which cannot be avoided.
Eg. Smoke detector mounted on the ceiling of a classroom. It has to detect the smoke anyhow and cannot avoid it.
Similarly when a non maskable interrupt arrives at the microprocessor It cannot be avoided, the microprocessor stops its
current task and responds to the interrupt.
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Serial IO control
To transfer the data and receive data serially to and from the microprocessor, serial io control is used with two
pins namely SID and SOD.
These pins are used when microprocessor needs to communicate with any device serially or in other words
during serial communication where data is transferred is transferred to and from the microprocessor in serial form
(Bit by bit).
Serial i/p data and Serial o/p data for receiving and transferring data serially.
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Binary number formats

Nibble : 4 bits form a nibble
Eg : 1000
Byte : 8 bits form a byte
Eg : 1000 1011
Lower nibble
Higher nibble
Word : 16 bits form a word

Lower byte
Eg : 1001 1000 1011 1010
Higher byte
Quad word : 64 bits form a quad word

Eg : 1000 10001 1010 1011 1100 1101 0001 0010 1000 10001 1010 1011 1100 1101
0001 0010
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Pin diagram of 8085
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Limitation Of 8085 Microprocessor

i. The 8085 is an 8-bit microprocessor hence it can perform operation only on two 8-bit numbers.
ii. The 8085 has 16 bit address lines and 8-bit data lines.
iii. The 8085 can address maximum memory of 64 Kb (2^16).
iv. The 8085 cannot perform any operation on ASCII number.
v. The 8085 cannot perform multiplication and division of numbers.
vi. The 8085 cannot perform subtraction, multiplication and division of BCD number.
vii. The 8085 cannot transfer the data directly from one memory to another memory.
viii. The 8085 cannot perform the pipelining of instruction.
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Chapter No.2
16 bit
Microprocessor
8086
What do you mean by 16 bit

processor?
A processor is said to be 16 bit processor, it means that:
1. The size of the data bus is 16 bits
2. Since the size of the data bus is 16 bit, therefore 16 bit data can be accessed and processed at a
time (i.e. in parallel i.e. simultaneously).
3. Size of the ALU (arithmetic logic unit) is 16 bits.
4. Size of the registers is 16 bits.
Note: This is because when 16 bit data enters the p it needs to be stored temporarily and processed
simultaneously. For Eg. If the size of the ALU is 8 bit and 16 bit enters the p, then if the p was taking 1
clock cycle to process the data it will take 2 clock cycles to process the data and will work as an 8 bit
processor.
5. Size of the microprocessor never depends on the address bus.
Note: Whenever we open the My computer in windows and right clicking on the C drive, then properties,
there we see 32 bit operating system, it means that the operating system is working on a 32 bit p.
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Salient features of 8086 p

It
requires +5V power supply
It is a 40 pin IC
Available in three clock rates: 5,8 and 10 MHz
It is a 16 bit microprocessor
Size of data bus is 16 bits
Size of address bus is 20 bits
Direct memory access upto 1Mb =
Note: Size of the memory always depends on the number of address lines.
Two separate units: Bus Interface Unit and Execution Unit
External Co processor (8087) supported
6 byte instruction queue present to help speed up instruction execution
Has multiplexed address and data bus
It consist two memory banks viz. odd memory bank and even memory bank
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Salient features of 8086 p

Concept of memory
addressing
Two address lines
Memory
Size of the data bus is 16

bits
No. of combinations possible

This is indicating bus (no. of lines together)
on two address lines are:
00
01
10
11
Therefore we can access 4 memory locations =
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Architecture of 8086
rnal hardware design of the p is called the Architecture of that p.

n in the block diagram 8086 is divided into two functional units : BUS INTERFACE UNIT (BIU) a
TION UNIT. Dividing the work between these two units speeds up processing.
U:
s out addresses
es instructions and data from memory
s the ports
words all operations related to outside world (outside the p) are handled by the BIU
ata transfers and address transfers are handled by this unit for BIU.
d Bus interface unit itself indicates that this unit is used to interface the buses with the outside w
BIU where to fetch instructions and data from

des the instruction
utes the instruction
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BIU
Memory
Interface
20
ARCHITECTURE
6
5
4
DS
ES
Segment Registers
--------
CS
6 byte
instruction
queue register
---------------------------------INSTRUCTION
DECODER AND
IP
Instruction pointer
CONTROL UNIT
-------------------------------------------------------INTERNAL SYSTEM BUSES
SS
AH
AL
BH
BL
CH
CL
DH
DL
General purpose
Registers
ARITHMETIC LOGIC
UNIT (ALU)
SP
BP
SI
EU
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DI
Pointers and index

Registers
TEMPORARY
REGISTER
FLAG REGISTER
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BIU (Bus Interface Unit)

The BIU consist of the following modules:
1. Physical address calculation unit (Generates 20 bit physical address)
2. Segment registers (Used to store the base address to access a segment)
3. Instruction pointer (Used to store the offset address, used along with the code segment)
4. Queue register, 6 bytes long (Used to store 6 prefetch instruction bytes from the memory)
With the help of these modules it performs the following action:
-. It sends out addresses to access memory and i/o ports
-. It fetches instructions and data from the memory and also performs write operation with the
help of system bus
-. In other words it interfaces with the external world
-. Instruction queuing in the queue register
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EU (Execution Unit)
The execution unit consist of the following modules:
1. General purpose registers (They are used for multipurpose)
2. Pointers and index registers (As offset registers to select a particular location within a segment)
3. Arithmetic logic unit (ALU)
4. Operand register or temporary register ()
5. Flag register
6. Instruction decoder
7. Timing and control unit
With the help of these modules the following actions are performed:
-. The instruction bytes coming from the queue are decoded by the instruction decoder (here we come to
know two things : (1). How many bytes instruction (2). What operation is to be performed (by decoding
the opcode))
-. After decoding execution takes place and data is placed in proper registers or send to the BIU to save in
the memory
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Instruction Decoder and Control Unit

As we have seen that a decoder is a combinational circuit which has binary inputs and it
converts these binary inputs to corresponding code depending upon the circuit which it is
going to drive.
Eg : A seven segment decoder driver i.e. IC 7447 had 4 inputs and 7 outputs.
These 4 were inputs in binary form and o/p combination of 7 o/ps was depending upon
the number to be displayed.
Similarly in the execution unit the decoder which is present, what it does, whenever any
byte arrives from the BU into the decoder, it decodes in such a way that it comes to know
two information viz. what operation is to be performed and the size of instruction in bytes.
Note: Always the first byte which arrives at the decoder is taken as opcode from which
we come to know what operation is to be performed and there after it comes to know that
the instruction is of how many bytes.
After decoding it drives the control unit which generates proper control signals to execute
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those bytes
which have been decoded. BY UBAID SAUDAGAR
General purpose registers

There are in all 4 general purpose registers viz. AX, BX, CX, DX each of 16 bits i.e. 2 bytes
i.e. 1 word.
These 4 registers are actually are pairs of 8 registers viz. AH, AL, BH, BL, CH, CL, DH, DL
each of 8 bits i.e. 1 byte.
The letter X specify complete 16 bit register. The letters L and H specify lower and higher
15
7
bytes of a register.
8 AH
0 AL
CH
CL
DH
DL
To store every bit 1 f/f is used hence an 8 bit register is used to store 8 bits and to store
BH
BL
16 bits, 16 bit register is used.
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General purpose registers

1. AL/AX (Accumulator): It is intermediate register between the ALU and the memory. Mostly, but
not always the results of arithmetic and logical operations are stored in the accumulator and then
from there it is transferred to wherever required.
It is the most important general purpose register of the p.
Eg: When the instruction DIV BL is executed what the p does is that it divide content of AX register
with the content of BL register by default and after dividing the quotient is by default stored in the AL
register and remainder is stored in the AH register.
2. BX (Base Register): To select any memory location particularly in the data segment we require
two addresses : base address (stored in the segment register) and offset address which can be
stored in the base register in certain addressing modes.
3. CL/CX (Counter Register): It is used as a default counter register during loop, shift, rotate,
repeat instructions. It can be used as 8 bit counter as well as 16 bit counter.
4. DX (Data register): During multiplication and division operations when the result goes beyond
16 bits i.e. 32bits, then the upper 16 bits are stored in the DX register.
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Segment registers
There are 4 segment registers in the Bus interface unit, size of each segment register is 16 bits.
15
0
Code Segment Register (CS register)
Code segment register (CS)
Data Segment Register (DS register)
Data segment register (DS)
Extra Segment Register (ES register)
Extra segment register (ES)
Stack Segment Register (SS register)
Stack segment register (SS)
The entire memory can be divided into four segments
- Code segment (Used to store instruction codes of the program)
- Data segment (Used to store data bytes/words)
- Extra segment (It is an additional segment to store data)
- Stack segment (Its used to store stack of data and addresses of main program during subroutine call)
Segment registers give the base address (starting address) to select any memory segment.
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Segment registers
Segment registers
CS
2500H
DS
4000H
ES
5000H
SS
7654H
Base
addrese
s
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Code segment
0000H
1 MB
memory
FFFFH
Data segment
0000H
FFFFH
Extra segment
0000H
FFFFH
Stack segment
0000H
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Operand register or Temporary

register
It is a 16 bit register which can store 16 bit data.
This register cannot be used by the programmer/user.
It is used by the p to store intermediate data or results therefore it is called as
temporary register.
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Pointers and Index Registers

The 16 bit register from where the p will take 16 bit effective address is called memory pointer.
There are three pointer registers as follows:
- Instruction pointer (IP)
- Stack Pointer (SP)
- Base Pointer (BP)
Also there are 2 index registers which have multiple purposes such as:
- Can be used for pointer addressing of data
- Used as source in some string processing instructions
- Used to store Offset address
Note: The index registers are also a type of memory pointers but having multiple purpose
There are two index registers as follows:
- Source Index register (SI) - Destination Index Register (DI)
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Instruction pointer (IP) register

The different instruction codes are stored in the memory in the code segment. Now to
execute these instructions the p needs to access these codes. Hence it generates 20 bit
physical address on the address bus.
Now to form this 20 bit physical address we require base address and offset address.
p will always take the base address from CS register and offset address from IP
00000H
register.
CS
1000
H
IP 2FACH
PA = BA + EA = 20 bits =
12FACH
Code
segment
-
8086
Memory
Microprocessor
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FFFFFH
42
Stack Pointer (SP) register

The stack memory segment is used to save useful data in the form of stack of data and
addresses when the p transfers the control from the main program to the subroutine.
To access the stack memory segment again we require physical address of 20 bits. Now
we require base address and offset address. p will always obtain the base address from
SS register and offset address from SP register.
Initial
The stack segment register and the stack pointer
register together
address the stack
top.
stack
0000H
1000H
Stack
top
segment
SS BA
PA = BA + EA = 10000H
Top of stack
FFFCH
SP OA
+ FFFCH = 1FFFCH
25
FFFDH
00
Microprocessor
98
34
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FFFEH
FFFFH
43
Stack memory
The stack in the 8086/8088 microprocessor, like that in many microprocessors, is a region of memory
that can store information for later retrieval. It is called a stack, because you "stack" things on it. The
philosophy is that you retrieve (pop) things in the opposite order of storing (push) them.
While executing main program you require some instructions which need to be executed again and
again within the same program, so instead of writing the same set of instructions again and again we
write a sub program or subroutine and then we call that subroutine from the main program.
So when we call the subroutine the address on the address bus changes as the control now gets
transferred to a different program. Therefore to avoid loss of address of main program we store this
address in a memory called as stack memory.
Now when the control gets transferred from main program to sub program the address on the address
bus changes. After executing the subroutine the address of the main program is required which is
stored in the stack memory.
This address is then again popped from the stack memory, and control gets transferred to main
program.
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Stack concept
SS = BA =
1000H
But if SP is loaded
initially = 1000H and
then PUSH inst. Is
executed then data
storage starts from
0FFFH and then
points to data last
entered i.e. 0FFEH
3AH
0000H
5DH
0FFEH
6FH
0FFFH
8BH
1000H
3EH
FFFEH
2CH
FFFFH
STACK SEGMENT
64 Kb
AX =
PUSH AX when SP =
2C3EH
0000H
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Offset address
varies from 0000H
to FFFFH
AX =
6F5DH
PUSH AX when SP =
1000H
Initially SP = 0000H
When PUSH inst. Is
executed storage of
data starts from 1
less i.e. FFFFH and
then points to the
data last entered i.e.
FFFEH
BY UBAID SAUDAGAR
STACK SEGMENT
64 Kb
45
Lets understand Stack with help of a

program
data segment
push ax
a dw 2500h
push bx
b dw 3498h
mov ax,0000
data ends
mov bx,0000
code segment
pop cx
start:
pop dx
mov ax, data
int 3
mov ds, ax
mov ax,0000h
code ends
mov ax, a
end start
mov bx, b
1/15/16
BY UBAID SAUDAGAR
46
Base pointer (BP) register

The stack segment is basically used to store stack of data and addresses during
subroutine calls or Call instruction. The size of the stack segment is 64kb but the entire
64kb is not used as stack data starts from the last addresses i.e. FFFFH and then moves
up. The upper region i.e. from 0000H is mostly empty and user can store its normal data
over there.
We know that SP register is used along with SS register to form the physical address and
the SP register points to the top of stack i.e. last byte entered into the stack memory as
stack.
Now if the user wants to store normal data into the stack i.e. from the address 0000H, the
p by default uses the BP register along with the SS register to form the physical address.
Note: Therefore the stack segment (SS) register can be used along with BP and SP
1/15/16
BY UBAID SAUDAGAR
47
Base pointer (BP) register

0000H 0 0 1 0 0 1 0 0000H
1
SS
BP
SP
- - - - - - - -
BA
OA
EA
0 0 1 1 0 1 1 0010H
1
PA = SS + BP = 00000H +
0010H = 00010H
- - - - - - - - - - - - - - 0 1 0 1 0 1 1 FFFCH
0
- - - - - - - -
Microprocess
or
1/15/16
1 0 0 1 1 0 0 FFFFH
0
BY UBAID SAUDAGAR
48
Source index (SI) and Destination

index (DI) registers
We know that data segment is used to store data. To access data segment we require 20
bit physical address.
Now this 20 bit physical address is formed using base address an offset address.
p will take the Base address from the DS register and the offset address from either SI
0000H
register or DI register or even BX register which 1000H
is called as base register.
DS
SI
BA
OA
DI
EA
BX
EA
PA = DS + (SI or DI or BX)
= 10000H + 2000H = 12000H
or
= 10000H + 3000H = 13000H
or
= 10000H + 4000H = 14000H
processor
1/15/16
2000H
3000H
4000H
FFFFH
BY UBAID SAUDAGAR
49
Flag register of 8086

Bit
16
X
Bit
15
X
Bit
14
X
Bit
13
X
Bit
12
OF
Bit
11
DF
Bit
10
IF
Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

TF
SF
8 MSBs
X Indicates Intel reserved (for future use)
CF Carry Flag
PF Parity Flag
AC Auxiliary Carry Flag
ZF Zero Flag
SF Sign Flag
TF Trap Flag
IF Interrupt Flag
DF Direction Flag
OF Overflow Flag
1/15/16
Total 9
flags
ZF
AC
PF
CF
8 LSBs
A 16 bit register used out of which 9 are used by

the p and the rest are reserved by Intel for
future use.
Since it is a register it can either be 0 or 1
Therefore a flag may be reset or set
The flags may be status flags or control flags
Status flags are those which give the current
status of the p
Control flags are those which control the
operations of the p
BY UBAID SAUDAGAR
50
Flag Register of 8086 cont..

Flags are basically used to reflect the status of the operations of the microprocessor or to
control the operations of the microprocessor.
Flags are a modified kind of register that record the condition of a microprocessor's
calculation.
Flag Register determines the current state of the processor.
Lets understand by an example:
Let AL = 95H = 1001 0101
BL = 6FH = 0110 1111
We ADD the contents of AL and BL registers with the help of the instruction ADD AL ,
Carry generated
This 8 bit value is stored in the
BL.
which is reflected by
the carry
flagthe two contents: 1001 0101
When
we add
AL register
+ 0110 1111
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BY UBAID SAUDAGAR
51
Flag Register of 8086 cont..

This instruction will add the contents of AL and BL and the result i.e. 104H has to be
stored in the register AL.
But what we notice is that the size of AL register is 8 bits only and it cannot accumulate
104H as it is 12 bits.
So what the microprocessor will do is that, it will store 04H in AL register and set the
carry flag to indicate that a carry is generated due to addition.
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BY UBAID SAUDAGAR
52
Carry flag (Bit 1)

Type: Status flag
Operation: During an addition operation if a carry is generated from the MSB or during a subtraction
operation a borrow is generated carry flag sets indicating a carry or borrow respectively.
Eg: 8 bit addition
We use the instruction ADD AL,BL (the contents of AL and BL are added and result is by default stored
in AL. Eg. 95H and 6FH ; the result is 104H). Now 104H is 12 bits and size of AL register is 8 bits.
Hence it indicates that a carry is generated which needs to be reflected somewhere, so we are
reflecting in the carry flag.
Therefore when CF = 1; carry is generated
CF = 0; carry not generated
Similarly for 16 bit addition we use the instruction ADD AX,BX (the contents of AX and BX will be
added and result will be stored in AX by default). If the result goes beyond 16 bits it means that a
carry is generated which will be reflected by the carry flag, it means that it will set.
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BY UBAID SAUDAGAR
53
Carry flag cont..

The carry flag is also used to reflect the result of subtraction.
Eg: 8 bit subtraction
We use the instruction SUB AL,BL (the operation performed is AL BL and result is stored
in register AL)
Now if AL >= BL then there is no borrow Eg. 35H 34H therefore CF = 0; reset
Now if AL < BL then a borrow is required Eg. 34H 35H therefore CF = 1; set
Similarly for 16 bit subtraction we use the instruction SUB AX,BX (the operation
performed is AX - BX and result is stored in AX).
Now if AX >= BX then there is no borrow Eg. 3500H 3400H therefore CF = 0; reset
Now if AX < BX then a borrow is required Eg. 3400H 3500H therefore CF = 1; set
Therefore the carry flag reflects the result on subtraction operation.
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BY UBAID SAUDAGAR
54
Auxiliary carry flag (Bit 5)

Type: Status Flag
Operation: During an addition operation if a carry is generated from the lower nibble to
the higher nibble, then AC flag sets. In other words that carry is stored in the Auxiliary
carry flag bit i.e. Bit 5, or we can say that the carry which is generated from the lower
nibble to the higher nibble is reflected in Bit No.5 ofThis
thecarry
flag which
register.
is
Eg: 8 bit addition
Instruction ADD AL,BL is executed
111
1
Carry
11
generated from the lower

nibble to higher is called
as AC and it is stored in
BIT no. 5 of flag register
AL = 45H = 0100 Lower

0101 nibbles
BL = 5BH = 0101 1011
ADD
= 1010 0000
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BY UBAID SAUDAGAR
55
Auxiliary carry flag cont..

SUB AL,BL instruction is executed.
1
Let AL = 10H = 0001 0000
Borrow taken
from the
higher nibble
BL = 18H = 0001 1000

SUB =
1000
As we see above that a borrow is taken from the higher nibble. As soon as the borrow is
taken from the higher nibble the AC flag sets i.e. AC = 1
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BY UBAID SAUDAGAR
56
Parity flag (Bit 3)

Type: Status flag
Operation: When an addition, subtraction, multiplication, division or any logical operation takes place
then depending on the result the parity flag gets affected.
p checks the 8 LSBs of the result:
If the number of ones in the 8 LSBs are 0/2/4/6/8 then the parity flag sets i.e. PF = 1 indicating even
parity
If the number of ones in the 8 LSBs are 1/3/5/7 then the parity flag resets i.e. PF = 0 indicating odd parity
Eg: Let AX = 1002H
p checks
these 8 bits
BX = 2008H
ADD AX,BX instruction is executed. The result obtained is 300AH (0011 0000 0000 1010) which is stored in
AX register.
Now p will check only the last 8 bits of the result
Here It came to know that No. of 1s are 2 which is even hence PF = 1
1/15/16
BY UBAID SAUDAGAR
57
Zero flag (Bit 7)

Type: Status Flag
Operation: Whenever any arithmetic or logical operation takes place and the result is 0
then zero flag sets to indicate that the result is 0 i.e. ZF = 1
Eg: Let AL = 80H
BL = 80H
SUB AL,BL instruction is executed. The result obtained is 00H in AL register. When p
checks this it has to reflect it somewhere that the result is zero, so it reflects in bit 7
which is reserved for zero flag by setting its value to 1 i.e. ZF = 1
Similarly for 16 bit operations, when the result is 0000H. ZF sets i.e. ZF = 1
Else it is always 0 i.e. ZF = 0
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BY UBAID SAUDAGAR
58
Sign flag (Bit 8)

Type: Status flag
Operation: Whenever the result of any arithmetic operation is negative the sign flag
sets i.e. SF = 1
This borrow
SUB
comes from
1 AL,BL instruction is executed
sign flag
111 1 1
AL = 94H = 1 0 0 1 0 1 0 0
11110 011 0 1 1 0
BL = 96H1 =
SUB
= 1 1 1 1 1 1 1 0 = FEH
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BY UBAID SAUDAGAR
59
Sign flag cont..

As we see above that AL < BL answer is negative which is indicated by the sign flag.
Whenever a borrow is
required by the MSB bit it indicates that answer is negative, hence sign flag sets and
borrow to the MSB is given
from the sign flag bit i.e. bit 8 in the flag register.
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BY UBAID SAUDAGAR
60
Overflow flag (Bit 12)

Type: Status flag
Operation: Whenever an arithmetic or logical operation takes place and the result which
gets stored in any of the registers goes out of range then the Overflow Flag sets to 1 i.e.
OF = 1
Eg: 8 bit addition
The result is 12 bits and AL
ADD AL,BL instruction is executed and the result will be by default stored in the AL
= 8 bits hence when a carry
register (size of AL = 8 bits)
is generated form the MSB
AL = 89H = 1000 1001
BL = 89H = 1000 1001
indicating that the result is

long enough to fit in the AL
register hence OF sets
ADD = 0001 0001 0010
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BY UBAID SAUDAGAR
61
Interrupt flag (Bit 10)

Type: Control flag
Operation: Interrupt flag is used to control the maskable interrupts of the p 8086 which arrive at the INTR
pin. Lets see how it controls the interrupts.
INTR pin
To INTR circuit
IF
Shown above is the internal circuitry to control the maskable interrupts. When Bit 10 of Flag register is 0 i.e.
IF = 0, input to the AND gate is 0 therefore o/p of AND gate goes low. Therefore any input to the AND gate
wont be recognized hence any interrupt occurring on the INTR pin wont be acknowledged as it is not
recognized.
When IF = 1 and interrupt on the INTR pin occurs it is recognized and given to the internal INTR circuitry
through AND gate and then acknowledged.
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BY UBAID SAUDAGAR
62
Trap Flag (Bit 9)

Type: Control Flag
Operation: This flag is used to detect any error in the program (debugging) by executing the
program in single stepping mode.
- If logic 0 is stored in TF, then the p will execute all the instructions of a program in one
operation (free run operation)
Eg: When we execute the program and press key F9, the entire program gets executed in one
stroke. The imp. Point to understand is that when we press the key F9, value 0 gets placed bit
9 of the flag register therefore Trap flag resets i.e. TF = 0.
- If logic 1 is stored in TF, then the p will execute one instruction of the program at a time,
after executing each instruction p will execute INT1 (software interrupt), so p will branch
from main program to subroutine.
The subroutine has a program which displays the result in different registers of p on the
screen, so after each instruction the programmer can verify the result.
Eg: We use F8 function key to execute the program in single stepping mode. When we press
BY UBAID
SAUDAGAR hence trap flag sets i.e. TF = 1
63
key F81/15/16
value 1 gets placed into bit 9 of flag
register,
Direction Flag (Bit 11 )

Memor
Type: Control Flag
y
Operation: To understand the operation lets take an example:
block
Offset
address
placed in
SI register
DS : 0000
40H
ES : 0000
DS : 0001
53H
ES : 0001
DS : 0002
87H
Memor
y
block
ES : 0002
Offset
ES : 0003
DS : 0003 98H
address
placed in DI
register
In the above example we see two memory blocks. The offset address of first memory block is
placed in the SI register and offset address of the second memory block is placed in the DI register.
Now we need to manually increment SI and DI after each byte transfer from data segment to extra
segment.
1/15/16
BY UBAID SAUDAGAR
64
Direction Flag cont..

To avoid all this what we do is after moving one byte from Data segment to extra
segment we clear the direction flag (CLD instruction is used to clear the direction flag)
which puts SI and DI in auto increment mode.
In other words whenever DF = 0, SI and DI increment automatically.
If we are copying the data from the last location we set the direction flag (STD instruction
is used to set the direction flag) which puts the SI and DI in auto decrement mode.
OA
In
other words whenever DF = 1,OA
SI and DI decrement automatically.
OA
OA
Source memory block

1/15/16
Destination memory block

BY UBAID SAUDAGAR
65
Arithmetic Logic Unit (ALU)

In digital techniques we have seen that to add two single bit numbers we used half adder, then to add two
single bit numbers along with carry we used full adder.
Similarly we designed half and full subtractor and so on. Hence for different arithmetic calculations different
ckts have to be designed.
Similarly logic operations such as AND, OR, NOT etc. we required different ICs like for AND gate we require IC
7408 and so on for other ICs.
Therefore for performing arithmetic and logical operations different ckts were designed and used which is
very much bulky.
Microprocessor has a unit called as ALU (arithmetic and logic unit) which does all the arithmetic and logical
operations which we do with the help of so many ckts.
The different operations performed by the ALU are: Addition, Subtraction, Multiplication, Division etc. and
ANDing, ORing etc.
The size of the ALU is 16 bits which means that the data coming from the memory to the p which is in
general 16 bits, that 16 bit data can be processed at a time i.e. in one clock cycle that data can be processed.
Hence the size of the ALU defines how many bit processor. Size of ALU = n ; Processor = n bits
1/15/16
BY UBAID SAUDAGAR
66
6 byte instruction queue register

Why is the 8086 queue only six bytes long?
As we know that the longest instruction in the instruction set of 8086 is six bytes long.
Hence with a six bytes long queue it is possible to prefetch even the longest instruction in
the instruction set.
1/15/16
BY UBAID SAUDAGAR
67

In general what happens in 8085 is that there is a microprocessor and memory.
Memory contains opcodes and operands.
With the help of Opcodes we come to know two things: how many byte instruction and
what operation is to be performed.
Eg: MVI A, 32H
Now this instruction is a two byte instruction, first byte is opcodes and second is operand
which is stored in the memory as follows:
3EH
1000H
32H
1001H
Random
address
Memory
1/15/16
BY UBAID SAUDAGAR
68

Now the p fetches 3EH first from the location 1000H, and brings it into the p where it is decoded.
When 3EH is decoded, what it comes to know that it is a two byte instruction and second that it needs
to move immediate data 32H into the accumulator.
So after decoding it again goes back to memory and fetches 32H and this 32H after being decoded as
data is moved to the Accumulator.
We notice that when it was being decoded at that the data bus, address bus was idle, it has no work,
and further what we notice Is that, after decoding again the p has to go to the memory and fetch data.
So this wastes a lot of time of the p.
This is a simple example of a car manufacturer which defines a person to make a car. Now that person
starts making the engine, then on its completion, he starts preparing the outer body and continues.
We need to understand is that the person is completing one task and then starting another, hence to
manufacture one car will take a lot of time.
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BY UBAID SAUDAGAR
69

The manufacturer came up with an idea, that why not increase my staff. Instead of one
staff Ill make it 5.
First : Engine manufacture
Second : Body manufacture
Third : Seat manufacture
Fourth : Painting
Fifth : Tyre manufacture
Now what happens that the work got divided and each person is busy. After completion of
first module it goes to second and so on till the fifth.
So every module is continuously busy, and the work got divided.
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BY UBAID SAUDAGAR
70

M1
M2
M3
M4
M5
0.2sec
(T1)
This is called
as parallel
processing
0.2sec
(T2)
0.2sec
(T1)
0.2sec
(T3)
0.2sec
(T2)
0.2sec
(T1)
0.2sec
(T4)
0.2sec
(T3)
0.2sec
(T2)
TOTAL TIME = 1sec

TOTAL TIME = 0.2 sec
0.2sec
(T1)
TOTAL TIME = 0.2 sec
0.2sec
0.2sec
0.2sec
0.2sec
0.2sec
1 person can do the work (T5)
in 1 sec, now
but
first time all the
(T4) the work
(T3) got divided,
(T2)
(T1)
modules are in wait state0.2sec

and waiting
for the
previous
one to complete
i.e. M2 is
0.2sec
0.2sec
0.2sec
0.2sec
waiting for M1 to complete.
So time(T5)
taken is (T4)
same i.e. (T3)
1s. But after
(T6)
(T2) the entire cycle is
complete once, now the 0.2sec
time taken
is only 0.2
sec. 0.2sec
0.2sec
0.2sec
0.2sec
1/15/16
(T7)
(T6)
(T5)
BY UBAID SAUDAGAR
(T4)
(T3)
71

Similarly in the microprocessor 8086 it has created a queue register of 6 bytes.
This queue is based on FIFO (first in first out) basis which means that the byte which
comes first also goes out first from this register.
From memory
Byte 6
Byte 5
Byte 4
Byte 3
First in
first out
Byte 2
Byte 1
To execution unit (For Decoding and Execution)
1/15/16
BY UBAID SAUDAGAR
72

p 8086 has created 2 logical units within its architecture one is the bus interface unit
(BIU) and the other is the execution unit (EU).
While the EU is decoding an instruction or executing an instruction which does not require
the use of buses, the BIU fetches upto six bytes from the memory.
The BIU stores these prefetch bytes in FIFO register called as queue register.
When the EU is ready for the next instruction it simply takes (fetches) the next byte from
the instruction queue in the BIU.
This is much faster than sending out address to the system memory and waiting for
memory to send back the next instruction bytes.
Drawback: The only drawback of the queue is when a branch instruction comes in the
queue:
Lets understand with an example:
1/15/16
BY UBAID SAUDAGAR
73

Suppose an instruction is at the address 3000H
Address at which it is
3000H : JMP 8000
going to jump
The
BIU fetches inst. from the memory and keeps in the queue, it fetches 6 bytes
Address at
which
and keeps in the queue.
instruction lies
4CH
Memory
00H
3000H
3001H
80H
3002H
56H
3003H
67H
3004H
7AH
3005H
69H
7AH
Assuming
that 4CH is
opcode for
JUMP instr.
67H
56H
80H
00H
4CH
TO EXECUTION UNIT
1/15/16
BY UBAID SAUDAGAR
74

When 4CH goes to the execution unit, there it is decoded where the p comes to know
that it is a three byte instruction and second thing that it has to do jump operation.
Since when 4CH was decoded and p came to know that it is a three byte instr. and jump
instruction hence p wants the address where to jump. So it fetches more two bytes i.e.
00H and 80H from the queue and decodes them as address.
During their decoding process queue is again full with 6 bytes.
Now the IP jumps to address 8000H to fetch instructions from that location.
The bytes which had been prefetched in the queue are now of no use and are thus
flushed.
Therefore the same process starts again as explained before.
1/15/16
BY UBAID SAUDAGAR
75
What is pipelining ?
When one instruction is getting decoded and executed and simultaneously next instruction is being
fetched from the memory is called as pipelining process.
In 8086 with the help of queue register 6 instruction bytes are prefetched in the queue register, whenever
the EU requires bytes for decoding and execution purpose it just has to fetch from the queue register
instead of going to the main memory and waist its time.
By the time it is decoding and executing the byte fetched from the queue, p does not allow the buses to
remain idle, the external bus goes to the memory and fetches the next bytes and places in the queue.
This is actually parallel processing and similar to a water pipe where the water continues to remain in
motion. Similar way the instruction bytes are in continuous motion i.e. from the memory to the BIU then
into the queue then to the execution unit for execution.
In other words the motion of bytes does not stop anywhere ideally unless and until a branch instruction
arises in the queue.
Note: The p does not perform the next fetch operation till at least two bytes of the instruction queue are
emptied.
1/15/16
BY UBAID SAUDAGAR
76
Pipelining process
Here we can see that there
Is a pipeline structure
Memory
BIU
t has a two stage pipeline

1. Fetch stage (prefetches upto 6 bytes)
2. Decode and Execute stage (where)
nstructions are decoded and executed
Execution unit
6
5
4
3
2
1
6 bytes queue
1/15/16
BY UBAID SAUDAGAR
77
Signal description (Pin description)
1/15/16
BY UBAID SAUDAGAR
78
Pin diagram of 8086 p

Vcc
GND
GND
40
1
20
CLK
RESET
READY
19
21
22
NMI
INTR
17
18
TEST
MN/MX
1/15/16
16 -2, 39
38 - 35
/-/
8086
p
23
33
BY UBAID SAUDAGAR
34
32
BHE/
RD
31
30
29
26
27
28
25
24
Minimum
mode
pins
Maximum
mode pins
HOLD
HLDA
WR
DEN
DT/R
M/ IO
ALE
INTA
/
/
LOCK
79
Pin configuration
8086 is 16 bit p available in three clock rates 5, 8, and 10 MHz and is a 40 pin ic.
It works in two modes minimum mode and maximum mode.
The pins on the p 8086 can be categorized into 3 types:
1. Pins common to minimum and maximum mode
2. Minimum mode pins
3. Maximum mode pins
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BY UBAID SAUDAGAR
80
(Pin 16 - 2) - Multiplexed
Address Data Bus
From pin number 16 2 are used by the multiplexed address data bus.
Multiplexing address and data lines means that the same lines are used for address and
data. Therefore the same lines are used to carry address information as well as data.
During T1 state of every machine cycle ALE signal goes high and enables the latches,
during this T1 state address which is generated by the p is available on this multiplexed
bus.
After T1 state gets over ALE signal goes low which disables the latches and DEN signal
also goes low which enables the Transrecievers. Now data is available on the multiplexed
bus.
Refer concept of latch
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BY UBAID SAUDAGAR
81
- (Pin 38 35)
These lines work as Address Bus (A16 A19) during T1 state of every machine cycle i.e.
when ALE signal goes high.
T2 onwards these work as status signals S3 to S6
S3 and S4 gives the status of the memory segment currently accessed.
S5 gives the status of Interrupt Flag.
S6 remains low in general.
Segment accessed
1/15/16
Extra segment
Stack segment
Code segment
Data segment
BY UBAID SAUDAGAR
82
Interrupt basics
What is an interrupt?
An interrupt is an external signal to the p which breaks the normal sequence of the program running in
the p.
For Eg. A person is reading a book and while reading he hears the door bell so what he does is that he
puts a bookmark in the book and goes and opens the door, receives the request from the person standing
on the door and then comes back.
Now it depends who has arrived on the door, if a non important person is there then he can tell him to
wait or ignore. But if an imp. person is there whom he cannot avoid, then he has to compulsory respond.
Similarly there are two types of interrupts one maskable (can be avoided) and the other non maskable
(cannot be avoided)
Another Eg. Is of gas detector (at any how it is going to detect the gas (non - maskable)), and a mobile
phone (if a non important call is there user can avoid it and if an important call is there user will accept it)
p 8086 consist of two interrupt pins i.e. NMI and INTR and one acknowledge pin INTA
Instead of being wired directly to the CPU, the interrupts from the external devices are channeled through
Programmable interrupt controller (PIC 8259).
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BY UBAID SAUDAGAR
83
Interrupt pins (INTR, NMI, INTA)
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BY UBAID SAUDAGAR
84
INTR (Pin 18):

This is input pin to the microprocessor.
It is an interrupt pin and the input is level triggered, which means that when logic high
arrives on this pin it gets activated.
An interrupting device such as keyboard, printer etc. is not directly connected to this pin but
through a PIC (IC 8259).
Interrupts arriving on this pin can be masked with the help of IF flag.
Initially the interrupt flag (IF) is in the set state so that any interrupt which arrives to the
microprocessor gets response i.e. the interrupt is unmasked (allowed).
When the instruction CLI is executed, IF flag gets cleared and interrupts arriving on this pin
are masked (they dont get any response).
When one interrupt is getting response from the processor (i.e. processor is executing ISR),
CLI instruction is executed so that no other device may interrupt the processor
1/15/16
BY UBAID SAUDAGAR
85
NMI (Pin 17)

This is an input pin to the p .
It is a positive edge triggered input.
It is a non maskable interrupt.
For any interrupt to be recognized the i/p at this pin should be high for at least 2 clock
cycles
Whenever there is a power failure this pin comes into use.
1/15/16
BY UBAID SAUDAGAR
86
INTA (Pin 24)

This is an acknowledge signal going out from the p to the PIC (IC 8259).
Whenever the p is interrupted on the INTR pin with a high signal, if the p accepts the
interrupt which means that the IF is set, it sends an acknowledgement signal to the PIC
from where the interrupt came, indicating that it has accepted the interrupt.
1/15/16
BY UBAID SAUDAGAR
87
RD (Pin 32) Read

This is an active low pin
It is an output pin. Whenever the p performs memory read or i/o read operation, this pin
goes low to indicate read operation. This pin is always used along with M/IO to indicate
memory read or I/O read.
RD
OE (o/p
enable)
Microprocess
Memory
or
Data from the memory goes to the p
1/15/16
BY UBAID SAUDAGAR
88
READY (Pin 22)

This is an input acknowledgement signal from the slow peripheral devices to the
microprocessor to indicate that data transfer is complete.
Eg. Printer connected to microprocessor.
The main use of this pin is to insert wait states into the timing of the microprocessor.
If the READY pin is at logic 0 level, the p enters wait states into its timing cycle and
remains idle.
The need for this is because the speed of the p is very fast, it operates in MHz and speed
of peripheral device like printer is slow as compared to that of the p. Hence p sends
data at a faster rate continuously to the peripheral, which may cause loss of data, hence
the peripheral sends a low signal on the READY input to send the data at a slower rate by
adding wait states to its timing cycle.
Once one slot of data is received by the peripheral then it sends an acknowledgement
high signal
on its input to indicate that data
transfer is complete and send the next slot of
1/15/16
BY UBAID SAUDAGAR
89
CLK (Pin 19) Clock

Clock pin provides the basic timing signal to the microprocessor.
chmitt trigger
IC 8284
onverting sine wave
Clock generator
nto square wave
T
f/f
X2
X1
CLK
Microprocessor
Crystal oscillator
1/15/16
BY UBAID SAUDAGAR
The crystal oscillator produces

sinusoidal oscillations.
We assume that the crystal
frequency = 10 MHz
Schmitt trigger converts this sine
wave into
square wave
T f/f divides the crystal frequency by
2
This frequency is applied to the p
which will be the
Operating frequency of the p
Therefore OF of p = 5 MHz
90
Vcc (Pin 40) ; GND (Pin 1 and 20)

Vcc i.e. +5V is applied at pin 40 and is used as power supply
There are two layers of 8086, hence two separate GND pins for two layers of 8086 chip
are used
This helps in improve noise rejection
1/15/16
BY UBAID SAUDAGAR
91
RESET (Pin 21)

It causes the processor to immediately terminate its present activity .
The 8284 clock generator provides this signal. This signal must be active high for at least 4 clock cycles
It clears all the flag register, the instruction queue, DS,SS, ES and IP register and sets the bits of the CS register
Hence whenever the processor boots the reset vector address of 8086 is FFFF0H (as CS = FFFFH and IP = 0000H)
Note: The reset vector is the default location a central processing unit will go to find the first instruction it will
execute after a reset. That is to say, the reset vector is a pointer or address where the CPU should always begin as
soon as it is able to execute instructions.
The system designer will store the monitor program starting from the address FFFF0H. The monitor program should
be executed to initialize system peripherals whenever the system is switched ON. To enable automatic execution of
monitor program, Whenever the system is switched ON, the EPROM should be mapped at the end of memory space in
8086-based system. Monitor program is a permanent program written by the system designer to take care of system
initializations. The system initializations includes the following.
1. Programming 8279 for keyboard scanning and display refreshing.
2. Programming peripheral ICs 8259,8257,8255,8251,8254,etc.,.
3. Initializing stack.
4. Display a message on display (output) device.
1/15/16
BY UBAID SAUDAGAR
92
Concept of latch
As we have learned the concept of f/f . What we have noticed that in some f/fs that
whatever we give them the input they store that input at their o/p.
A simple example is of a D f/f, where when we apply a logic 1 at its input that logic 1
appears at the o/p and doesnt change unless and until next clock appears.
Logic 0 at i/p
CLK
1/15/16
Logic 0 at o/p
Flip Flop or
Latch
BY UBAID SAUDAGAR
93
Concept of latch
So in general what we can say that it stores that 1 bit at its o/p or it holds this value at its
o/p, therefore we can also term it as a D latch.
A latch is nothing but a f/f but basically used to hold values at its o/p for other devices.
Now an Octal (Eight) Latch is a device with eight D f/fs.
Its IC number is 8282 . It has an i/p pin STB which is active high and when logic 1 is applied
to it activates the IC and i/ps are applied to all the latches and correspondingly o/ps appear
at the o/p.
Now lets understand why we require octal latch:
No. of address lines = 20
No. of data lines = 16
Now these 16 lines are multiplexed with 16 address lines and these are time multiplexed.
1/15/16
BY UBAID SAUDAGAR
94
Concept of latch
Multiplexing address and data lines means that the same lines are used for address and
data.
Therefore the same lines are used to carry address information as well as data.
The remaining address lines are multiplexed with 4 status signals (S3 S6)
Lets understand this multiplexing with the help of a simple multiplexer diagram :
Address
Data
2 : 1 MUX
Address or Data depending upon ALE
When ALE = 1, it selects address and makes it available at the o

When ALE = 0, it selects data and makes it available at the o/p
1/15/16
BY UBAID SAUDAGAR
95
Concept of latch and machine cycle

ALE is an o/p signal from the p which goes to the octal latch to make it active.
Since we know that the multiplexing is time multiplexing hence ALE becomes high for a
short duration and then becomes low.
Now we need to understand when does it become high and low.
- Crystal frequency = 10 MHz (assumption)
- Operating frequency = 5 MHz
- Time period of each clock pulse = 1/(5 * ) = 0.2 s = 1T state
-------
-------
1 T state
= 0.2 sec
1/15/16
BY UBAID SAUDAGAR
96

Now many T states together form 1 machine cycle and one instruction consist of many
machine cycle.
For Eg. Consider the instruction MVI A, 32H
This instruction is of 2 bytes viz. first byte is the opcode and second is the operand.
For this instruction 2 machine cycles are required viz. opcode fetch machine cycle
and memory read machine cycle.
To fetch the opcode from the memory it requires 4 T states (T1, T2, T3, T4) = 0.8 s
To fetch the operand from the memory it requires 3 T states (T1, T2, T3) = 0.6 sec
Therefore total time to execute an instruction = 1.4 s
The main aim to clear the concept of T state and machine cycle is that during T1 state
of every machine cycle ALE goes high and that moment of time address is available
on the1/15/16
multiplexed address and data bus.
BY UBAID SAUDAGAR
97

Now this ALE is connected to STB pin of the octal latch, and the multiplexed 8 lines are
connected to octal latch
Since its an octal latch hence only 8 lines can be connected to it, therefore we require 3
octal latches.
ALE
STB
Three
the connection
- is as follows:
octal
/ - /(8 bit) latches are required,
8282
Multiplexed
Microprocesso Address
r
and
Data bus
1/15/16
STB
8282
STB
8282
BY UBAID SAUDAGAR
20 bit address generated to access

Memory or I/O device
98
How address gets latched?

In the above figure we see that there are three external octal latches.
The ALE signal is connected with the strobe input (STB i/p) of the latches which enables
the latches and loads the address into the latches.
Since each latch is of 8 bits hence we have to use 3 latches to latch 20 bit address.
This is the
ALE
/-/
-
Microproces
sor
1/15/16
20 bit address
3EH
32H
Octal
latche
s
Data bus
BY UBAID SAUDAGAR
opcode
fetched
during first
machine
cycle
This is the
data fetched
during
second
machine
cycle
99
How address gets latched?

Consider the instruction MVI A,32H is executed.
This instruction is a 2 byte instruction and has two machine cycles. First machine cycle
has 4 T states and second machine cycle has 3 T states.
On T1 state of every machine cycle ALE goes high and enables the latches. The addresses
is available on the multiplexed bus for this T1 state and then disappears.
Therefore in order to save our address so that it doesn't get lost we use latches which
latch the address at its o/p (which means that it holds the address at its o/p).
This is because when T2 begins, ALE becomes low, latches gets disabled and data is
available on the multiplexed bus.
Since latches are disabled they do not respond to data appearing on the bus, and address
is available on their o/p with which the proper memory location is accessed.
1/15/16
BY UBAID SAUDAGAR
100
ALE (Pin 25)

ALE stands for Address Latch Enable.
As we studied in the previous slides about latch. Latch has an input pin STB which is
connected to the o/p pin of the p i.e. ALE
As the name suggests, it is used to enable the latch by generating a high signal during T1
state of every machine cycle.
As soon as ALE pin goes high, latches gets enabled, address which is available on the
address bus goes to the input of the latches where it is latched (it holds the address at its
o/p).
Now ALE goes low after T1 state gets over, hence disabling the latches (as STB also goes
low).
Now data is available on the multiplexed A/D bus.
Since latches are disabled hence data which arrives at latches get no response.
1/15/16
BY UBAID SAUDAGAR
101
Concept of Numeric Processor 8087

A system having two microprocessor will require only lesser time to complete the task.
Using a general-purpose microprocessor such as the 8086 to perform mathematical functions such as
log, sine, and others is very time consuming, not only for the CPU but also for programmers writing such
programs.
In the absence of a math coprocessor, programmers must write subroutines using 8086 instructions for
mathematical functions.
You may take a normal example of simple calculator and a scientific calculator.
In a simple calculator normal calculations takes place, but in scientific calculator apart from the normal
calculations, log, sine, cos and many other calculations are present.
For performing those complicated calculations numeric processor is designed and Operation of 8087
does not require any software support from the system software or operating system.
They are Unable to fetch the code from the memory so they work under the control of main processor .
The 8087 instruction may lie interleaved in the 8086 program, but it is the task of 8086 to identify the
8087 instructions from the program, send it to 8087 for further execution & after the completion of
execution cycle the result may be referred back to CPU.
1/15/16
BY UBAID SAUDAGAR
102
TEST (Pin 23)

It is an active low input line dedicated for 8087 math co processor(numeric processor).
When this pin is high in the maximum mode, it indicates to the microprocessor that it is
busy.
Whenever those instructions arrive in the program which are dedicated to the co
processor then they are sent to the co processor for execution.
While the co processor is busy executing those instructions it sends a high signal on the
TEST pin of the p indicating that it is busy executing those instructions, till then the p
remains in idle state.
1/15/16
BY UBAID SAUDAGAR
103
MN/MX (Pin 33)

This is an input pin to the p which will indicate the processor will work in which mode.
If input to this pin is high i.e. if the pin is connected to Vcc (+5V) then p will enter in
minimum mode
If input to this pin is low i.e. if the pin is connected to GND (0V) then p will enter in
maximum mode
1/15/16
BY UBAID SAUDAGAR
104
Concept of Memory Banking

NEED :
We know that our microprocessor is 16 bit microprocessor, hence it has 16 data lines, it means that
16 bit data can be accessed and processed from the memory in 1 machine cycle.
But we have seen that a memory chip has n locations and each location has 8 bits, therefore only 8
bit data bus can be connected to the memory chip.
Since only 8 bit data bus can be connected hence only 8 bit data can be accessed at a time.
Therefore in 1 machine cycle only 8 bit data can be accessed and processed.
Therefore it will behave as an 8 bit processor.
So to avoid this the entire 1 Mb memory is divided into two banks viz. odd bank and even bank.
Note: The 8086 microprocessor has 20 address lines and with the help of these 20 lines we can
address 1 Mb of memory.
Each bank will have a capacity of 512 Kb (odd + even bank = 512 Kb + 512 Kb = 1 Mb)
1/15/16
BY UBAID SAUDAGAR
105

00000H 1010 1011
00002H 1011 1100
All even addresses
In even bank
FFFFAH
0101 1010
FFFFCH
0011 0101
FFFFEH
0011 1100
8 bit data
Even bank
at every
location
OVERVIEW :
1/15/16
00001H 1000 1001

00003H 0111 1000
FFFFBH
FFFFDH
FFFFFH
All odd addresses

In odd bank
0101 0110
0010 0011
0001 0010
Odd bank
BY UBAID SAUDAGAR
8 bit data
at every
location
106
NNECTION OF ADDRESS AND DATA BUS :

Since
the memory size reduces to 512 Kb each, hence address bus size also reduces as follows:
No. of address lines required to access 512 Kb = ; where x is the no. of address lines
We replace x by 19 therefore = 524288 locations and at each location 1 byte = 524288 bytes == 512 Kb
Address Bus
Even Memory
Bank
Address Bus
Data Bus
Data Bus
1/15/16
Odd Memory
Bank
BY UBAID SAUDAGAR
107
LECTION OF MEMORY BANKS :

As we know that only 19 address lines are required to access memory banks, 1 address line is left.
With the help of the previous diagram we understood how address and data bus is connected to the
memory banks. Now we need to understand how this memory banks are enabled and disabled.
A0
BHE
Even
Memory
Bank
Odd
Memory
Bank
CS
CS
Microprocessor
8086
1/15/16
BY UBAID SAUDAGAR
108

In the above figure we see that the address line A0 is not used for addressing purpose but
used for chip selection. The chip select on the memory is active low hence when A0 is low,
lower memory bank or even bank gets selected.
To select the odd bank or higher memory bank an o/p signal BHE is used. When this pin
goes low odd memory bank or higher memory bank gets selected.
We need to now understand how addressing takes place.
Refer next slide
1/15/16
BY UBAID SAUDAGAR
109

A1
9
A1
8
A1
7
A1
6
A1
5
A1
4
A1
3
A1
2
A1
1
A1
0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BH
E
A0
BHE
A1 A19
ADDRESS BUS
DO D7
1/15/16
00001H
3EH
4FH
00003H
4AH
5CH
00005H
9CH
00000H
00002H
00004H
6BH
8086
D8 D15
34H
FFFFFH
54H
FFFFEH
DATA BUS
ADDRESS BUS
DATA BUS
BY UBAID SAUDAGAR
110
DDRESSING THE MEMORY BANKS :
From the above diagram and table what we see is that, the address lines are connected to
both the banks simultaneously.
The lower order data lines (D0 D7) are connected to lower memory bank and higher
order data lines (D8 D15) are connected to higher memory bank.
Consider the 1st row in the table, where we see that A0 and BHE, both are low
hence both the banks are enabled.
Now the address from A19 A1 = 0000000000000000000, this address will select the 0 th
location of both the banks, since both the banks are enabled data will be loaded to both
the memory banks in case of write operation or data will be loaded from both the memory
banks to the data buses in case of read operation.
Consider the 2nd row in the table, where we see that A0 is 0 and BHE is 1,
therefore lower bank is enabled and higher bank is disabled.
1/15/16
BY UBAID SAUDAGAR
111

Now the address from A19 A1 = 0000000000000000001, this address will select the 1 st
location of both the banks, but since lower bank is enabled and higher bank is disabled
therefore data will be loaded only from the lower memory bank onto the lower order data
bus or vice versa in case of read or write operation.
Consider the 3rd row in the table, where we see that A0 is 1 and BHE is 0,
therefore lower bank is disabled and higher bank is enabled.
Now the address from A19 A1 = 0000000000000000010, this address will select the 2 nd
location of both the banks, but since lower bank is disabled and higher bank is enabled
therefore data will be loaded only from the higher memory bank onto the higher order
data bus or vice versa in case of read or write operation.
1/15/16
BY UBAID SAUDAGAR
112
CESSING WORDS AND BYTES FROM BANKS :
As we discussed before that our main aim of memory banking is that the microprocessor
should be able to access 16 bits i.e. 2 bytes i.e. 1 word at a time and process it in 1
machine cycle.
But depending upon instruction and address it accesses bytes or words.
Consider the table on next slide
1/15/16
BY UBAID SAUDAGAR
113

INSTRUCTION
ADDRESS
DATA TYPE
BHE
A0
MACHINE
CYCLE
DATA LINES
USED
MOV AL,
[0000H]
0000H
BYTE
ONE
D0 D7
MOV AX,
[0000H]
0000H
WORD
ONE
D0 D15
MOV AL,
[0001H]
0001H
BYTE
ONE
D8 D15
WORD
0
1
MOV AX,
0001H
[0001H]
Byte
is accessed in one
machine cycle as this
instruction is accessing a
byte from even memory
location. Hence even
bank is enabled and odd
bank is disabled and
data is available on the
lower order data bus D0 D7
1/15/16
Word is accessed in one

instruction is accessing a
word from even memory
location. Hence even and
odd bank both are
enabled to and data is
available on the lower
order data bus D0 - D7
1
FIRST
D8 D15
0
D0 D7
Byte is accessed
in one SECOND
Word is accessed in two
machine cycles. This inst.
instruction is accessing
Is accessing a word
a byte from odd memory
starting from the odd
location. Hence odd
memory location hence in
the first machine cycle 1
bank is enabled and
byte is accessed from odd
even bank is disabled
bank, in the 2nd machine
and data is available on
cycle 2nd byte is accessed
the higher order data
from even bank
bus D8 D15
BY UBAID SAUDAGAR
114
BHE/ (Pin 34)

is used for future development.
BHE is active low o/p signal and stands for Bus High Enable.
This o/p pin is used to activate the odd memory bank, when the o/p of this pin is low it
activates the odd memory bank and data is available on the higher order data bus (D8
D15)
If this pin goes high then odd memory bank gets disabled and any type of data transfer
from the higher order data bus is disabled.
1/15/16
BY UBAID SAUDAGAR
115
WR Write (Pin 29)

This is an o/p pin is used in minimum mode, i.e. MN/MX = 1
It is connected to the memory or i/o device. When this pin goes low it indicates write
operation.
It is used along with M/IO pin to indicate whether memory write or io write operation.
WR
WR
8086
Microprocess
Memory
or from the microprocessor goes to memory
Data
1/15/16
BY UBAID SAUDAGAR
116
M/IO (Pin 28)

This is an o/p pin used in minimum mode, to distinguish between a memory operation and
io operation.
When this pin is low it indicates io operation and is used with RD and WR.
For Eg. M/IO is high, and RD is also low whereas WR is high, then memory read operation
takes place.
For Eg. M/IO is high, and WR is also low whereas RD is high, then memory write operation
takes place.
WRonly M/IO is low.
In similar manner IO readWR
and IO write operation takes place,
RD
8086
Microprocessor
1/15/16
OE
Data Bus
Memory
BY UBAID SAUDAGAR
117
Concept of DMA (Direct Memory

Access)
Consider that an io device and memory are connected to the p.
Lets consider that a pen drive is connected which will be treated as an io device.
Now bulk data is to be transferred from the main memory to the pen drive.
The procedure will be that the pen drive will access the p, which in turn will perform a read
operation from the memory, then a write operation to the pen drive.
Reads data from the memory
Memory
System Bus
8086
Microprocessor
1/15/16
Writes data to I/O device

System Bus
BY UBAID SAUDAGAR
Data transfer takes place between

I/O device and memory
I/O
device
118

Access)
If the data is small, then going this way is not a big issue . But if data is more, then going
through this method is quite tedious and will take a lot of time.
Secondly ps are not designed just for data transfer from one device to another, going this
way we are wasting the time of the p.
Hence our requirement is that data should be transferred directly between the two devices
without any intervention from the p.
To achieve our requirement Intel designed a controller called as DMA controller which meets
our requirement.
Now what is going to happen that the I/O device gets connected to the DMA controller which
in turn gets connected to the p.
Whenever there is a requirement of data transfer between I/O device and memory, I/O device
sends a request signal to the DMA controller, DMA will send a request signal (HOLD) to the p
to release the system bus.
1/15/16
BY UBAID SAUDAGAR
119

Access)
p will send an acknowledge signal to the DMA that it has released the system bus it
actually means that the system bus from the p side is tri stated.
DMA also sends an acknowledge signal to the I/O device indicating that it has the control
over the system bus. Now data transfer takes place directly between the I/O device and
the memory under DMA control, hence by passing the p and this data transfer takes
place at a higher rate.
By the time data transfer takes
placebus
outside
the from
p, p
may perform
System
tri stated
external
devices some internal
calculation part as external system bus is REQ
tristated.
HOLD
HLDA
REQ
DACK
System Bus
DMA
Controller
8257
Microprocessor
8086
1/15/16
System Bus
BY UBAID SAUDAGAR
System bus tri stated from
I/O
device
Memory
120
HOLD (Pin 31)

It is input pin used in the minimum mode. The i/p comes from the DMA controller which is
acting another bus master (as it also has data and address lines) requesting the p to
release the system bus.
In response 8086 completes the current machine cycle and releases the system bus.
In other words it tristates its external system bus.
1/15/16
BY UBAID SAUDAGAR
121
HLDA (Pin 30)

It is acknowledge signal generated by the p to the DMA controller after releasing the
system bus, indicating that it has released the system bus.
After which DMA operation takes place.
1/15/16
BY UBAID SAUDAGAR
122
Concept of Octal Bus Transrecievers

As we have seen that the octal latch is used to latch the address obtained from the
multiplexed A/D bus during the T1 state.
After T1 state ALE goes low and data is available on the multiplexed A/D bus. This data
cannot be latched as the latches are disabled.
Therefore for driving this data coming from the data bus we require Octal Transrecievers (IC
8286)
Now these Transrecievers contain 8 bidirectional buffers. Lets see what a buffer is.
Input
Output
Shown in the above diagram is the basic diagram of a buffer.

1/15/16
BY UBAID SAUDAGAR
123

It is a single input, single output, non inverting device with gain =1.
As we have seen that, an inverter is a device which is same as a buffer but having a
bubble at the end which inverts the input.
But in case of a buffer if there is 0 at the input there will be 0 at the o/p.
The main important feature of a buffer is that it is used to amplify the current or power.
This is because the o/p current of the microprocessor is very low say few mA like 5mA.
Now the device which it is driving gets activated or gets drived at 50mA. So we require a
device which will amplify the current to drive that device.
Hence buffers are used.
Now there are 8 such buffers present in an octal bus Transreciever.
1/15/16
BY UBAID SAUDAGAR
124

Also the Buffers used are tristated buffers which means that it has three states viz. high,
low and hi z (hi - impedance).
High and low is understood but hi z state i.e. high impedance state effectively removes
the device's influence from the rest of the circuit.
In other words infinite resistance state.
Enable
Input
Output
In the above diagram we see an active high tri state buffer. When the enable i/p is high
the buffer acts normally i.e. allows i/p to appear at the o/p with an increase in current as
current1/15/16
is amplified.
BY UBAID SAUDAGAR
125

But when the enable i/p is 0, the buffer enters in hi z state i.e. it isolates the input from the o/p
Now, an octal Transreciever has bidirectional buffers as follows:
Output A Input A
Input BOutput B
Enable
Enable
As we know that data bus is bidirectional, hence we see that buffers are also bidirectional.
1/15/16
BY UBAID SAUDAGAR
126

Now this octal bus Transreciever consist of such 8 bidirectional buffers.
When data gets transferred between the p and the memory, ALE goes high during T1
state, address gets latched with the help of an 8282 octal latch.
After T1 state gets over, T2 starts, ALE goes low, latches gets disabled, data is now
available on the multiplexed bus.
8086 has an o/p pin DEN which is connected to the OE pin of the Transreciever.
When DEN pin is high Transreciever is inactive, when it becomes low Transreciever gets
activated.
During the T1 state, this pin is high as no data is available on the multiplexed A/D bus,
therefore 8286 is inactive.
As soon as T1 state gets over, DEN pin goes low activating the 8286 Transreciever
As we 1/15/16
know that Data bus is bidirectional
hence there are two possibilities viz. data
BY UBAID SAUDAGAR
127

Now with the help of DEN and OE of p and 8286 Transreciever, the IC gets enabled but
we need to decide the direction of data flow.
Hence there is a pin labelled T on the IC 8286 . When T = 1, flow is from p to memory
and when T = 0, flow is from memory to p.
8086 p has a pin labelled DT/R, when this pin goes high, it indicates data transmit,
therefore data flows from p to memory by making T = 1.
When this pin goes low, it indicates receive, thereby making T = 0, therefore data flows
from memory to p.
We now understand that why we require bi directional buffers.
When T = 1, buffer A gets activated and buffer B is in hi z state.
When T = 0, buffer B gets activated and buffer A is in hi z state.
1/15/16
BY UBAID SAUDAGAR
128
DEN (Pin 26) Data Enable

This pin is used to activate the octal bus Transreciever IC 8286 . It is connected to the OE
pin of the Transreciever which consist of 8 bidirectional buffers. Actually when DEN goes
low OE goes low and all the internal buffers get activated.
OE
DEN
8286
Transreciev
er
Active
low
o/p
OE
Microprocessor
8086
1/15/16
Active
low i/p
8286
Transreciev
er
BY UBAID SAUDAGAR
129
DT/R (Pin 27) Data transmit/ Receive

This pin is used to decide the direction of data flow i.e. either data will flow from the p to memory or io
device or data will flow from the memory or io device to the p.
When this pin goes high i.e. when DT/R = 1, which indicates data transmit from p to memory or io device
In other words whenever write operation takes place, DT/R goes high, hence flow of data is from the p.
When this pin goes low i.e. when DT/R = 0, which indicates receive i.e. p receives data from memory or io
device.
In other words whenever read operation takes place, DT/R goes low, hence flow of data is towards the p.
DT/R
8286
Transreciev
er
1/15/16
8086
Microprocess
or
BY UBAID SAUDAGAR
130
(Pin 28 26) Status lines

These are the active low status lines used in maximum mode which reflect the type of
operation being carried out by the processor. It indicates which machine cycle is currently
in operation.
Refer table below:
1/15/16
Indication
Interrupt acknowledge
Read I/O port
Write I/O port
Halt
Code Access
Read memory
Write memory
Passive
BY UBAID SAUDAGAR
131
LOCK (Pin 29)

This pin is used in the maximum mode.
When a programmer is executing some important instructions during which no interrupt
can be tolerated (such as when we restart our computer and there are some updates
which the windows is taking at that time if any other command is given to the PC it will
not react to it) at that time what the programmer does it writes a LOCK prefix alongside
the instruction, due to which this pin goes low indicating to the external bus masters such
as DMA that it cannot take control over the system bus.
When the next instruction arrives without the LOCK prefix then this pin goes high and
allows other bus masters to access gain over the system bus.
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(Pin 24 25)
QS stands for queue status. It means that outside the chip we come to know what is the
status of the queue register inside the microprocessor.
Lets understand from the table below:
Queue status
0
No operation (All the six registers of the queue are full)
It indicates that the opcode is being executed
The instruction queue is empty, all registers are cleared due to branching
operation
It indicates that operands are being executed
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//
This signal works in the maximum mode when more than one processor is connected in
the system.
RQ stands for bus request. GT stands for bus grant.
0 has the higher priority than 1. It means that when two processors simultaneously asks
the 8086 to release the system bus, the processor which is connected at pin 31 will get
bus grant first then the one which is connected at pin 30.
The external processor will send a low signal as a request to the p to release the system
bus, the p will complete its current machine cycle and release the bus i.e. it will grant the
bus to the bus master by sending a low signal.
After using the system bus again the external bus master will send a low signal thereby
releasing back the system bus to the p.
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Minimum mode configuration
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Minimum mode operation

In minimum mode configuration MN/MX = 1. It consists of 8284 clock generator and reset
circuit.
Three octal latches (IC 8282) are used to demultiplex the address/data lines and 2 octal
Transrecievers (IC 8286) are used as data amplifiers for the transmission of data to the
memory or i/o from the microprocessor and vice versa.
In this mode all the control signals are given out by the microprocessor itself. Only a
single processor is present on the system.
The latches gets activated when the ALE signal from the microprocessor goes high, which
is connected to STB pin of the Octal latch. This allows address to be available on the
output of latch after T1 state.
The Transrecievers have two pins OE and T. The Transrecievers gets activated when it
receives a low signal on the OE pin from the microprocessor pin DEN.
To select
the direction of data DT/R is connected
to T pin of the Transrecievers. When DT/R
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Minimum mode operation

IC 8284 clock generator is used to provide clock signals (timing signals) to the processor
so that all the operations of the processor are properly synchronized and work according
to proper timing signals.
The wait state generator is used to add wait states when a slow peripheral is connected to
the processor.
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IC 8284 (CLOCK GENERATOR)
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IC 8284 (CLOCK GENERATOR)

The 8284 clock generator consist of a reset circuitry which is used to reset the
microprocessor.
When a low signal is applied to the RES pin of the clock generator, it sends a high signal
to the RESET pin of the processor thereby restarting the processor (reboot the processor).
Once booted a logic 1 appears on the RES pin as the capacitor gets charged to +5V.
PCLK i.e. peripheral clock is a timing signal to the peripherals to synchronize their
operations with the processor.
The EFI i.e. external frequency input is used to determine the oscillator frequency.
RDY1 and RDY2 are input signals from the peripherals to the clock generator with RDY1
having higher priority.
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74LS373 (Octal LATCH)
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74LS373 (Octal LATCH)

An octal latch has 8 D-latches and 8 tri-state buffers.
The 74LS373 octal latch has two control inputs Enable (G) and Output Control (OC).
The Enable control is active high and is connected to CLK inputs of all 8 latches. Logic I in
CLK input will store the
logic levels present at D inputs in respective latches.
The Output Control signal is active-low and is connected to control inputs of all 8 tri-state
buffers.
Logic O will enable the buffers to output data from respective latches.
The latch Intel 8282 provides the same functionality of 74LS373
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74LS245 (Bidirectional Buffer)
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74LS245 (Bidirectional Buffer)

We know that 74LS245 is a bi-directional 8-bit buffer.
It has DIR signal to control the direction of data flow.
When DIR signal is low, data flow is from B to A and when it is high data flow is from A to
B.
It also has G signal which when activated enables the buffer.
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8288 Bus controller
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8288 Bus controller

The input to the bus controller are the status signals from the microprocessor in
maximum mode.
The output of the bus controller are the control signals which are required to drive the
latches and Transrecievers.
Also control signals such as MEMR, MEMW, IORD, IOWR are also generated from the bus
controller.
Which signals should be generated depends on the status of the status signals to the bus
controller.
Refer S2,S1,S0 status signals section.
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Maximum mode operation
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Maximum mode operation

As we can see in the block diagram, maximum mode is the mode in which more than one
processor is present on the system.
Therefore the control signals required to drive the latches and Transrecievers are
generated by the bus controller.
Also control signals required for memory selection and io selection are generated by the
bus controller.
The bus controller gets status signals from the microprocessor which gives the status of
the operation to be performed.
The remaining pins which were used in minimum mode but now their functionality
changed in maximum mode are used for request and grant signals to other processors on
the system.
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Real mode memory addressing

8086
operates in the real mode.
It is said to be real mode as it can access only 1 Mb of memory.

Assuming that we have 4 Gb address space, to address 4 Gb locations we require 32
addressing lines therefore = 4294967295 locations = 4 Gb locations
First 1 Mb memory
Therefore the address varies from: called as real

memory
00000000H to FFFFFFFFH i.e.
4 Gb address space
0000 0000 0000 0000 0000 0000 0000 0000 to

1111 1111 1111 1111 1111 1111 1111 1111
Now the first 1 Mb of memory is called as real memory.
8086 is therefore accessing the real memory and the way we will access the real memory
is called as real mode addressing.
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Memory segmentation
The
p 8086 has 20 address lines therefore the number of memory locations it can
access is = 1048576 = 1 Mb.
Therefore consider the memory below:
0000 0001
(01H)
0010 0100
(24H)
Address varies from

0000 0000 0000 0000
0000 1111 1111 1111
1111 1111
1000 1111
(8FH)
1001 1010
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(9AH)
This is the normal way of addressing a memory location

We see that, at every location only
8 bit data is available and it is
stored in hexadecimal form and has
a 20 bit address.
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Memory segmentation cont..

Hence our main aim is to access a memory location and from there access data.
The main point to understand is that the size of the registers is 16 bit and address is of 20 bits.
Therefore 8086 uses the memory segmentation scheme to access 1 Mb of memory or 1M locations.
The memory is divided into segments or blocks. The length of the segment is 64 Kb. Two registers are
used, one to access a segment and one to move within the segment (select any location within the segment).
Consider the memory given on next slide:
Two steps to access any location within a memory:
Select the segment with the help of base address or segment address (starting address (indicating
start of any segment). It means that the segment register contains the base address with the help of which
we are able to select any segment.
Now to move within the segment or in other words to select any location within the segment we use offset
address or effective address which we get from any pointer or index register or any general purpose
register.
Assume base address = 1000H and offset address = 0FFFH .
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Memory segmentation cont..

0th segment
To move within the
segment i.e. to select any
location within the
segment first is to select
the segment, second is to
select any location within
the segment.
1st segment
2nd segment
64 Kb
Base address = 1000H

which selects the segment
Offset address = 0FFFH
Which selects the location 0FFFH
And now from this location data
will be accessed
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8th segment
15th segment
BY UBAID SAUDAGAR
Memory is divided
into 16 segments
and size of every
segment is 64 Kb
= 65536 = 64 Kb
It means that in every segment
there are 65536 locations.
Now we have such 16 segments
and every segment has 65536
locations it means that the total
size of the memory is = 65536 *
16 = 1048576 = 1 Mb
151
Memory segmentation
Now these segments are logical segments, it means that there is no physical division
within the memory.
The segments can either be Code Segment, Data Segment, Extra Segment, Stack
segment.
Code segment : when a segment is assigned as code segment, it is used to store the
codes or instructions
Data Segment : when a segment is assigned as data segment, it is used to store data
used in the programs
Extra Segment : it is also another segment used to store data
Stack Segment : it is used to store stack of data and address of main program during
subroutine call
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Physical address calculation

The No. of address lines in 8086 = 20
Memory accessible = = 1Mb

Scheme of accessing = Segmentation scheme
Memory is divided into 64 Kb logical segments
Whenever a memory is accessed it is accessed using the physical address
In segmentation scheme physical address is calculated using two addresses viz. base
address or segment address and offset address or effective address.
Since address bus is of 20 bits = Physical address is of 20 bits
The calculation is as follows:
Physical address (PA) = BA + EA
But addition is a little different, lets understand with an example:
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Physical address calculation cont..

Let BA = 1000H = 0001 0000 0000 0000 = 16 bit
EA = 3467H = 0011 0100 0110 0111 = 16 bit
Now base address is always appended with 0H i.e. 0000B at the end internally by the
p.
Therefore BA now becomes = 0001 0000 0000 0000 0000 = 10000H
Now,
PA = 0001 0000 0000 0000 0000
+
0011 0100 0110 0111
=
=
10000H
20 bit physical
3467H
address
--------------------------------------------0001 0011 0100 0110 0111 = 13467H

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Now this 20 bit physical address is used to access the memory as:
0000H
0000H
FFFFH
The base and the

offset address can
also written as
4000 : 0023
Physical
address varies
from 00000H
To FFFFFH
Starting
addresses
of
segments
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5000H
0000H
FFFFH
6000H
0000H
FFFFH
F000H
0000H
FFFFH
BY UBAID SAUDAGAR
Physical
address
varies from
00000H to
0FFFFH
Physical
address
varies from
F0000H to
FFFFFH
64 Kb
155

In the above diagram we see that the base address are the starting address of any segment. Now
that segment may be code segment, data segment, extra segment, stack segment.
Hence the base address may vary from 0000H to F000H.
The offset address is also called as displacement. This address is required to select any location
within the segment which has been selected with the help of base address.
The offset address varies from 0000H to FFFFH which is equal to 64Kb.
0000 0000 0000 0000 = 0000H
0000 0000 0000 0001 = 0001H
-
Between the first address and

the last address there are
65536 locations = approx. 64K
locations within a segment
1111 1111 1111 1111 = FFFFH

Imp: Since these are logical segments hence it is not necessary that base address should start at
fixed locations like 1000H, 2000H.F000H etc., it may start at any random location where memory
is empty.
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Consider,
Base address : 1238H
Offset address : 01FFH
Therefore Physical address = 12380H
+
01FFH
-------------1257FH
--------------One important point to notice is that the offset address varies as 0000H to FFFFH in every
segment but the base address of every segment is different. Hence physical address
varies due to base address.
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Segment Register
Starting address of segment
Ending address of segment
2000H
20000H
2FFFFH
2001H
20010H
3000FH
2100H
21000H
30FFFH
AB00H
AB000H
BAFFFH
1234H
12340H
2233FH
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Chapter No. 3
8086 Instruction
Set
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About assembly language

programming
Assembly language is a low level language which uses mnemonics (opcodes) and
operands (data) to write an instruction.
It does not consist of powerful statements like C, C++ which are said to be high level
language.
To convert C codes to machine codes (also called as machine level language which only
the machine understands) we require a compiler.
To convert an assembly language program to machine language which the machine i.e.
p understands an assembler is required.
An assembler is a software which converts assembly language program to machine
language which the microprocessor understands.
Several assemblers are available for developing assembly language programs.
Turbo assembler and macro assembler are widely used tools.
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Program development tools

Editor:
It is used to type the assembly language statements for the program and save in a file.
The file containing the text of assembly language statements is called as source file and
has the extension .asm
Assembler:
Assembler is a software which reads the text from the source file, translates into
respective binary codes and saves into two files, one with the extension .obj called as
object file and one with the extension .lst called as list file.
The object file contains binary codes and addresses of the instructions.
The list file contains assembly language statements, binary codes, and offset address for
each instruction.
Assembler
indicates syntax errors if anyBYin
the source file.
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Program development tools

Linker:
Large assembly language programs are usually divided into many small modules.
The code for each module are separately developed, tested and finally linked into a single
large executable program.
The linker is used to join many object files into a single large object file.
Usually linker produces files with the extension .exe which can be directly loaded in the
memory and executed.
Debugger:
It enables the program to be loaded into the system memory, execute it and then debug
it. It also enables to insert breakpoints at any desired locations, change the content of
register, memory location and rerun the program.
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How does microprocessor differentiate

between data and instruction and
code?
-
As soon as p is turned on it begins execution of code in the memory sequentially
An instruction consists of two parts viz. opcode and operand
Opcode tells the microprocessor what operation is to be performed.
Operand is the one on which the operation is to performed.
How the operation is to be performed we come to know from addressing mode.
Both opcode and data (operand) present in the instruction are in binary numbers, so
how to differentiate?
The p always interprets the first byte it fetches as opcode and second as operand
Eg. We tell the processor that our program begins at 2000h. The first code it fetches is
3Eh, when it decodes it knows that it is a 2 byte instruction, hence the second code i.e.
32h is a data byte. If we enter 06h instead of 32h then it will load 06 in the accumulator
instead
of 32
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Concept about instruction

What
is word length of a microprocessor?
The word length is defined as the no. of bits, the microprocessor recognizes and processes at a time.
As we know that our microprocessor is 16 bit microprocessor hence it recognizes 16 bits at a time.
What actually it means is that the number of binary combinations possible to pass on the data bus.
Since data bus is of 16 bits hence 16 binary bits can pass on it from :
0000 0000 0000 0000
Between these two limits the number of binary combinations are = 65536
1111 1111 1111 1111

Microprocessor understands only binary codes, now each 16 bit binary pattern is assigned a special
task, or we can say that the design engineer assigns a special meaning to each 16 bit binary
combination using logic ckts, this is called an instruction.
For Eg. 1111 1110 1100 1001 is an instruction which tells the microprocessor to decrement the content
of CL register by one
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Concept about instruction

What is an instruction ?
An instruction is a binary pattern designed inside a microprocessor to perform a specific
function.
The entire group of instructions that a microprocessor supports is called Instruction Set.
As explained above the different binary combinations are different instructions and a set
of these binary combinations are called as the instruction set of that microprocessor.
Instructions tell us what operation is to be performed.
Now how to perform the operation, we come to know from addressing modes.
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Addressing modes
The different addressing modes are as follows:
1. Implicit addressing mode
2. Register addressing mode
3. Immediate addressing mode
4. Direct addressing mode
5. Register Indirect addressing mode
6. Register relative addressing mode
7. Based indexed addressing mode
8. Relative based indexed addressing mode
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Immediate addressing mode

In this addressing mode the data (operand) is present in the instruction itself.
Eg.
Mov bl,02h
;this instruction when executed will move immediate data 02h into the bl register
Assume bl = 9fh before execution

After execution bl = 02h
Mov ax,0000h
;this instruction when executed will move immediate data 0000h to the ax register
Assume ax = 121ah before execution

After execution ax = 0000h
Note:
Mov bl,1000h
;is not valid as 1000h is 16 bit and bl is a register which is 8 bits
Always in an instruction the source and the destination size should be same, if source is 8 bits in size,
then destination should also be 8 bits.
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Direct addressing mode

In this addressing mode, the data is present in the memory i.e. data segment, and the
effective address (offset address) where the data is present is given in the instruction.
Eg.
Mov al, [1234h]
1234h
;this instruction moves the data present at the effective address
Assume data at the address ds : 1234 = 78h; al = 90h

After execution al = 78h
Note:
If we write : mov ax,1234h, this instruction will move 1234h into the ax register, hence to
denote address in the instruction we write the address in square bracket [].
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Register addressing mode

In this addressing mode the data is present in any of the general purpose registers.
The name of the register is mentioned in the instruction itself.
Eg:
Mov al,bl
register
;when this instruction is executed the contents of bl register is copied to al
If bl = 55h;
al = 00h
After instruction is executed

Bl = 55h; al = 55h
Note:
Mov ax,bl
not same
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;this instruction is not valid as the size in bits of source and destination is
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Register indirect addressing mode

In this addressing mode the data is present in the memory location and the address of the
memory location is not given directly in the instruction but instead is stored in some
register pair or index register.
For this purpose three registers are used viz. BX, SI, and DI
Eg.
Mov al,[si]
;it moves the contents at the memory location whose offset address is
given by si register
Assume al = 00h, si = 145Ah, now square brackets in the instruction indicates address
Let data at the location DS : 145AH = 34h
After execution al = 34h
Similarly we can write
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Mov al,[bx]
or mov al,[di]
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170
;here bxBYand
di hold offset address where data is present
Register relative addressing mode

In this addressing mode, data is present in the memory and to access this data we require
its address.
The address is not given directly in the instruction but instead is obtained by adding the
contents of the base register and displacement or index register and displacement.
Eg.
Mov al,08[si]
08h = 100Ah
; si = 1002h, displacement = 08, therefore effective address = 1002h +
The above instruction will move the content at the memory location 100Ah which is
formed by adding si and displacement in al register.
Assume data at location DS : 100Ah = 56h
Therefore al = 56h after execution
Note: The
displacement may be 8 bit or BY16
bit
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Based indexed addressing mode

In this addressing mode the data is present in the memory whose address is not given
directly in the instruction but instead is calculated by adding the contents in the base
register and index register.
BX and BP are used as base registers and SI and DI are used as index registers.
Therefore effective address may be calculated using {BX or BP} + {SI or DI}
Eg.
Mov al,[bx][si]
offset address
;let bx = 1087h, si = 2004h, si+bx = 308Bh = effective address or
This instruction will mov the data present at the memory location 308Bh into al register.
Lets assume al = 09h before execution and address 308Bh contains 8Ch data.
After execution al = 8Ch
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Relative based indexed addressing

mode
In this addressing mode the data is present in the memory and to access this data, we
require its address which is not present directly in the instruction.
The address is calculated by adding the contents in the base register and index
register and displacement
Therefore {BX or BP} + {SI or DI} + {displacement}
Note: The displacement may be 8 bit or 16 bit
Eg.
Mov al,1234[si][bp] ;let si = 1000h, bp = 1200h, displacement = 1234h, EA =
1000h+1200h+1234h = 3434h
When the above instruction is executed the data at the location 3434h will be copied in
the al register.
Assume
al = 23h before execution, dataBYat
the location 3434h = 6Fh
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Implicit addressing mode

In the addressing mode the data is neither present in the instruction, nor any register, nor
at any memory location.
There are some instructions which work on some registers directly such addressing
scheme is called as implicit addressing mode.
Eg.
STI
;set interrupt flag
CLD
;clear direction flag
STD
;set direction flag
Note: In the above instructions there is no concern with data.
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Assembler directives
Assembly language contains two types of statements
- Instructions
- Directives
Instructions are translated into machine code by the assembler which the processor
understands by decoding them. In other words instructions, instruct the processor to do a
particular task.
Directives are instructions to the assembler which help the assembler in the assembly
process and these directives are not translated into machine code.
Or
Statements that direct the assembler to do some special task
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DB, DW, DD, DQ, DT directives Cont..

D B : define byte
The DB directive is used to reserve a byte or bytes of memory location in the available
memory.
Eg: array DB 20h {assembler reserves 1 byte of memory for the variable named sum and
initializes its value to 20}
array DB 0 {assembler reserves 1 byte of memory for the variable named sum and
initializes it to 0}
D W : define word
The DW directive is used to reserve a word or words of memory location in the available
memory.
Eg: array DW 1234h, 2345h, 3456h, 5678h {this makes the assembler reserve four words
in memory(8 bytes), and initializes the words the specified values in the statements}
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DB, DW, DD, DQ, DT directives cont..

D Q : define Quad word
This directive is used to direct the assembler to reserve four words(8 bytes) of memory for
the specified variable.
D D : define double word
This directive is used to direct the assembler to reserve two words(4 bytes) of memory for
the specified variable.
D T : define ten bytes
This directive directs the assembler to define the specified variable requiring 10 bytes for
its storage and initialize 10 bytes with the specified values.
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DB, DW, DD, DQ, DT directives cont..

Let's understand with the help of an example
Data segment
A db 20h,45,00101101B
B dw 2786h,34h,76,10011010B
C dd 12345678h,32h,6ABFh
D dq 12345678ABCD9876h
E dt 123456789ABCDE874590h
Data ends
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Assume directive
A S S U M E : assume logical segment name
The ASSUME directive is used to inform the assembler the names of the logical segments to
be assumed for different segments used in the program.
Eg: the statement ASSUME
CS : CODE directs the assembler that the machine
code(executable program) are available in a segment named CODE and hence CS register
is to be loaded with the segment address for the label CODE, while loading.
Eg: the statement ASSUME DS : DATA indicates to the assembler that the data items related
to the program are available in the logical segment named DATA, and DS register is to be
initialized by the segment address for data segment while loading
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Segment, ends and end directive

S E G M E N T :
The segment directive is used to indicate the start of a logical segment.
Eg: CODE SEGMENT statement indicates to the assembler the start of a logical segment called CODE
Eg: DATA SEGMENT statement indicates to the assembler the start of a logical segment called DATA
E N D S : end of segment
This directive marks the end of a logical segment. The logical segments are assigned with the names using ASSUME directive. The names
appear with the ENDS directive as prefix to mark the end of those particular segments.
Eg: DATA SEGMENT

.
.
DATA ENDS
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Segment, ends and end directive

cont..
E N D : end of program
The END directive marks the end of an assembly language program. When the assembler
comes across the END directive, it ignores the source lines available later on.
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Org (originate) directive

This assembler directive is used to assign starting memory location of program.
If org is not given then program code will be stored from the effective address 0000h by
default.
Eg: Org 1000h will start storing the program from the address 1000h.
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EQU (equate) directive

This directive tells the assembler to assign a value to the corresponding label.
This directive is used in general when we use some value ,multiple times in a program. So
when we want to change the value. We need to go everywhere in the program where we
entered the value.
Instead of that what we will do is that we will use equ directive and assign that value to a
label through this directive as follows:
Count equ 100h
Now the above directive will assign value 100h to count label.
Now we use this count label many times in the main program. If we want to change its
value, we will just change the value above once and not go to every instruction like
others.
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Proc and endp directive

The subprogram called as subroutine is also called as procedure.
The proc and endp directive are used to indicate the start and of the subprogram or
procedure.
Eg.
Add proc far/near
The above statement identifies the start of a procedure named add and tells the
assembler that the procedure is far (different code segment)
Endp
The above directive indicates the end of procedure.
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Even directive
This assembler directive informs the assembler to increment the memory location counter to the next even address
if it is not already at the even address.
As we know that mp 8086 is a 16 bit processor, therefore it can access a word in one machine cycle.
But the condition is that the word is located at an even address.
Eg:1005h is a word located at 2000h and 2001h
Which means that at:
2000h 10h
2001h 05h
Hence in such case we dont require an even directive.
But if the word is located at 2001h and 2002h
Then it means that:
2001h 10h
2002h 05h
Now to access this word it will take 2 machine cycles, hence to reduce the access time we use even directive
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Chapter No.3
Instruction set of
8086
Data transfer instructions

This type of instructions are used to transfer 8/16 bit data from source to destination
without any changes in the source operand and only changing the source operand.
Always in such cases size of source and destination should be same.
X
Source
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8/16 bits
X
8/16 bits
Destinati
on
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Arithmetic instructions
Arithmetic instructions are used to perform different arithmetic operations in ALU.
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XCHG D,S (Exchange the content of

destination and source)
This instruction exchanges the content of source and destination. The size of the source
and destination must be equal.
The possible combinations of source and destinations are as follows:
Destination
Source
Register
Register
Memory
Register
It is to be noted that immediate address is also not allowed

Eg: XCHG cl,[0004h]
Where 0004h is the offset address, but it is not allowed.
For examples refer class notes.
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DAA (decimal adjust AL after addition)

This instruction is used to adjust the result and get the final result in packed bcd form.
Operation performed:
To add two 8 bit numbers and obtain the result in AL register.
Then execute DAA instruction
This instruction will check lower nibble of AL register (if > 9 or AC = 1, then it will add 06h to AL
register)
Also it will check higher nibble of AL register (if > 9 or CF = 1, then it will add 60h to AL register)
If both the nibbles are greater than 9 then AL = AL + 66h
Eg: ADD AL, BL
DAA
Refer testing.asm
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DAS (Decimal adjust AL after

subtraction)
This instruction is used to adjust the result and get the final result in packed bcd form.
Operation performed:
To subtract two 8 bit numbers and obtain the result in AL register.
Then execute DAS instruction
This instruction will check lower nibble of AL register (if > 9 or AC = 1, then it will subtract 06h from AL
register)
Also it will check higher nibble of AL register (if > 9 or CF = 1, then it will subtract 60h from AL register)
If both the nibbles are greater than 9 then AL = AL - 66h
Eg: SUB AL, BL
DAS
Refer testing.asm
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AAA (ASCII adjust after addition)

Need for ASCII adjust instructions: numerical data coming into a computer from a terminal is usually in ASCII
code.
In this code numbers 0 to 9 are represented by the ASCII codes 30H to 39H.
The 8086 allows you to add two ASCII code for two decimal digits without masking off 3 in the upper nibble
of each.
After the addition, the AAA instruction is used to make sure that the result is in correct unpacked BCD form.
Operation, assume AL = 0011 0101 = ASCII 5,
BL = 0011 1001 = ASCII 9
Add al, bl = 35h + 39h = 6eh which is incorrect bcd form

AAA when executed AL = AL AND 0fh = 6eh AND 0fh = 0eh
Since lower nibble of AL > 9,
AL = AL + 06 = 14h
AH = AH + 1 = 00h + 01h = 01h (note that AH should be zero to get correct result)
AL = AL AND 0FH = 14h AND 0fh = 04h
Therefore AH = 01h AL = 04h i.e. correct unpacked bcd result
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AAS (ASCII adjust after subtraction)

Operation:
Sub al, bl ; let bl = 0011 1001 39h = ascii 9 ; let al = 0011 0101 35h = ascii 5
aas
If lower nibble of AL > 9 or AF = 1, then AL = AL 06
AH = AH 1
AF = CF =1
AL = AL AND 0F
This instruction corrects the result in AL register after subtracting two unpacked ASCII
operands.
The result is unpacked bcd format.
Refer testint.asm
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AAM (ASCII adjust for multiplication)

This instruction can be used to convert the result of the multiplication of two valid
unpacked BCD numbers
This instruction must be used after multiplication instruction. The multiplication of two
unpacked BCD numbers is always less than 100, hence the result will be in AL and that
number is finally then converted into unpacked BCD form.
Eg:
If AL = 06 (ASCII value is 30), BL=08 (ASCII value is 38)
MUL BL
AAM
[ AX = 30H {48 decimal}

[
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AH = 04
AL = 08
]
]
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AAD (ASCII adjust before division)

Syntax: AAD
This instruction is used before division instruction.
Eg:
If AX = 0205 and BL = 07
AAD ; after execution AX = 0019 (25 decimal)
DIV BL ; content of AX is divided by BL, after execution AL = 03 (quotient), AH = 04
(Remainder)
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PUSH source, POP destination

PUSH:
This instruction pushes the content of the specified register or memory location on to the stack memory.
The PUSH instruction decrements the stack pointer by 2 and copies a word (16 bit only) into the stack segment
which is pointed by the stack pointer.
Eg. PUSH BX
The above instruction decrements the SP by 2 and copies the contents of the BX register onto the stack memory
POP:
This instruction removes the contents from the stack memory i.e. from the stack segment and loads into the
specified register or memory location
Eg. POP CX
The above instruction when executed, increments the stack pointer by 2 and removes a word from the stack
segment and loads in the CX register
Refer chapter 2 for stack concept
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PUSHF and POPF

PUSHF:
The above instruction copies the flag register contents i.e. 16 bits into the stack segment
pointed by the stack pointer.
So whenever the above instruction is executed the stack pointer decrements by 2 and the
flag register contents are stored on to the stack.
POPF:
The above instruction copies the contents (16 bits) from the stack segment pointed buy
the stack pointer into the flag register.
So whenever the above instruction is executed the stack pointer is incremented by 2 and
contents on the stack memory are moved to the flag register.
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Inc d (Increments the contents of

destination)
This instruction increments the contents of destination by one and stores the result in the
same destination.
The destination may be a register or any memory location but not any immediate data.
Eg:
Inc ch
Inc si ;where si consist of offset address
Refer testint.asm
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Dec d (decrements the contents of the

destination)
This instruction decrements the contents of the destination by one and stores the result in
the destination again.
The destination may be a register or memory, but not an immediate data.
Eg.
Dec ch
Dec si
Refer testint.asm
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XLAT
The XLAT instruction is used to translate a byte from one code to another code
The byte to be translated is put in the AL register.
There is a lookup table where a number of bytes are present
Eg. Data segment
Table db 00h,01h,04h,09h,16h,25h
a db 04
Data ends
Code segment
Mov al, a
Lea bx, table
Xlat
Code ends
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TEST D,S (AND destination and source

data)
This instruction is used to AND the destination content and source content and the result
is copied in the ALU, so the old value of destination is not lost.
S
D
ALU
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Flag controlled instructions

STC Set carry flag
STD Set direction flag
When direction flag sets, it sets the SI and DI flag in auto decrementing mode
STI Set interrupt flag
When interrupt flag is set, the interrupts appearing on the INTR pin are enabled
CLC Clear carry flag
CLD Clear direction flag
When direction flag clears, it sets the SI and DI flag in auto incrementing mode
CLI Clear interrupt flag
When interrupt flag is cleared, the interrupts appearing on the INTR pin are disabled
CMC Complement the carry flag
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MOV D,S (Move source data into

destination)
In this instruction, content of the source is transferred or copied into the destination. The
source value does not changes.
The possible combination of source and destination are:
Destination
Source
Register
Register
Memory
Register
Register
Memory
Register/memory
Data
Register/memory
Segment register
Segment register
except CS
Register/memory
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MOV D,S (Move source data into

destination)
Register can be any 8/16 bit register.
But important is to notice that source and destination should be of same size.
Memory can be indicated by any method as discussed in the addressing modes.
For examples refer class notes
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LAHF (Load AH register with 8 LSBs of

flag register)
This instruction copies the content of 8 LSBs of flag register into AH register, so the old
value of flag register is not lost but the old content of AH register is lost.
8 LSBs of flag
register
AH
X may be 0 or 1
As reserved by Intel
Refer testint.asm
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SAHF (Store contents of AH register

into 8 LSBs of flag register)
This instruction copies the content of AH register into the 8 LSBs of flag register, the content of AH
register does not change but the content in the flag register changes.
8 LSBs of flag
register
AH
X may be 0 or 1
As reserved by Intel
Refer testint.asm
Note: The value which is reserved by Intel cannot be changed or manipulated
Eg: if at bit no.6, Intel has reserved a 0, if we try to set that bit, it cannot be set.
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LDS R,Memory (Load DS and given

register {16 bit register} with memory
contents )
This instruction copies the contents of four memory locations in the given register and DS register.
The register R should be of 16 bits. Refer testint.asm
Note: immediate addressing is also not allowed over here
R
DS
Memory
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LES R,Memory (Load ES and given

register {16 bit register} with memory
contents )
This instruction copies the contents of four memory locations in the given register and ES register.
The register R should be of 16 bits. Refer testint.asm
Note: immediate addressing is also not allowed over here
R
ES
Memory
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LEA R,EA(OA) (Load effective address

of memory into given register R)
This instruction copies the effective address of memory into the given register R.
The register R should be of 16 bits, as EA or OA is always of 16 bits.
EA of
memory
16 bit register
Refer testing.asm and class notes.
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ADD D,S (Add destination and source

data)
This instruction adds the source and destination and the result is stored in the destination itself.
The size of the source and destination is the same. The possible combinations of source and destination are
given below.
Destination
Source
Register
Register
Register
Memory
Memory
Register
Register/mem
ory
Data
Eg: add ax, bx

Add al, bl
Add dx, ds: [1234h]

Refer testing.asm
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ADC D, S (Add destination and source

data with carry)
This instruction adds the content of source and destination with carry and result is stored
in the same destination.
The size of the source and destination should be same.
The possible combinations are same as add instruction.
Eg: adc ax, bx
adc al, bl
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SUB D, S (subtract source from

destination)
The subtract instruction subtracts the source from the destination and the result is stored
in the destination.
The source operand and destination operand should be same.
The possibility of source and destination are:
Eg:
sub ax, bx
sub al, bl
Refer testing.asm
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Sbb d, s (subtract the content of

source with borrow from the content of
destination)
This instruction subtracts the contents of source with borrow from the content of
destination and the result is stored in the destination itself.
The possible combinations are same as sub instruction
Eg: Sbb ax, bx
Sbb al, bl
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Neg d (negate the contents of

destination)
This instruction finds the 2s complement of the contents of the destination and stores the
result in the same destination.
The destination may be a register or memory but not an immediate data
Eg.
Neg ah
Neg cx
Neg si
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; si register contains the memory address
BY UBAID SAUDAGAR
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Cbw (convert sign byte into sign word)

This instruction converts the sign byte present in register AL into sign word and stores the
result in register AX.
Eg.
Content of AL = 94h
So after cbw instruction is executed, the result in AX = FF94H
Note: FF is indicating the number is negative
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Cwd (convert sign word into sign

double word)
This instruction converts the sign word present in the ax register into sign double word
and stores the result in register DX AX
Eg.
Let AX = 1004H
Therefore after execution of cwd instruction
The result in the DX AX register after execution = 0000H - 1004 H
Note that 0000h here indicates the number is positive
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Mul s (8/16 bits) (unsigned

multiplication of source data and
accumulator)
This instruction is used multiply two 8/16 bit numbers and store the result in AX if result is
16 bit or DX-AX in case result is 32 bits
The source may be a memory or register, but not an immediate data.
Eg.
Mul bl
This instruction will multiply content in al (by default) and bl and store the result in ax
register.
Mul bx
This instruction will multiply content in ax (by default) and bx and store the result in dx-ax
register.
Refer testint.asm
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IMUL S (8/16 bits) (integer

multiplication of source data with
accumulator)
This instruction is used for signed multiplication which multiplies source operand with the
contents of accumulator and the result is stored in AX if result is 16 bits.
It is stored in DX-AX register if result is 32 bits.
Refer testint.asm
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DIV S (Division)
This instruction is used for division operation.
To understand this instruction lets take some examples.
Eg1.
DIV BL
The above instruction will divide AX/BL by default (where AX is dividend and BL is divisor)
In other words, whenever the source operand is a byte, the dividend is a word i.e. AX register
After division we get a quotient and a remainder, quotient is stored in AL register and remainder is
stored in AH register by default
Eg2.
DIV BX
The above instruction will divide DX-AX/BX by default (where DX-AX is dividend and BX is divisor)
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Call operand (unconditional call)

When the microprocessor executes the CALL instruction, then the microprocessor will
branch from the main program to the subprogram (procedure (subroutine)).
If the main program and the sub program are present in the same code memory segment,
then it is called as intra segment branching in which only the IP is changed i.e. the offset
address changes but base address remains same.
But if the main program and the sub program are present in different code memory
segments, then it is called as inter segment branching in which the contents of CS and IP
are changed i.e. both base and offset address are changed.
There are two types of call i.e. Near CALL and Far CALL.
Near CALL is associated with intra segment branching and Far CALL is associated with
Inter segment branching.
When the CALL instruction is executed, the control gets transferred to the sub program.
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Call operand (unconditional call) cont..

When the control gets transferred to the sub program the contents of the Instruction Pointer (IP) are
changed only during Near CALL
When the control gets transferred to the sub program the contents of the Code Segment register (CS) and
Instruction Pointer (IP) are changed only during Far CALL
When the control gets transferred to the sub program, the sub program gets executed and at the end of
the program there exist a RET instruction which returns the control to the main program
Near CALL
Main program and Sub program = same code segment
When control transfers to sub program, next instructions address (offset present in IP) are saved on the
stack and CS contents remain unchanged
The control gets transferred to subprogram by loading starting address of sub program in IP register
At the end of subprogram RET instruction gets executed due to which the address of the next instruction in
the main program is loaded from the stack into the IP register and execution of main program continues.
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Far CALL
Main program and Sub program = different code segment
When control transfers to sub program, next instructions address (offset present in IP and
base address present in CS) are saved on the stack.
The control gets transferred to subprogram by loading base and offset of sub program in
CS and IP register
At the end of subprogram RET instruction gets executed due to which the base and the
offset address of the next instruction in the main program is loaded from the stack into
the CS and IP register and execution of main program continues.
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Main program
Sub program (Procedure)
Next
instructio
n
HLT
RET
CALL
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String instructions
REP
This is an instruction prefix, which can be used in string instructions.
It can be used with string instructions only.
It causes the instruction to be repeated CX no. of times.
After each execution the SI and DI registers are incremented or decremented by 1.
It is important that before we use the REP instruction prefix the following steps must be
carried out:
1. CX must be initialized to count value.
2. If auto incrementing is required, DF must be cleared using CLD instruction else set
using STD instruction.
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String instructions
MOVSB/MOVSW{move string}
It is used to transfer a word/byte from data segment to extra segment
The offset of the source in the data segment is in SI
The offset of the destination in extra segment is in DI
Eg: MOVSB {ES:[DI]
DS:[SI]..byte transfer}
Eg: MOVSW {ES:[DI], ES:[DI+1]
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DS:[SI],DS:[SI+1]}
BY UBAID SAUDAGAR
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String instructions
2.LODSB/LODSW {Load string}
It is used to load AL(or AX) register with a byte(or word) from data segment.
The offset of the source in data segment is in SI
Eg: LODSB { AL
DS:[SI].byte transfer}
Eg: LODSW {AL
DS:[SI]; AH
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DS:[SI+1]}
BY UBAID SAUDAGAR
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String instructions
3.STOSB/STOSW {Store string}
It is used to store AL(or AX) in the extra segment.
The offset of the destination in extra segment is in DI
Eg: STOSB {ES:[DI]
Eg: STOSW {ES:[DI]
1/15/16
AL .byte transfer}
AL; ES:[DI+1]
AH}
BY UBAID SAUDAGAR
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String instructions
4.CPMSB/CPMSW {Compare string}
It is used to compare a byte(or word) in the data segment with a byte or a word in the
extra segment
The offset of the byte(or word) in extra segment is in DI, the offset of the byte(or word) in
data segment is in SI
Comparison is done by subtracting the byte(or word) in extra segment from the byte(or
word) in data segment
Flags are affected but result is not stored anywhere
Eg: CMPSB {compare DS[SI]with ES:[DI].byte operation}
Eg: CMPSW {compare DS:[SI],DS:[SI+1] and ES:[DI],ES:[DI+1]}
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229

Microprocessor and Programming

Uploaded by

Microprocessor and Programming

Uploaded by

Chapter No.

Every location consist

To select the chip,

0000 1111 (0FH)

What is a Microprocessor (p) ?

What is a Microprocessor (p) ? Cont.

Microprocessor Based System

Features of 8085 microprocessor

Register organization cont..

Register organization cont..

Basic concepts about Opcode and

Basic concepts about Opcode and

Working overview of the

Let's understand the working by considering a memory attached to the microprocessor.

Working overview of the

Working overview of the

Working overview of the

Working overview of the

About Address And Data Bus

How address and data are separated ?

Binary number formats

Word : 16 bits form a word

Quad word : 64 bits form a quad word

Pin diagram of 8085

Limitation Of 8085 Microprocessor

What do you mean by 16 bit

Salient features of 8086 p

Salient features of 8086 p

Two address lines

Size of the data bus is 16

No. of combinations possible

rnal hardware design of the p is called the Architecture of that p.

BIU where to fetch instructions and data from

Pointers and index

BIU (Bus Interface Unit)

Instruction Decoder and Control Unit

General purpose registers

General purpose registers

Operand register or Temporary

Pointers and Index Registers

Instruction pointer (IP) register

Stack Pointer (SP) register

Lets understand Stack with help of a

mov ax, data

Base pointer (BP) register

Base pointer (BP) register

Source index (SI) and Destination

Flag register of 8086

Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

A 16 bit register used out of which 9 are used by

Flag Register of 8086 cont..

Flag Register of 8086 cont..

Carry flag (Bit 1)

Carry flag cont..

Auxiliary carry flag (Bit 5)

generated from the lower

AL = 45H = 0100 Lower

Auxiliary carry flag cont..

BL = 18H = 0001 1000

Parity flag (Bit 3)

Zero flag (Bit 7)

Sign flag (Bit 8)

Sign flag cont..

Overflow flag (Bit 12)

indicating that the result is

ADD = 0001 0001 0010

Interrupt flag (Bit 10)

Trap Flag (Bit 9)

Direction Flag (Bit 11 )

Direction Flag cont..

Source memory block

Destination memory block

Arithmetic Logic Unit (ALU)

6 byte instruction queue register

6 byte instruction queue register

6 byte instruction queue register