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Code Coverage Analysis Is The Process of

Coverage analysis is used to determine how well a set of test cases exercises a program or design. It works by finding parts of the code not tested, creating new test cases to increase coverage, and measuring coverage metrics to indirectly assess quality. Common coverage tools like Covered analyze Verilog code coverage by processing simulation dumps and design files to measure metrics like line, toggle, memory, logic, and state coverage.

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Lakshmisree Sajit
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40 views

Code Coverage Analysis Is The Process of

Coverage analysis is used to determine how well a set of test cases exercises a program or design. It works by finding parts of the code not tested, creating new test cases to increase coverage, and measuring coverage metrics to indirectly assess quality. Common coverage tools like Covered analyze Verilog code coverage by processing simulation dumps and design files to measure metrics like line, toggle, memory, logic, and state coverage.

Uploaded by

Lakshmisree Sajit
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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What is coverage analysis?

In coverage analysis, analysis of coverage


matrics is done,and assure quality of your set of
tests
Mainly codecoverage analysis is done
Code coverage analysis is the process of:
*Finding areas of a program not exercised by a
set of test
cases,
*Creating additional test cases to increase
coverage, *Determining a quantitative measure
of code coverage, which is an indirect measure
of quality

Cntnd
You use coverage analysis to assure quality of
your set of tests, not the quality of the actual
product.
You do not generally use a coverage analyzer
when running your set of tests through your
release candidate.
Coverage analysis requires access to test
program source code and often requires
recompiling it with a special command.

Coverage analysis tools


Code Coverage Tool(covered)
Verification Navigator
An integrated design verification
environment that enables a consistent,
easy-to-use and efficient verification
methodology with a powerful set of bestin-class tools for managing the HDL
verification process,coverage analysis etc.

What is Covered?
Covered is a Verilog code coverage analysis tool that can be useful for
determining how well a diagnostic test suite is covering the design
under test (DUT). It is command-line based with an optional Tcl/Tk GUI
report viewer, making it portable across almost all platforms.
Covered is a tool that uses your design files along with standard VCD,
LXT2 or FST dump files to analyze the code coverage of the DUT. The
code coverage information is stored in a special database file that can
be retrieved and "merged" with new coverage information to create a
summed coverage total for several tests.
After a database file has been created, the user may generate various
ASCII reports that summarize the coverage information or run
Covered's GUI to interactively analyze the coverage information.
Additionally, multiple CDD files from the same design can be ranked
for the purposes of running regressions and understanding which CDD
files do not add coverage information and can be excluded from
regressions runs, if needed.

Cntnd
Covered currently supports Verilog-1995, Verilog2001 (with the exception of config blocks
currently), and SystemVerilog constructs. Metrics
that are generated include the following:
Line coverage
Toggle coverage
Memory coverage
Combinational logic coverage
FSM state and state-transition coverage
Assertion (functional) coverage

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