1 2 3 4

D D

1 2 3
1.sch 2.sch 3.sch

C C

B B

Title
A A

Size Number Revision

A4
Date: 24-Sep-2010 Sheet of
File: D:\rathijeet\pcb design\u-controller u-processor\u-controller\pic
Drawn By: controller\LOGPIC-LS02I10\L
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 1 2 3 4

CN2 DSP1
RA0 RA1 7-SEG-CA
1 2
RA2 RA3 SEGA 7
3 4 a DPY +5Vcc
RA4 RA5 SEGB 6 a
5 6 b
RE0 RE1 +5Vcc CN4 R4 SEGA SEGC 4
7 8 SEGA-RB0 c f b
9 10 RB4 RB5 SEGD 2 g
1 2 d Q1
D RB2 RB3 330E SEGE 1 D
5X2 3 4 e e c
RB0 RB1 SW1
5 6 SEGA-RB1 R5 SEGB SEGF 9 f d R12 RD0
RC6 RC7 RB0 SEGA-RB0 SEGG 10 h
CN3 7 8 g [LEDgn]
RC4 RC5 RB1 SEGA-RB1 330E SEGH 5 10K
RD0 RD1 9 10 h
RC2 RC3

V
1 2 11 12 RB2 SEGA-RB2 SEGA-RB2 R6 SEGC
RD2 RD3 RC0 RC1 RB3 SEGA-RB3 BC547
3 4 13 14 330E
RD4 RD5 RD6 RD7 RB4 SEGA-RB4
5 6 15 16

8
RD6 RD7 +5Vcc RD4 RD5 RB5 SEGA-RB5 R8 SEGD
7 8 17 18 SEGA-RB3
9 10 RD2 RD3 RB6 SEGA-RB6
19 20 330E
RD0 RD1 RB7 SEGA-RB7
5X2 21 22
RB6 RB7 +5Vcc
23 24 SEGA-RB4 R10 SEGE
25 26 SW DIP-8
330E
CN5 13X2
RC0 RC1 SEGA-RB5 R9 SSEGF
1 2 DSP2
RC2 RC3 330E 7-SEG-CA
3 4
RC4 RC5
RC6
5 6
RC7 +5Vcc SEGA-RB6 R10 SEGG SEGA 7 a DPY +5Vcc
7 8 SEGB 6 b a
J1 J4 J3 J2 330E
9 10 SEGC 4 c f b
RA0 RD0 RC0 RB0 R11 SEGH SEGD 2 g
C 1 1 1 1 SEGA-RB7 d Q2 C
5X2 RA1 RD1 RC1 RB1 SEGE 1
2 2 2 2 e e c
RA2 RD2 RC2 RB2 330E SEGF 9 d
3 3 3 3 f R13 RD1
CN6 RA3 RD3 RC3 RB3 SEGG 10 h
4 4 4 4 g [LEDgn]
RB0 RB1 RA4 RD4 RC4 RB4 SEGH 5 10K
1 2 5 5 5 5 h
RB2 RB3 RA5 RD5 RC5 RB5

V
3 4 6 6 6 6
RB4 RB5 RE0 RD6 RC6 RB6 BC547
5 6 7 7 7 7
RB6 RB7 +5Vcc RE1 RD7 RC7 RB7
7 8 8 8 8 8

8
9 10
CON8 CON8 CON8 CON8
5X2

+5Vcc J5 +5Vcc J6 +5Vcc J7 +5Vcc J8

1 1 1 1
2 2 2 2
B 3 3 3 3 B
RP1 CON3 RP2 CON3 RP3 CON3 RP4 CON3
RD0 RA0 RB0 RC0 +5Vcc CN7
RD1 RA1 RB1 RC1 1
RD2 RA2 RB2 RC2 RE0
2
RD3 RA3 RB3 RC3 RE1
3
RD4 RA4 RB4 RC4 MH1 MH2 MH3 RE2
4
RD5 RA5 RB5 RC5 5
RD6 RE0 RB6 RC6
RD7 RE1 RB7 RC7 MTH MTH MTH CON5
SIP8-1 SIP8-1 SIP8-1 SIP8-1
MH4 MH5 MH6

MTH MTH MTH

Title
A A

Size Number Revision

A4
Date: 24-Sep-2010 Sheet of
File: D:\rathijeet\pcb design\u-controller u-processor\u-controller\pic
Drawn By: controller\LOGPIC-LS02I10\L
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 1 2 3 4

+5Vcc CS1 16 LCD LCD1

RB5
1
RB3
2
D1 R14 CON2 LCD 16X2 MODULE
1N4148 10K +5Vcc
D ZX1 PR1 D
MCLR RB7_ICSD
1 40
RA0 RB6_ICSD RA0

16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
2 39
2

C7 RA1 RB5
3 38
RA2 RB4
RESET 4 37 +5Vcc
10uF RA3 RB3 POT1
SW2 5 36 +5Vcc
RA4 RB2
6 35 VR1
RA5 RB1
1

7 34 +5Vcc
RE0 RB0 10K
8 33 +5Vcc
+5Vcc RE1
9 32 R?
RE2 RC5 +5Vcc
10 31 RE0
RD7 4K7 PR2 1
11 30
RD6 2 CN9
12 29 R? RD0 RD1
RD5 RC4 RA1 3
13 28
RD4
Y2 14 27 4K7 CON3
RC0 RC7
15 26 R? RE1
RC1 RC6 RC3 POT1 1

2
1
16 25 CN10
RC2 RC5 4K7 2
4MHz 17 24 CN15 CON2 RD2
RC3 RC4 3
18 23 RD1
C RD0 RD3 C
19 22 RD7 CON3
RD1 RD2
20 21 RD6 RE2
1
40 PIN SOCKET RD5
2

2
1
+5Vcc RD4 RD0 CN11
3
CN12 CN14 CON2
MCLR RD2 RD3 CON3
1
CJ1 CJ2 2
RB7_ICSD RB6_ICSD 3
1 1 RB7_ICSD
RB7 RB6 4
2

2
1

1
2
2 RB6_ICSD
5
CON2 CON2 RB3 CN13 CON2 CN8
6
CON2
CON6

B B
+5Vcc J10
CON4
LD2
1
2
3
4

POWER ON

R30
+12V J11

1
2
330E
+V U7 CON2 +12V
7805 +5Vcc +V
SW SPDT 1 3
BD1 +V Vin Vout 1 3
Vin Vout
PJ1 D2 SW3 3 2 1
Gnd

AC2 + C17
10uF/63V Gnd C14
3 4 C13 U6 10uF/63
1N4007 AC1 - 1000uF/25V
PJ 7812
2

KBL06
2

Title
A A

Size Number Revision

2
1

A4
J13
Date: 24-Sep-2010 Sheet of
CON2
File: D:\rathijeet\pcb design\u-controller u-processor\u-controller\pic
Drawn By: controller\LOGPIC-LS02I10\L
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 1 2 3 4

+5Vcc
+5Vcc Vdd ZX2
Vpp2 data

20
1 40

7
U5 data CLOCK
ATMEGA8 2 39
C2 C10
PD0 2 3 38
PD0 (RXD) 47uF Vdd

AVCC
R16

VCC
D 1uF 4 37 D

16
PD1 3 Vpp1

2
PD1 (TXD) 4K7 5 36
U1 4 Vdd
PD2 (INT0) 6 35
C1 4 1 5 Vdd data
C2+ C1+ PD3 (INT1) 7 34 R17 R18

V+
VCC
5 3 C4 +5Vcc 6 1 CLOCK
C2- C1- PD4 (XCK/T0) (RESET') PC6 8 33
1uF 1uF 11 28 Vdd 1K 1K
PD5 (T1) (ADC5/SCL) PC5 CLOCK 9 32
14 11 R19 12 27
T1 OUT T1 IN PD6 (AIN0) (ADC4/SDA) PC4 DATA 10 31
13 12 J9 2K2 13 26 Vdd data
R1 IN R1 OUT PD7 (AIN1) (ADC3) PC3 PC3 11 30
7 10 RC6 25 CLOCK
T2 OUT T2 IN V R21 68E (ADC2) PC2 12 29
CON1 8 9 RC7 14 24 Vpp1
R2 IN R2 OUT - PB0 (ICP1) (ADC1) PC1 13 28
1 15 23 Vdd
+ PB1 (OC1A) (ADC0) PC0
GND

16 14 27
6 G R20 68E PB2 (SS'/OC1B) wp/cs
V-

RS232 TTL 17 15 26
2 PB3 (MOSI/OC2) A2/DI CLOCK
USB 18 21 16 25
7 MAX232 ZD2 ZD1 PB4 (MISO) AREF data
19 17 24
3 3V6 3V6 PB5 (SCK) A2/DI
18 23
15

8 9 CLOCK

GND
GND
C5 PB6 (XTAL1/TOSC1) 19 22
4 10 Vdd wp/cs
1uF PB7 (XTAL2/TOSC2) J12 20 21
9 Vpp
5 12MHz 1 40 PIN SOCKET
Y3 2

22
8
C 3 +12V C
DB9FEMALE data R22
C10 C11 4
22pF 22pF clock 4K7
5
6
Q5
CON6 R25 BC558
4K7
+5Vcc
4
U2 R24
PD0 Q4
4K7 VPP1
RC3 2 7 +5Vcc CN1
CLK DNC
Vcc

+5Vcc BC548 R26

1
RC4 3 6 4K7
D ORG 2
GND

3
RC5 4 1
BT1 Q CS
+ CON3 Q3
2 1 R23
-
93C46 BC558
PC3
4K7
4

3V
B +12V B
R29
Vdd 4K7
B? +5Vcc
R27 Q6
1

sq. wave R28 BC558

U3 4K7
4K7
vcc
Vbat

7 6 RC3
sq. out SCL +5Vcc Q7
R31
6 5 RC4 PD1
8

Y? X2 SDA 4K7 VPP2

2
gnd

X1 U4 BC548
32.768Khz 3 R32
NC
Vcc

DS1307 2 4K7
A1
6 1
4

SCL SCL A0
5
SDA SDA
7
Vss

+5Vcc WP

C? 24C512 Title
A A
C? C? C? C? C?
4

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

Size Number Revision
A4
Date: 24-Sep-2010 Sheet of
File: D:\rathijeet\pcb design\u-controller u-processor\u-controller\pic
Drawn By: controller\LOGPIC-LS02I10\L
1 2 3 4