1.

PSPICE A BRIEF OVERVIEW

I. INTRODUCTION SPICE is a powerful general purpose analog circuit simulator that is used to verify circuit designs and to predict the circuit behavior. This is of particular importance for integrated circuits. It was for this reason that SPICE was originally developed at the Electronics Research Laboratory of the University of California, Berkeley (1975), as its name implies: Simulation Program for Integrated Circuits Emphasis. PSpice is a PC version of SPICE (MicroSim Corp.) and HSpice is a version that runs on workstations and larger computers. PSpice is available on the PCs in the SEAS PC computing Labs and HSPICE is available on ENIAC or PENDER. A complete manual of the Avant! Star- HSPICE (pdf document) is available as well. SPICE can do several types of circuit analyses. Here are the most important ones:

Non-linear DC analysis: calculates the DC transfer curve. Non-linear transient analysis: calculates the voltage and current as a function of time when a large signal is applied. Linear AC Analysis: calculates the output as a function of frequency. A bode plot is generated. Noise analysis Sensitivity analysis Distortion analysis Fourier analysis: calculates and plots the frequency spectrum. Monte Carlo Analysis

In addition, PSpice has analog and digital libraries of standard components (such as NAND, NOR, flip-flops, and other digital gates, op amps, etc). This makes it a useful tool for a wide range of analog and digital applications. All analyses can be done at different temperatures. The default temperature is 300K. The circuit can contain the following components:

Independent and dependent voltage and current sources Resistors Capacitors Inductors Mutual inductors Transmission lines Operational amplifiers Diodes Bipolar transistors

MOS transistors JFET MESFET Digital gates (PSpice, version 5.4 and up)

II. HOW TO SPECIFY THE CIRCUIT TOPOLOGY AND ANALYSIS?

A SPICE input file, called source file, consists of three parts. 1. Data statements: description of the components and the interconnections. 2. Control statements: tells SPICE what type of analysis to perform on the circuit. 3. Output statements: specifies what outputs are to be printed or plotted. Although these statements may appear in any order, it is recommended that they be given in the above sequence. Two other statements are required: the title statement and the end statement. The title statement is the first line and can contain any information, while the end statement is always .END. This statement must be a line be itself, followed by a carriage return! In addition, you can insert comment statements, which must begin with an asterisk (*) and are ignored by SPICE.
TITLE STATEMENT ELEMENT STATEMENTS . . COMMAND (CONTROL) STATEMENTS OUTPUT STATEMENTS .END <CR>

(i) Data Statements to Specify the Circuit Components and Topology

a. Independent DC Sources Voltage source: Vname N1 N2 Type Value Current source: Iname N1 N2 Type Value N1 is the positive terminal node N2 is the negative terminal node Type can be DC, AC or TRAN, depending on the type of analysis (see Control Statements) Value gives the value of the source The name of a voltage and current source must start with V and I, respectively. Examples:
Vin 2 0 DC 10 Is 3 4 DC 1.5

b. Resistors
Rname N1 N2 Value

c. Capacitors (C) and Inductors (L)

Cname N1 N2 Value <IC> Lname N1 N2 Value <IC>

N1 is the positive node. N2 is the negative node. IC is the initial condition (DC voltage or current). The symbol < > means that the field is optional. If not specified, it is assumed to be zero. In case of an inductor, the current flows from N1 to N2. Example:
Cap5 3 4 35E-12 5 L12 7 3 6.25E-3 1m

d. Operational Amplifiers, and other elements An operational amplifier can be simulated in different ways. The first method is to model the amplifier by resistors, capacitors and dependent sources. As an example an ideal opamp is easily simulated using a voltage dependent voltage source. The second option uses actual transistors to model the opamp. An example of the first approach (linear AC model) is given below for the uA741 opamp. We defined a subcircuit for the opamp. SPICE code for the 741 opamp (ref: Macromodeling with Spice, by J.A. Connelly/P. Choi)
* Subcircuit for 741 opamp .subckt opamp741 1 2 3 * +in (=1) -in (=2) out (=3) rin 1 2 2meg rout 6 3 75 e 4 0 1 2 100k rbw 4 5 0.5meg cbw 5 0 31.85nf eout 6 0 5 0 1 .ends opamp741

II (i). Subcircuits

A subcircuit allows you to define a collection of elements as a subcircuit (e.g. an operational amplifier) and to insert this description into the overall circuit (as you would do for any other element). Defining a subcircuit A subcircuit is defined bu a .SUBCKT control statement, followed by the circuit description as follows:
.SUBCKT SUBNAME N1 N2 N3 ... Element statements . . . .ENDS SUBNAME

in which SUBNAME is the subcircuit name and N1, N2, N3 are the external nodes of the subcircuit. The external nodes cannot be 0. The node numbers used inside the subcircuit are stricktly local, except for node 0 which is always global. For an example, see Operational Amplifier above. e. Semiconductor Devices A semiconductor device is specified by two command lines: an element and model statement. The syntax for the model statement is:
.MODEL MODName Type (parameter values)

MODName is the name of the model for the device. The Type refers to the type of device and can be any of the following: D: Diode NPN: npn bipolar transistor PNP: pnp bipolar transistor NMOS: nmos transistor PMOS: pmos transistor NJF: N-channel JFET model PJF: P-channel JFET model The parameter values specify the device characteristics as explained below. m1. Diode Element line: Dname N+ N- MODName Model statement:
.MODEL MODName D

m2. Bipolar transistors

Element: Qname C B E BJT_modelName Model statement:

.MODEL BJT_modName NPN

m3. MOSFETS Element: Mname ND NG NS &ltNB> ModName L= W= The MOS transistor name (Mname) has to start with a M; ND, NG, NS and NB are the node numbers of the Drain, Gate, Source and Bulk terminals, respectively. ModName is the name of the transistor model (see further). L and W is the length and width of the gate (in m). Model statement:
.MODEL ModName NMOS

m4. JFETS Element: Jname ND NG NS ModName ND, NG, and NS are the node numbers of the Drain, Gate, and Source terminals, respectively. ModName is the name of the transistor model Model statement:
.MODEL ModName NJF (parameter= ) .MODEL ModName PJF (parameter= )

for the N-JFET and P-JFET respectively.

II (ii) Commands or Control Statements to Specify the Type of Analysis

a. .OP Statement : This statement instructs Spice to compute the DC operating points:

voltage at the nodes current in each voltage source operating point for each element

b. .DC Statement: DC SRCname START STOP STEPin which SRC name is the name of the source you want to vary; START and STOP are the starting and ending value, respectively; and STEP is the size of the increment. Example: .DC V1 0 20 2 c. .TF Statement

The .TF statement instructs PSpice to calculate the following small signal characteristics: 1. the ratio of output variable to input variable (gain or tranfer gain) 2. the resistance with respect to the input source 3. the resistance with respect to the output terminals
.TF OUTVAR INSRC

in which OUTVAR is the name of the output variable and INSRC is the input source. Example: .TF V(3,0) VIN d. .SENS Statement This instructs PSpice to calculate the DC small-signal sensitivities of each specified output variable with respect to every circuit parameter.
.SENS VARIABLE Example: .SENS V(3,0)

e. .TRAN Statement This statement specifies the time interval over which the transient analysis takes place, and the time increments. The format is as follows:
.TRAN TSTEP TSTOP <TSTART <TMAX>> <UIC>

TSTEP is the printing increment. TSTOP is the final time TSTART is the starting time (if omitted, TSTART is assumed to be zero) TMAX is the maximum step size. UIC stands for Use Initial Condition and instructs PSpice not to do the quiescent operating point before beginning the transient analysis. If UIC is specified, PSpice will use the initial conditions specified in the element statements (see data statement) IC = value.

f. .IC Statement This statement provides an alternative way to specify initial conditions of nodes (and thus over capacitors).
.IC Vnode1 = value Vnode2 = value etc.

g. .AC Statement

This statement is used to specify the frequency (AC) analysis. The format is as follows:
.AC LIN NP FSTART FSTOP .AC DEC ND FSTART FSTOP .AC OCT NO FSTART FSTOP

in which LIN stands for a linear frequency variation, DEC and OCT for a decade and octave variation respectively. NP stands for the number of points and ND and NO for the number of frequency points per decade and octave. FSTART and FSTOP are the start and stopping frequencies in Hertz. Example: .AC DEC 10 1000 1E6

II (iii) Output Statements

These statements will instruct PSpice what output to generate. If you do not specify an output statement, PSpice will always calculate the DC operating points. The two types of outputs are the prints and plots. A print is a table of data points and a plot is a graphical representation. The format is as follows:
.PRINT TYPE OV1 OV2 OV3 ... .PLOT TYPE OV1 OV2 OV3 ...

in which TYPE specifies the type of analysis to be printed or plotted and can be:

DC TRAN AC

The output variables are OV1, OV2 and can be voltage or currents in voltage sources. Node voltages and device currents can be specified as magnitude (M), phase (P), real (R) or imaginary (I) parts by adding the suffix to V or I as follows:

M: Magnitude DB: Magnitude in dB (deciBells) P: Phase R: Real part I: Imaginary part

Examples:
.PLOT DC V(1,2) V(3) I(Vmeas) .PRINT TRAN V(3,1) I(Vmeas) .PLOT AC VM(3,0) VDB(4,2) VM(2,1) VP(3,1) IR(V2)

FULL WAVE RECTIFIER (Sample Program) AIM :

To simulate full wave rectifier circuit and to plot the input and output waveforms.

CIRCUIT DIAGRAM:

PROGRAM: *FULL WAVE RECTIFIER VAC 1 2 SIN(0 230 50HZ) R1 1 2 100MEG E1 3 0 1 2 E2 0 2 1 2 C1 4 0 220UF RL 4 0 500 D1 3 4 DIODE D2 2 4 DIODE .MODEL DIODE D .TRAN 0MS 100MS 10MS .PROBE .END

0.1 0.1

INPUT OUTPUT WAVEFORMS

RESULT:
The full wave rectifier circuit is simulated and its input & output waveforms were plotted.

2. BRIDGE RECTIFIER AIM:

To simulate Bridge rectifier circuit and to plot the input and output waveforms.

CIRCUIT DIAGRAM:

INPUT OUTPUT WAVEFORMS

RESULT:
The bridge rectifier circuit is simulated and its input & output waveforms were plotted.

3. VOLTAGE REGULATOR AIM:

To simulate and plot the regulation characteristics of 1.Series voltage regulator. 2.Shunt voltage regulator.

2-1. SERIES VOLTAGE REGULATOR CIRCUIT DIAGRAM :

Note : Model parameter for zener diode is D(IS=0.5UA RS=1 BV=5.2 IBV=0.5UA)

FREQUENCY RESPONSE:

2-2. SHUNT VOLTAGE REGULATOR CIRCUIT DIAGRAM:

FREQUENCY RESPONSE:

RESULT:
Series and Shunt voltage regulator circuits were simulated and their respective frequency response characteristics were drawn.

4. BJT AMPLIFIER
AIM: TO CALCULATE AND PLOT A) The transient response of BJT amplifier. B) Voltage gain for frequencies from 1 Hz to 100 KHz

BJT AMPLIFIER CIRCUIT: (pnp)

R 1 5 V d V c 5 4 2 7 k R 1 3 0 k C 1 u 2

0
R 5 0 V F O R F E F Q = = = V 1 1 0 C 1 u 1 Q 2

7 7

0 1 0 m 1 k

R 5

4 k

R 2

5 k

C 1

3 0 u

R 2

6 0 k

A) TRANSIENT ANALYSIS:
2.0V

1.0V

0V

-1.0V 0s 0.2ms V(C2:2) 0.4ms 0.6ms 0.8ms 1.0ms Time 1.2ms 1.4ms 1.6ms 1.8ms 2.0ms

B) AC ANALYSIS:
V 1 5 5 V C 0 1 u 1 d c Q 2 R 4 2 7 k R 1 3 0 k C 1 u 2

0
R 5 0 1 V 0 V V a c d c 1 1

7 7

R 5

4 k

R 2

5 k

C 1

3 0 u

R 2

6 0 k

Frequency Vs Vo/Vi
100V

50V

0V 1.0Hz V(C2:2)

10Hz

100Hz Frequency

1.0KHz

10KHz

100KHz

Frequency vs 20 log(V0/Vi)
40

-40 1.0Hz VDB(C2:2)

10Hz

100Hz Frequency

1.0KHz

10KHz

100KHz

RESULT: The transient response and the frequency response characteristics of the common emitter BJT amplifier is simulated and plotted.

5. TWO STAGE BJT AMPLIFIER

AIM: TO CALCULATE AND PLOT C) The transient response of two stage BJT amplifier with and without feedback. D) Voltage gain for frequencies from 1 Hz to 100 KHz

A) TRANSIENT ANALYSIS: TWO STAGE BJT AMPLIFIER WITHOUT FEEDBACK:

V 1 5 V d c 2 1 R 0 2 0 R k 1 2 4 k R 1 2 6 0 R k 6 . 8 8 k C 1 Q 6 0 3 u

0
C R 1 1 5 0 C 1 0 1 u Q V V F O A R F M E F P Q = L = V = 0 1 2 1 k 0 m v R 3 0 k R 5 1 k C 4 5 u 3 2 N 2 2 2 2 Q 2 N 2 2 2 1 Q 5 2 0 u

. 6

7 0 k

. 6

1 k

1 0 k

INPUT WAVEFORM
10mV

0V

-10mV 0s V(V2:+) Time 0.5ms 1.0ms 1.5ms 2.0ms 2.5ms 3.0ms

OUTPUT WAVEFORM
2.0V

0V

-2.0V 0s V(C3:2) Time 0.5ms 1.0ms 1.5ms 2.0ms 2.5ms 3.0ms

TWO STAGE BJT AMPLIFIER WITH FEEDBACK:

V 1 5 V d c 2 1 R 0 2 0 k R 4 1 2 k R 1 2 6 0 k R 6 . 8 8 k C 1 0 Q 6 3 u

0
C R 1 5 1 0 C 1 1 0 u Q V V F O A R F M E F P Q = = V = 0 1 2 1 k 0 m v R 3 0 k R 5 1 k C 4 u 3 2 N 2 2 2 2 Q 2 N 2 2 2 1 0 2 u

3 . 6

7 0 k

. 6

1 k

1 0 0 k

0
R 2 1 5 1 k C 1 0 6 u

INPUT WAVEFORM
10mV

0V

-10mV 0s V(V2:+) Time 0.5ms 1.0ms 1.5ms 2.0ms 2.5ms 3.0ms

OUTPUT WAVEFORM
2.0V

0V

-2.0V 0s V(C3:2) Time 0.5ms 1.0ms 1.5ms 2.0ms 2.5ms 3.0ms

B) AC ANALYSIS TWO STAGE BJT AMPLIFIER WITHOUT FEEDBACK:

V 1 5 V d c 1 R 2 2 0 0 R k 1 2 4 k R 6 1 2 0 R k 6 8 . 8 k C 1 0 Q 6 3 u

0
C R 1 1 5 0 C 1 1 2 0 u

1 0 u Q 2 N 2 2 2 2 Q 2 N 2 2 2 2

1 V 0 V

V a c d c

3 C 3 5 0 k R 3 R . 6 5 1 k 4 5 u R 7 3 0 k R 3 R . 6 k 9 1 1 0 0 k

FREQUENCY RESPONSE Frequency vs V0/Vi

200V

100V

0V 1.0Hz V(C3:2)

10Hz

100Hz Frequency

1.0KHz

10KHz

100KHz

Frequency vs 20 log(V0/Vi)
50

25

0 1.0Hz VDB(C3:2)

10Hz

100Hz Frequency

1.0KHz

10KHz

100KHz

TWO STAGE BJT AMPLIFIER WITH FEEDBACK:

V 1 5 V d c 1 R 2 2 0 0 R k 1 4 2 k R 6 1 2 0 R k 6 8 . 8 k C 3

0
C R 1 1 5 0 C 1 1 0 u Q 1 V 0 V V a c d c 3 C 4 1 5 u 2 N 2 2 2 2 Q 2 N 2 2

1 0 u

1 0 u Q 6

2 2 2

R 3 5 0 k

5 . 6 k

R 7 3 0 k

9 . 6 k

R 1 0 1 0 k

0
R 1 1 2 5 k C 1 0 6 u

FREQUENCY RESPONSE Frequency vs V0/Vi

120V 80V

40V

0V 1.0Hz V(C3:2)

10Hz

100Hz Frequency

1.0KHz

10KHz

100KHz

Frequency vs 20 log(V0/Vi)
50

25

0 1.0Hz VDB(C3:2)

10Hz

100Hz

1.0KHz Frequency

10KHz

100KHz

RESULT: CALCULATED AND PLOTTED A) The transient response of two stage BJT amplifier with and without feedback. B) Voltage gain for frequencies from 1 Hz to 100 KHz.

6. DARLINGTON AMPLIFIER AIM :

To Simulate a Darlington pair (using the sub circuit of BC 547 transistor) and to plot its frequency response characteristics.

CIRCUIT DIAGRAM :

Fig(i) Circuit diagram of Darlington pair

Fig(ii) Equivalent circuit of transistor BC 547

FREQUENCY RESPONSE

RESULT:
Darlington pair using BC 547 transistors is simulated and its frequency response characteristics is plotted.

7. ASTABLE MULTIVIBRATOR

AIM :
To Simulate an Astable multivibrator circuit using BC 107 transistor and to plot its transient response characteristics.

CIRCUIT DIAGRAM :

OUT PUT AT THE COLLECTOR OF Q1:

RESULT:
Astable multivibrator circuit using BC 107 transistors is simulated and its transient response characteristics is plotted.

8. JFET AMPLIFIER

AIM: TO SIMULATE AND PLOT E) The transient response of JFET amplifier. F) Voltage gain for frequencies from 1 Hz to 100 KHz CIRCUIT DIAGRAM:

4 3 . 5 k C 1 u 2 2 0 V

V 1 d c

R 5 0

C 1 u

1 B F 2 5 6 C

V V F

O A R

F M E

F P Q

V = =

2 =

0 1

R 0 k . 5 v 2 5 0 0 k R R 3 1 . 5 k C 3 1 0 u

5 2 0 k

A) TRANSIENT ANALYSIS: INPUT WAVEFORM

50 0mV

0V

- 500mV 0s V(R1:1) Time 0.5ms 1.0ms 1.5ms 2.0ms 2.5ms 3. 0ms

OUTPUT WAVEFORM:
5.0V

0V

-5.0V 0s V(R5:2) Time 0.5ms 1.0ms 1.5ms 2.0ms 2.5ms 3.0ms

B) AC ANALYSIS

FREQUENCY RESPONSE Frequency vs V0/Vi

10V

5V

0V 1.0Hz V(R5:2)

10Hz

100Hz Frequency

1.0KHz

10KHz

100KHz

Frequency vs 20 log(V0/Vi)
20

-20 1.0Hz VDB(R5:2)

10Hz

100Hz Frequency

1.0KHz

10KHz

100KHz

RESULT: The transient response and the frequency response characteristics of the common source FET amplifier is simulated and plotted.

9. CLIPPING AND CLAMPING CIRCUIT

AIM:
To Simulate and plot the input and output waveforms of the 1) Clipping circuit. 2) Clamping circuit 1. CLIPPING CIRCUIT.

Input wave form

Output waveform (Clipped)

2. CLAMPING CIRCUIT

Input & Output wave forms

RESULT : The clipping & clamping circuits were simulated and the respective plots were obtained using Pspice.

10. INVERTER
AIM: To plot the transient response of TTL, CMOS inverter.

TTL INVERTER:

1 4 k

2 1 k

V Q 1 Q b r e a k N Q Q b 2 r e a k N Q R 3 1 k Q b 3 r e a k N 5 V d c

V 1 V 2 T D T R T F P W P E

= = = = = R

0 V 2 5 0 n s 1 n s 1 n s = 3 8 n s = 6 0 n s

INPUT VPULSE:
5.0V

2.5V

0V 0s 20ns V(V2:+) 40ns 60ns 80ns 100ns Time 120ns 140ns 160ns 180ns 200ns

1 4 k

2 1 k

V Q 1 Q b r e a k N Q Q b 2 r e a k N Q R 3 1 k Q b 3 r e a k N 5 V d c

V 1 V 2 T D T R T F P W P E

= = = = = R

0 V 2 5 0 n s 1 n s 1 n s = 3 8 n s = 6 0 n s

OUTPUT PULSE:
5.0V

2.5V

0V 0s 20ns V(Q2:c) 40ns 60ns 80ns 100ns Time 120ns 140ns 160ns 180ns 200ns

CMOS INVERTER:

V 5 M b r e a M 2 k P V d c

V 1 V 2 T D T R T F P W P E

= = = R

= =

0 1 n s n s = 4 0 n s = 8 0 n s 1

0 5

1 M M 1 k N R 1 1 0 0 k

b r e a

INPUT VPULSE:
5.0V

2.5V

0V 0s 20ns V(M1:g) 40ns 60ns 80ns 100ns Time 120ns 140ns 160ns 180ns 200ns

V 5 M b r e a M V 1 V 2 T D T R T F P W P E = = 0 5 V 1 M M 1 k N R 1 2 k P V d c

0 1 n s = 1 n s = 4 0 n s R = 8 0 n s

= =

b r e a

1 0 0 k

OUTPUT PULSE
5.0V

2.5V

0V 0s 20ns V(M2:d) 40ns 60ns 80ns 100ns Time 120ns 140ns 160ns 180ns 200ns

RESULT: The transient response of TTL, CMOS inverter are plotted.

PSPICE LAB

LIST OF EXPERIMENTS:

1. PSPICE A BRIEF OVERVIEW 2. BRIDGE RECTIFIER 3. VOLTAGE REGULATOR 4. BJT AMPLIFIER 5. TWO STAGE BJT AMPLIFIER 6. DARLINGTON AMPLIFIER 7. ASTABLE MULTIVIBRATOR 8. JFET AMPLIFIER 9. CLIPPING AND CLAMPING CIRCUIT 10. INVERTER