ADC Program Examples for Products AT89C51CCxx, T89C51AC2, T89C5115

References
Atmel 8051 Microcontrollers Hardware Manual

8051 Microcontrollers

Application Note

Rev. 4361C80C5111/04

1. Introduction
This Application Note provides to customers C and Assembler program examples for ADC. These examples are developped for the different configuration modes of this feature. The Code example targets T89C51CC01, please replace the line # include T89C51CC01.h with the corresponding line for AT89C51CC03, T89C51CC02, AT89C51AC3, T89C51AC2, T89C5115 products.

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2. C Examples
2.1 8 bits ADC
/** * @file $RCSfile: Adc_8bits.c,v $ * * Copyright (c) 2004 Atmel. * * Please read file license.txt for copyright notice. * * @brief This file is an example to use Adc. * * This file can be parsed by Doxygen for automatic documentation * generation. * Put here the functional description of this file within the software * architecture of your program. * * @version $Revision: 1.0 $ $Name: */ $

/* @section

I N C L U D E S */

#include "t89c51cc01.h"

unsigned char value_converted=0x00; /* converted value */ unsigned char value_AN6=0x00; unsigned char value_AN7=0x00; bit end_of_convertion=0; /* converted AN6 value */ /* converted AN7 value */ /* software flag */

/** * FUNCTION_PURPOSE:this function setup Adc with channel 6 and 7 and start * 8bits convertion. * FUNCTION_INPUTS:void * FUNCTION_OUTPUTS:void */ void main(void) { /* configure channel P1.6(AN6) and P1.7(AN7) for ADC */ ADCF = 0xC0;

/* init prescaler for adc clock */ /* Fadc = Fperiph/(2*(32-PRS)), PRS -> ADCLK[4:0] */ ADCLK = 0x06; /* Fosc = 16 MHz, Fadsc = 153.8khz */

ADCON = 0x20;

/* Enable the ADC */

EA = 1; EADC = 1;

/* enable interrupts */ /* enable ADC interrupt */

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while(1) { ADCON &= ~0x07; ADCON |= 0x06; ADCON &= ~0x40; ADCON |= 0x08; while(!end_of_convertion); end_of_convertion=0; value_AN6=value_converted; /* Clear the channel field ADCON[2:0] */ /* Select channel 6 */ /* standard mode */ /* Start conversion */ /* wait end of convertion */ /* clear software flag */ /* save converted value */

ADCON &= ~0x07; ADCON |= 0x07; ADCON &= ~0x40; ADCON |= 0x08;

/* Clear the channel field ADCON[2:0] */ /* Select channel 7 */ /* standard mode */ /* Start conversion */

while(!end_of_convertion); end_of_convertion=0; value_AN7=value_converted;

/* wait end of convertion */ /* clear software flag */ /* save converted value */

} }

/** * FUNCTION_PURPOSE:Adc interrupt, save ADDH into an unsigned char * FUNCTION_INPUTS:void * FUNCTION_OUTPUTS:void */ void it_Adc(void) interrupt 8 { ADCON &= ~0x10; value_converted = ADDH; end_of_convertion=1; } /* Clear the End of conversion flag */ /* save value */ /* set flag */

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2.2 10bits ADC

/** * @file $RCSfile: Adc_10bits.c,v $ * * Copyright (c) 2004 Atmel. * * Please read file license.txt for copyright notice. * * @brief This file is an example to use Adc. * * This file can be parsed by Doxygen for automatic documentation * generation. * Put here the functional description of this file within the software * architecture of your program. * * @version $Revision: 1.0 $ $Name: */ /* @section I N C L U D E S */ $

#include "t89c51cc01.h" unsigned int value_converted=0x0000;/* converted value */ unsigned int value_AN6=0x0000; unsigned int value_AN7=0x0000; bit end_of_convertion=0; /* converted AN6 value */ /* converted AN7 value */ /* software flag */

/** * FUNCTION_PURPOSE:this function setup Adc with channel 6 and 7 and start * 10bits convertion. * FUNCTION_INPUTS:void * FUNCTION_OUTPUTS:void */ void main(void) {

/* configure channel P1.6(AN6) and P1.7(AN7) for ADC */ ADCF = 0xC0;

/* init prescaler for adc clock */ /* Fadc = Fperiph/(2*(32-PRS)), PRS -> ADCLK[4:0] */ ADCLK = 0x06; ADCON = 0x20; /* Fosc = 16 MHz, Fadsc = 153.8khz */ /* Enable the ADC */

EA = 1; EADC = 1;

/* enable interrupts */ /* enable ADC interrupt */

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while(1) { ADCON &= ~0x07; ADCON |= 0x06; ADCON &= ~0x40; ADCON |= 0x08; while(!end_of_convertion); end_of_convertion=0; value_AN6=value_converted; /* Clear the channel field ADCON[2:0] */ /* Select channel 6 */ /* standard mode */ /* Start conversion */ /* wait end of convertion */ /* clear software flag */ /* save converted value */

ADCON &= ~0x07; ADCON |= 0x07; ADCON &= ~0x40; ADCON |= 0x08;

/* Clear the channel field ADCON[2:0] */ /* Select channel 7 */ /* standard mode */ /* Start conversion */

while(!end_of_convertion); end_of_convertion=0; value_AN7=value_converted;

/* wait end of convertion */ /* clear software flag */ /* save converted value */

} }

/** * FUNCTION_PURPOSE:Adc interrupt, save ADDH and ADDL into an unsigned int * FUNCTION_INPUTS:void * FUNCTION_OUTPUTS:void */ void it_Adc(void) interrupt 8 { ADCON &= ~0x10; value_converted = ADDH<<2; value_converted |= (ADDL & 0x03); end_of_convertion=1; } /* Clear the End of conversion flag */ /* save 8 msb bits */ /* save 2 lsb bits */ /* set flag */

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2.3 SFR Register Definition

/*H************************************************************************* ** * NAME: T89C51CC01.h *--------------------------------------------------------------------------* PURPOSE: inlcude file for KEIL **************************************************************************** */ #ifndef _T89C51CC01_H_

#define _T89C51CC01_H_

#define Sfr(x, y)

sfr x = y sbit x = y^z

#define Sbit(x, y, z)

#define Sfr16(x,y)sfr16 x = y

/*----------------------------------------*/ /* Include file for 8051 SFR Definitions */

/*----------------------------------------*/ /* BYTE Register */

Sfr (P0 , 0x80); Sfr (P1 , 0x90);

Sbit (P1_7, 0x90, 7); Sbit (P1_6, 0x90, 6); Sbit (P1_5, 0x90, 5); Sbit (P1_4, 0x90, 4); Sbit (P1_3, 0x90, 3); Sbit (P1_2, 0x90, 2); Sbit (P1_1, 0x90, 1); Sbit (P1_0, 0x90, 0);

Sfr (P2 , 0xA0); Sbit (P2_7 , 0xA0, 7); Sbit (P2_6 , 0xA0, 6); Sbit (P2_5 , 0xA0, 5); Sbit (P2_4 , 0xA0, 4); Sbit (P2_3 , 0xA0, 3); Sbit (P2_2 , 0xA0, 2); Sbit (P2_1 , 0xA0, 1); Sbit (P2_0 , 0xA0, 0);

Sfr (P3 , 0xB0); Sbit (P3_7 , 0xB0, 7); Sbit (P3_6 , 0xB0, 6);

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Sbit (P3_5 , 0xB0, 5); Sbit (P3_4 , 0xB0, 4); Sbit (P3_3 , 0xB0, 3); Sbit (P3_2 , 0xB0, 2); Sbit (P3_1 , 0xB0, 1); Sbit (P3_0 , 0xB0, 0); Sbit (RD , 0xB0, 7); Sbit (WR , 0xB0, 6); Sbit (T1 , 0xB0, 5); Sbit (T0 , 0xB0, 4); Sbit (INT1, 0xB0, 3); Sbit (INT0, 0xB0, 2); Sbit (TXD , 0xB0, 1); Sbit (RXD , 0xB0, 0); Sfr (P4 , 0xC0);

Sfr (PSW , 0xD0);

Sbit (CY Sbit (AC Sbit (F0

, 0xD0, 7); , 0xD0, 6); , 0xD0, 5);

Sbit (RS1 , 0xD0, 4); Sbit (RS0 , 0xD0, 3); Sbit (OV Sbit (UD Sbit (P , 0xD0, 2); , 0xD0, 1); , 0xD0, 0);

Sfr (ACC , 0xE0); Sfr (B , 0xF0); Sfr (SP , 0x81); Sfr (DPL , 0x82); Sfr (DPH , 0x83);

Sfr (PCON , 0x87); Sfr (CKCON , 0x8F);

/*------------------ TIMERS registers ---------------------*/ Sfr (TCON , 0x88); Sbit (TF1 , 0x88, 7); Sbit (TR1 , 0x88, 6); Sbit (TF0 , 0x88, 5); Sbit (TR0 , 0x88, 4); Sbit (IE1 , 0x88, 3); Sbit (IT1 , 0x88, 2); Sbit (IE0 , 0x88, 1); Sbit (IT0 , 0x88, 0); Sfr (TMOD , 0x89);

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Sfr

(T2CON , 0xC8); , 0xC8, 7); , 0xC8, 6); , 0xC8, 5); , 0xC8, 4); , 0xC8, 2); , 0xC8, 1);

Sbit (TF2 Sbit (EXF2 Sbit (RCLK Sbit (TCLK Sbit (TR2 Sbit (C_T2

Sbit (EXEN2 , 0xC8, 3);

Sbit (CP_RL2, 0xC8, 0);

Sfr (T2MOD , 0xC9); Sfr (TL0 , 0x8A); Sfr (TL1 , 0x8B); Sfr (TL2 , 0xCC); Sfr (TH0 , 0x8C); Sfr (TH1 , 0x8D); Sfr (TH2 , 0xCD); Sfr (RCAP2L , 0xCA); Sfr (RCAP2H , 0xCB); Sfr (WDTRST , 0xA6); Sfr (WDTPRG , 0xA7);

/*------------------- UART registers ------------------------*/ Sfr (SCON , 0x98); Sbit (SM0 Sbit (FE Sbit (SM1 Sbit (SM2 Sbit (REN Sbit (TB8 Sbit (RB8 Sbit (TI Sbit (RI , 0x98, 7); , 0x98, 7); , 0x98, 6); , 0x98, 5); , 0x98, 4); , 0x98, 3); , 0x98, 2); , 0x98, 1); , 0x98, 0);

Sfr (SBUF , 0x99); Sfr (SADEN , 0xB9); Sfr (SADDR , 0xA9); /*-------------------- ADC registers ----------------------*/ Sfr (ADCLK , 0xF2); Sfr (ADCON , 0xF3); #define MSK_ADCON_PSIDLE 0x40 #define MSK_ADCON_ADEN #define MSK_ADCON_ADEOC #define MSK_ADCON_ADSST #define MSK_ADCON_SCH Sfr (ADDL , 0xF4); #define MSK_ADDL_UTILS 0x03 0x20 0x10 0x08 0x07

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Sfr (ADDH , 0xF5); Sfr (ADCF , 0xF6);

/*-------------------- FLASH EEPROM registers ------------*/ Sfr (FCON , 0xD1);

#define MSK_FCON_FBUSY 0x01 #define MSK_FCON_FMOD #define MSK_FCON_FPS #define MSK_FCON_FPL Sfr (EECON , 0xD2); 0x06 0x08 0xF0

#define MSK_EECON_EEBUSY 0x01 #define MSK_EECON_EEE #define MSK_EECON_EEPL Sfr (AUXR , 0x8E); 0x20 0x02 0xF0

#define MSK_AUXR_M0 Sfr (AUXR1 , 0xA2);

#define MSK_AUXR1_ENBOOT 0x20 /*-------------------- IT registers -----------------------*/ Sfr (IPL1 , 0xF8); Sfr (IPH1 , 0xF7); Sfr (IEN0 , 0xA8);

Sfr (IPL0 , 0xB8); Sfr (IPH0 , 0xB7); Sfr (IEN1 /* IEN0 , 0xE8); */ , 0xA8, 7); , 0xA8, 6); , 0xA8, 5); , 0xA8, 4); , 0xA8, 3); , 0xA8, 2); , 0xA8, 1); , 0xA8, 0);

Sbit (EA Sbit (EC Sbit (ET2 Sbit (ES Sbit (ET1 Sbit (EX1 Sbit (ET0 Sbit (EX0

/*

IEN1

*/

Sbit (ETIM , 0xE8, 2); Sbit (EADC , 0xE8, 1); Sbit (ECAN , 0xE8, 0); /*--------------------- PCA registers --------------------*/ Sfr (CCON , 0xD8); Sbit(CF Sbit(CR , 0xD8, 7); , 0xD8, 6);

Sbit(CCF4, 0xD8, 4); Sbit(CCF3, 0xD8, 3); Sbit(CCF2, 0xD8, 2); Sbit(CCF1, 0xD8, 1); Sbit(CCF0, 0xD8, 0);

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Sfr (CMOD , 0xD9); Sfr (CH , 0xF9); Sfr (CL , 0xE9); Sfr (CCAP0H Sfr (CCAP0L Sfr (CCAPM0 Sfr (CCAP1H Sfr (CCAP1L Sfr (CCAPM1 Sfr (CCAP2H Sfr (CCAP2L Sfr (CCAPM2 Sfr (CCAP3H Sfr (CCAP3L Sfr (CCAPM3 Sfr (CCAP4H Sfr (CCAP4L Sfr (CCAPM4 , 0xFA); , 0xEA); , 0xDA); , 0xFB); , 0xEB); , 0xDB); , 0xFC); , 0xEC); , 0xDC); , 0xFD); , 0xED); , 0xDD); , 0xFE); , 0xEE); , 0xDE);

/*------------------- CAN registers --------------------------*/ Sfr (CANGIT , 0x9B); #define MSK_CANGIT_CANIT0x80 #define MSK_CANGIT_OVRTIM #define MSK_CANGIT_OVRBUF0x10 #define MSK_CANGIT_SERG0x08 #define MSK_CANGIT_CERG0x04 #define MSK_CANGIT_FERG0x02 #define MSK_CANGIT_AERG0x01 0x20

Sfr (CANTEC , 0x9C); Sfr (CANREC , 0x9D); Sfr (CANTCON , 0xA1); Sfr (CANMSG , 0xA3); Sfr (CANTTCL , 0xA4); Sfr (CANTTCH , 0xA5); Sfr (CANGSTA , 0xAA); #define MSK_CANGSTA_OVFG0x40 #define MSK_CANGSTA_TBSY0x10 #define MSK_CANGSTA_RBSY0x08 #define MSK_CANGSTA_ENFG0x04 #define MSK_CANGSTA_BOFF0x02 #define MSK_CANGSTA_ERRP0x01 Sfr (CANGCON , 0xAB); #define MSK_CANGCON_ABRQ #define MSK_CANGCON_OVRQ #define MSK_CANGCON_TTC 0x80 0x40 0x20 0x10 0x10 0x00

#define MSK_CANGCON_SYNCTTC #define TTC_EOF #define TTC_SOF

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#define MSK_CANGCON_AUTBAUD #define MSK_CANGCON_ENA 0x02

0x08

#define MSK_CANGCON_GRES 0x01

Sfr (CANTIML , 0xAC); Sfr (CANTIMH , 0xAD); Sfr (CANSTMPL , 0xAE); Sfr (CANSTMPH , 0xAF); Sfr (CANPAGE , 0xB1); Sfr (CANSTCH , 0xB2); #define MSK_CANSTCH_DLCW #define MSK_CANSTCH_TxOk #define MSK_CANSTCH_RxOk #define MSK_CANSTCH_BERR #define MSK_CANSTCH_SERR #define MSK_CANSTCH_CERR #define MSK_CANSTCH_FERR #define MSK_CANSTCH_AERR 0x80 0x40 0x20 0x10 0x08 0x04 0x02 0x01

Sfr (CANCONCH , 0xB3); #define MSK_CANCONCH_IDE #define MSK_CANCONCH_DLC 0x10 0x0F

#define MSK_CANCONCH_CONF 0xC0 #define DLC_MAX 8 #define CH_DISABLE 0x00 #define CH_RxENA #define CH_TxENA #define CH_RxBENA 0x80 0x40 0xC0

Sfr (CANBT1 , 0xB4); #define CAN_PRESCALER_MIN #define CAN_PRESCALER_MAX Sfr (CANBT2 , 0xB5); #define MSK_CANBT2_SJW #define MSK_CANBT2_PRS #define CAN_SJW_MIN #define CAN_SJW_MAX #define CAN_PRS_MIN #define CAN_PRS_MAX 0 3 0 7 0x60 0x0E 0 63

Sfr (CANBT3 , 0xB6); #define MSK_CANBT3_PHS2 0x70 #define MSK_CANBT3_PHS1 0x0E #define CAN_PHS2_MIN 0 #define CAN_PHS2_MAX 7 #define CAN_PHS1_MIN 0 #define CAN_PHS1_MAX 7

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Sfr (CANSIT1 , 0xBA); Sfr (CANSIT2 , 0xBB); Sfr (CANIDT1 , 0xBC); Sfr (CANIDT2 , 0xBD); Sfr (CANIDT3 , 0xBE); Sfr (CANIDT4 , 0xBF); #define MSK_CANIDT4_RTRTAG 0x04

Sfr (CANGIE , 0xC1); #define MSK_CANGIE_ENRX #define MSK_CANGIE_ENTX #define MSK_CANGIE_ENERCH #define MSK_CANGIE_ENBUF #define MSK_CANGIE_ENERG 0x20 0x10 0x08 0x04 0x02

Sfr (CANIE1 , 0xC2); Sfr (CANIE2 , 0xC3); Sfr (CANIDM1 , 0xC4); Sfr (CANIDM2 , 0xC5); Sfr (CANIDM3 , 0xC6); Sfr (CANIDM4 , 0xC7); #define MSK_CANIDM4_RTRMSK 0x04 #define MSK_CANIDM4_IDEMSK 0x01

Sfr (CANEN1 , 0xCE); Sfr (CANEN2 , 0xCF);

#endif

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3. Assembler 51 Examples
3.1 8 bits Adc
$INCLUDE (t89c51cc01.INC) /* converted value */ /* converted AN6 value */ /* converted AN7 value */ /* software flag */ value_converted DATA 10H; value_AN6 DATA 11H; value_AN7 DATA 12H; end_of_convertion BIT 20H;

org 000h ljmp begin

org 43h ljmp adc_it

;/** ; * FUNCTION_PURPOSE:this function setup Adc with channel 6 and 7 and start ; * 8bits convertion. ; * FUNCTION_INPUTS:void ; * FUNCTION_OUTPUTS:void ; */ org 0100h begin:

/* configure channel P1.6(AN6) and P1.7(AN7) for ADC */ MOV ADCF,#0C0h;

/* init prescaler for adc clock */ /* Fadc = Fperiph/(2*(32-PRS)), PRS -> ADCLK[4:0] */ MOV ADCLK,#06h; MOV ADCON,#20h; /* Fosc = 16 MHz, Fadsc = 153.8khz */ /* Enable the ADC */

SETB EA; SETB EADC; loop:

/* enable interrupts */ /* enable ADC interrupt */

ANL ADCON,#~07h; ORL ADCON, #06h; ANL ADCON,#~40h; ORL ADCON, #08h; JNB end_of_convertion,$; CLR end_of_convertion;

/* Clear the channel field ADCON[2:0] */ /* Select channel 6 */ /* standard mode */ /* Start conversion */ /* wait end of convertion */ /* clear software flag */

MOV value_AN6,value_converted;/* save converted value */

ANL ADCON,#~07h;

/* Clear the channel field ADCON[2:0] */

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ORL ADCON, #07h; ANL ADCON,#~40h; ORL ADCON, #08h; JNB end_of_convertion,$; CLR end_of_convertion;

/* Select channel 7 */ /* standard mode */ /* Start conversion */ /* wait end of convertion */ /* clear software flag */

MOV value_AN7,value_converted;/* save converted value */

JMP loop ;/** ; * FUNCTION_PURPOSE:Adc interrupt, save ADDH into an unsigned char ; * FUNCTION_INPUTS:void ; * FUNCTION_OUTPUTS:void ; */ adc_it: ANL ADCON,#~10h; MOV value_converted,ADDH; SETB end_of_convertion; RETI /* Clear the End of conversion flag */ /* save value */ /* set flag */

end

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3.2 10 bits ADC

$INCLUDE (t89c51cc01.INC) /* converted msb value */ /* converted lsb value */ /* converted msb AN6 value */ /* converted lsb AN6 value */ /* converted msb AN7 value */ /* converted lsb AN7 value */ /* software flag */ msb_value_converted DATA 10H; lsb_value_converted DATA 11H; msb_value_AN6 DATA 12H; lsb_value_AN6 DATA 13H; msb_value_AN7 DATA 14H; lsb_value_AN7 DATA 15H; end_of_convertion BIT 20H; CLR end_of_convertion

org 000h ljmp begin

org 43h ljmp adc_it

;/** ; * FUNCTION_PURPOSE:this function setup Adc with channel 6 and 7 and start ; * 8bits convertion. ; * FUNCTION_INPUTS:void ; * FUNCTION_OUTPUTS:void ; */ org 0100h begin:

/* configure channel P1.6(AN6) and P1.7(AN7) for ADC */ MOV ADCF,#0C0h;

;/* init prescaler for adc clock */ ;/* Fadc = Fperiph/(2*(32-PRS)), PRS -> ADCLK[4:0] */ MOV ADCLK,#06h; MOV ADCON,#20h; /* Fosc = 16 MHz, Fadsc = 153.8khz */ /* Enable the ADC */

SETB EA; SETB EADC; loop:

/* enable interrupts */ /* enable ADC interrupt */

ANL ADCON,#~07h; ORL ADCON, #06h; ANL ADCON,#~40h; ORL ADCON, #08h; JNB end_of_convertion,$; CLR end_of_convertion;

/* Clear the channel field ADCON[2:0] */ /* Select channel 6 */ /* standard mode */ /* Start conversion */ /* wait end of convertion */ /* clear software flag */

MOV msb_value_AN6,msb_value_converted;/* save converted msb value */ MOV lsb_value_AN6,lsb_value_converted;/* save converted lsb value */

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ANL ADCON,#~07h; ORL ADCON, #07h; ANL ADCON,#~40h; ORL ADCON, #08h;

/* Clear the channel field ADCON[2:0] */ /* Select channel 7 */ /* standard mode */ /* Start conversion */

JNB end_of_convertion,$; CLR end_of_convertion;

/* wait end of convertion */ /* clear software flag */

MOV msb_value_AN7,msb_value_converted;/* save converted msb value */ MOV lsb_value_AN7,lsb_value_converted;/* save converted lsb value */

JMP loop ;/** ; * FUNCTION_PURPOSE:Adc interrupt, save ADDH and ADDL into an unsigned int ; * FUNCTION_INPUTS:void ; * FUNCTION_OUTPUTS:void ; */ adc_it: ANL ADCON,#~10h; /* Clear the End of conversion flag */

;/* copy ADDH[7:6] into msb_value_converted[1:0] */ MOV A,ADDH SWAP A RR A RR A ANL A,#~0FCh MOV msb_value_converted,A ;/* copy ADDH[5:0] into lsb_value_coverted[7:2] MOV A,ADDH RL A RL A ANL A,#~03h MOV lsb_value_converted,A ;/* copy ADDL[1:0] into lsb_value_coverted[1:0] MOV A,ADDL ANL A,#~0FCh ORL lsb_value_converted,A

SETB end_of_convertion; RETI

/* set flag */

end

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3.3 SFR Register Definition

;*INC*********************************************************************** ** ; NAME: 89C51CC01.inc ;--------------------------------------------------------------------------; PURPOSE: for Keil ;*************************************************************************** **

;---------------------------------------; Include file for 8051 SFR Definitions ;----------------------------------------

; P0 P1 P2

BYTE Register DATA DATA DATA 80H 90H 0A0H

P3 RD WR T1 T0 INT1 INT0 TXD RXD

DATA BIT BIT BIT BIT BIT BIT BIT BIT

0B0H 0B7H 0B6H 0B5H 0B4H 0B3H 0B2H 0B1H 0B0H

P4

DATA

0C0H

PSW CY AC F0 RS1 RS0 OV P

DATA BIT BIT BIT BIT BIT BIT BIT

0D0H 0D7H 0D6H 0D5H 0D4H 0D3H 0D2H 0D0H

ACC B SP DPL DPH PCON CKCON

DATA DATA DATA DATA DATA DATA DATA

0E0H 0F0H 81H 82H 83H 87H 8FH

;------------------ TIMERS registers --------------------TCON DATA 88H

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TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

BIT BIT BIT BIT BIT BIT BIT BIT

8FH 8EH 8DH 8CH 8BH 8AH 89H 88H

TMOD

DATA

89H

T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 C_T2 CP_RL2

DATA BIT 0CFH BIT 0CEH BIT 0CDH BIT 0CCH BIT 0CBH BIT 0CAH BIT 0C9H BIT 0C8H

0C8H

T2MOD DATA0C9H TL0 TL1 TH0 TH1 DATA DATA DATA DATA 8AH 8BH 8CH 8DH

TL2 DATA0CCH

TH2 DATA0CDH RCAP2L DATA0CAH RCAP2H DATA0CBH WDTRST WDTPRG DATA0A6H DATA0A7H

;------------------- UART registers -----------------------SCON SM0 FE SM1 SM2 REN TB8 RB8 TI RI DATA BIT 9FH BIT9FH BIT9EH BIT9DH BIT9CH BIT9BH BIT9AH BIT99H BIT98H 98H

SBUF

DATA

99H

SADEN DATA0B9H SADDR DATA0A9H ;-------------------- ADC registers ----------------------

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ADCLK DATA0F2H ADCON DATA0F3H ADDL DATA0F4H ADDH DATA0F5H ADCF DATA0F6H

;-------------------- FLASH EEPROM registers -----------FPGACON FCON EECON AUXR AUXR1 DATA0F1H

DATA0D1H DATA0D2H DATA8EH DATA0A2H

;-------------------- IT registers ----------------------IPL1 DATA0F8H IPH1 DATA0F7H IEN0 DATA0A8H

IPL0 DATA0B8H IPH0 DATA0B7H IEN1 DATA0E8H

; EA EC ET2 ES ET1 EX1 ET0 EX0 ;

IEN0 BIT 0AFH BIT 0AEH BIT 0ADH BIT 0ACH BIT 0ABH BIT 0AAH BIT 0A9H BIT 0A8H IEN1

ETIM BIT 0EAH EADC BIT ECAN BIT 0E9H 0E8H

;--------------------- PCA registers -------------------CCON DATA0D8H CF CR BIT 0DFH BIT 0DEH

CCF4BIT0D4H CCF3BIT0D3H CCF2BIT0D2H CCF1BIT0D1H CCF0BIT0D0H CMOD DATA0D9H CH DATA0F9H CL DATA0E9H CCAP0H DATA0FAH

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CCAP0L CCAPM0 CCAP1H CCAP1L CCAPM1 CCAP2H CCAP2L CCAPM2 CCAP3H CCAP3L CCAPM3 CCAP4H CCAP4L CCAPM4

DATA0EAH DATA0DAH DATA0FBH DATA0EBH DATA0DBH DATA0FCH DATA0ECH DATA0DCH DATA0FDH DATA0EDH DATA0DDH DATA0FEH DATA0EEH DATA0DEH

;------------------- CAN registers -------------------------CANGIT DATA 09BH CANTEC DATA 09CH CANREC DATA 09DH CANTCON DATA 0A1H CANMSG DATA 0A3H CANTTCL DATA 0A4H CANTTCH DATA 0A5H CANGSTA DATA 0AAH CANGCON DATA 0ABH CANTIML DATA 0ACH CANTIMH DATA 0ADH CANSTMPL DATA 0AEH CANSTMPH DATA 0AFH CANPAGE DATA 0B1H CANSTCH DATA 0B2H CANCONCH DATA 0B3H CANBT1 DATA 0B4H CANBT2 DATA 0B5H CANBT3 DATA 0B6H CANSIT1 DATA 0BAH CANSIT2 DATA 0BBH CANIDT1 DATA 0BCH CANIDT2 DATA 0BDH CANIDT3 DATA 0BEH CANIDT4 DATA 0BFH CANGIE DATA 0C1H CANIE1 DATA 0C2H CANIE2 DATA 0C3H CANIDM1 DATA 0C4H CANIDM2 DATA 0C5H CANIDM3 DATA 0C6H CANIDM4 DATA 0C7H CANEN1 CANEN2 DATA 0CEH DATA 0CFH

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Atmel Corporation
2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 487-2600

Atmel Operations
Memory
2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314

RF/Automotive
Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 Tel: 1(719) 576-3300 Fax: 1(719) 540-1759

Regional Headquarters
Europe
Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500

Microcontrollers
2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60

Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom

Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80

Asia
Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369

ASIC/ASSP/Smart Cards
Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743

Japan
9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581

e-mail
literature@atmel.com

Web Site
http://www.atmel.com

Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Companys standard warranty which is detailed in Atmels Terms and Conditions located on the Companys web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmels products are not authorized for use as critical components in life support devices or systems. Atmel Corporation 2004. All rights reserved. Atmel, the Atmel logo, andcombinations thereof are registered trademarks of Atmel Corporation or its subsidiaries. Windows Windows 98 , Windows XP, and Windows 2000 are trademarks and/ore registered trademark of Microsoft Corporation. Other terms and product names in this document may be the trademarks of others.

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