Scribd
Upload
29 views10 pages

Design A Simple 32-Bit

This document describes the design of a 32-bit single-cycle MIPS CPU. The CPU supports R-type instructions like ADD and SUB, I-type instructions like LW, SW, XORI, and BNE, and J-type instructions like J. All instructions are 32-bits wide with different formats. The CPU will use a register file, data memory, instruction memory, ALU, and control logic. The control logic will generate signals to read registers, perform ALU operations, control data memory access, write registers, and increment the PC each cycle.

Uploaded by

denholam
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
Download as ppt, pdf, or txt
29 views10 pages

Design A Simple 32-Bit

This document describes the design of a 32-bit single-cycle MIPS CPU. The CPU supports R-type instructions like ADD and SUB, I-type instructions like LW, SW, XORI, and BNE, and J-type instructions like J. All instructions are 32-bits wide with different formats. The CPU will use a register file, data memory, instruction memory, ALU, and control logic. The control logic will generate signals to read registers, perform ALU operations, control data memory access, write registers, and increment the PC each cycle.

Uploaded by

denholam
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
Download as ppt, pdf, or txt
Download as ppt, pdf, or txt
You are on page 1/ 10

Design a simple 32-bit MIPS Single-Cycle CPU

CPU Instructions: LW,SW J,JR,BNE XORI,ADD,SUB,SLT

Review of MIPS instructions format


All instructions are 32-bit wide. Three instructions format : R-type,I-type and J-type. Op: 6-bit opcode of the instruction Rs,Rt,Rd: 5-bit source and destination register numbers. Sa: 5-bit shift amount used by shift instructions Funct: 6-bit function field for R-type instructions Immediate: 16-bit immediate value or address offset Immediate: 26-bit target address of the jump instruction

OVERVIEW
Using

two previous lab projects(register and ALU) for single-cycle CPU design. Using datamem.v and instrmem.v for design. The instructions include: R-type: ADD,SUB,SLT,JR I-type : SW,LW,BNE,XORI J-type: J

Requirements of the Instruction Set

Memory Instruction memory where instructions are stored Data memory where data is stored Registers 32 32-bit general purpose registers, R0 is always zero Read source register Rs Read source register Rt Write destination register Rt or Rd Program counter PC register and Adder to increment PC Sign and Zero extender for immediate constant ALU for executing instructions

Components of the Datapath

Combinational Elements

ALU, Adder Immediate extender Multiplexers Instruction memory Data memory PC register Register file Timing of reads and writes
5 5 5 32 32 16

32 32

Extend

m u x
1
select

32

A L U

32

zero ALU result overflow

ExtOp

ALU control

Storage Elements
PC

Instruction
32

32 32 32

Data Memory
Address Data_out Data_in
32

Address

Instruction Memory

Registers
RA RB RW BusA BusB BusW
32

MemRead
32 32

MemWrite

Clocking methodology

Clock RegWrite

Main Control Signal Values


Op Xori Bne J Sw Lw Rformat Jr Reg ALU Mem regwirte Mem Mem branch jmp ALUOp extend Dst Src toReg Read Write 1 x x X 0 1 1 0 x 1 1 0 0 x x x 1 0 1 0 0 0 1 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 x 0 0 0 0 0 1 0 0 0 11 01 xx 00 00 10 0 x X 1 1 X

xx

You might also like