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Verilog HDL Lab Manual

Experiment No. 01
Write a program in Verilog HDL for AND Gate using Dataflow and Behavioral Modeling Style Block Diagram: A AND GATE B C

Boolean Equation: Truth Table:

C = A.B

A 0 0 1 1

B 0 1 0 1

C 0 0 0 1

a) Data Flow Modeling module test_aand (a,b,out); input a,b; output out; assign out = a & b; endmodule

b) Behavioral Modeling module test_andgg(a,b,cin); input a; input b; output cin; reg cin; always@ (a or b) begin Prepared By: Atush Jain (jainatush@gmail.com) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology Indore(M.P.)

Verilog HDL Lab Manual

case ({a,b}) 2'b00: begin cin = 1'b0; end 2'b01: begin cin = 1'b0; end 2'b10: begin cin = 1'b0; end 2'b11: begin cin = 1'b1; end default: begin cin = 1'b0; end endcase end endmodule

Prepared By: Atush Jain (jainatush@gmail.com) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology Indore(M.P.)

Verilog HDL Lab Manual

Experiment No. 02
Write a program in Verilog HDL for OR Gate using Dataflow and Behavioral Modeling Style Block Diagram: A OR GATE B C

Boolean Equation: Truth Table:

C=A+B

A 0 0 1 1

B 0 1 0 1

C 0 1 1 1

a) Data Flow Modeling module test_or_ex (a,b,out); input a,b; output out; assign out = a | b; endmodule

b) Behavioral Modeling module test_orgg(a,b,cin); input a; input b; output cin; reg cin; always@ (a or b) begin Prepared By: Atush Jain (jainatush@gmail.com) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology Indore(M.P.)

Verilog HDL Lab Manual

case ({a,b}) 2'b00: begin cin = 1'b0; end 2'b01: begin cin = 1'b1; end 2'b10: begin cin = 1'b1; end 2'b11: begin cin = 1'b1; end default: begin cin = 1'b0; end endcase end endmodule

Prepared By: Atush Jain (jainatush@gmail.com) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology Indore(M.P.)

Verilog HDL Lab Manual

Experiment No. 03
Write a program in Verilog HDL for NAND Gate using Dataflow and Behavioral Modeling Style Block Diagram: A NAND GATE B C

Boolean Equation: Truth Table:

C = (A.B)

A 0 0 1 1

B 0 1 0 1

C 1 1 1 0

a) Data Flow Modeling module test_nand_ex (a,b,out); input a,b; output out; assign out = ~(a & b); endmodule

b) Behavioral Modeling module test_nandgg(a,b,cin); input a; input b; output cin; reg cin; always@ (a or b) begin Prepared By: Atush Jain (jainatush@gmail.com) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology Indore(M.P.)

Verilog HDL Lab Manual

case ({a,b}) 2'b00: begin cin = 1'b1; end 2'b01: begin cin = 1'b1; end 2'b10: begin cin = 1'b1; end 2'b11: begin cin = 1'b0; end default: begin cin = 1'b0; end endcase end endmodule

Prepared By: Atush Jain (jainatush@gmail.com) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology Indore(M.P.)

Verilog HDL Lab Manual

Experiment No. 04
Write a program in Verilog HDL for NOR Gate using Dataflow and Behavioral Modeling Style Block Diagram: A NOR GATE B C

Boolean Equation: Truth Table:

C = (A + B)

A 0 0 1 1

B 0 1 0 1

C 1 0 0 0

a) Data Flow Modeling module test_nor_ex (a,b,out); input a,b; output out; assign out = ~(a | b); endmodule

b) Behavioral Modeling module test_norgg(a,b,cin); input a; input b; output cin; reg cin; always@ (a or b) begin Prepared By: Atush Jain (jainatush@gmail.com) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology Indore(M.P.)

Verilog HDL Lab Manual

case ({a,b}) 2'b00: begin cin = 1'b1; end 2'b01: begin cin = 1'b0; end 2'b10: begin cin = 1'b0; end 2'b11: begin cin = 1'b0; end default: begin cin = 1'b0; end endcase end endmodule

Prepared By: Atush Jain (jainatush@gmail.com) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology Indore(M.P.)

Verilog HDL Lab Manual

Experiment No. 05
Write a program in Verilog HDL for XOR Gate using Dataflow and Behavioral Modeling Style Block Diagram: A XOR GATE B C

Boolean Equation: Truth Table:

C = (A.B + A.B)

A 0 0 1 1

B 0 1 0 1

C 0 1 1 0

a) Data Flow Modeling module test_xor_ex (a,b,out); input a,b; output out; assign out = (a ^ b); endmodule

OR
module test_xorg2 (a,b,c); input a,b; output c; assign c = (~a & b) | (a & ~b); endmodule

Prepared By: Atush Jain (jainatush@gmail.com) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology Indore(M.P.)

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Verilog HDL Lab Manual

b) Behavioral Modeling module test_xorgg(a,b,cin); input a; input b; output cin; reg cin; always@ (a or b) begin case ({a,b}) 2'b00: begin cin = 1'b0; end 2'b01: begin cin = 1'b1; end 2'b10: begin cin = 1'b1; end 2'b11: begin cin = 1'b0; end default: begin cin = 1'b0; end endcase end endmodule

Prepared By: Atush Jain (jainatush@gmail.com) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology Indore(M.P.)

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Verilog HDL Lab Manual

Experiment No. 06
Write a program in Verilog HDL for XNOR Gate using Dataflow and Behavioral Modeling Style Block Diagram: A XNOR GATE B C

Boolean Equation: Truth Table:

C = (A.B + A.B)

A 0 0 1 1

B 0 1 0 1

C 1 0 0 1

a) Data Flow Modeling module test_xnor_ex (a,b,out); input a,b; output out; assign out = ~ (a ^ b); endmodule OR
module test_xorg2 (a,b,c); input a,b; output c; assign c = (a & b) | (~a & ~b); endmodule

Prepared By: Atush Jain (jainatush@gmail.com) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology Indore(M.P.)

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Verilog HDL Lab Manual

b) Behavioral Modeling module test_xnorgg(a,b,cin); input a; input b; output cin; reg cin; always@ (a or b) begin case ({a,b}) 2'b00: begin cin = 1'b1; end 2'b01: begin cin = 1'b0; end 2'b10: begin cin = 1'b0; end 2'b11: begin cin = 1'b1; end default: begin cin = 1'b0; end endcase end endmodule

Prepared By: Atush Jain (jainatush@gmail.com) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology Indore(M.P.)

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Verilog HDL Lab Manual

Experiment No. 07
Write a program in Verilog HDL for Half Adder using Dataflow and Gate Level Modeling Style Block Diagram: A HALF ADDER B CARRY SUM

Boolean Equation:

Sum = (A.B + A.B) Carry = A.B

Truth Table: A 0 0 1 1 B 0 1 0 1 SUM 0 1 1 0 CARRY 0 0 0 1

a) Data Flow Modeling

module test_halfadder (a, b, sum, carry); input a, b; output sum, carry; assign sum = a ^ b; assign carry = a & b; endmodule

b) Gate Level Modeling

module test_halfadd (a, b, sum, carry); input a, b; output sum, carry; xor(sum, a, b); and(carry, a, b); endmodule

Prepared By: Atush Jain (jainatush@gmail.com) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology Indore(M.P.)

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Verilog HDL Lab Manual

Experiment No. 08
Write a program in Verilog HDL for Full Adder using Dataflow, Gate Level and Structural Modeling Style Block Diagram: A SUM B C Boolean Equation: Sum = A Xor B Xor C Carry = A.B + B.C + C.A FULL ADDER CARRY

Truth Table: A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 SUM 0 1 1 0 1 0 0 1 CARRY 0 0 0 1 0 1 1 1

a) Data Flow Modeling

module test_fulladder_df (a, b, c, sum, carry); input a, b, c; output sum, carry; assign sum = a ^ b ^ c; assign carry = (a & b) | (b & c) | (c & a); endmodule

b) Gate Level Modeling

module test_fulladd (a, b, c, sum, carry); input a, b, c;

Prepared By: Atush Jain (jainatush@gmail.com) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology Indore(M.P.)

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output sum, carry; wire temp, temp1, temp2; xor(temp, a, b); and(temp1, a, b); xor(sum, temp, c); and(temp2, temp, c); or(carry, temp2, temp1); endmodule

Verilog HDL Lab Manual

c) Structural Modeling module struc_fa(a1, b1, c1, sum1, carry1); input a1, b1, c1; output sum1, carry1; wire temp, temp1, temp2; test_halfadder haa (.a(a1),.b(b1),.sum(temp),.carry(temp1)); test_halfadder hab (.a(temp),.b(c1),.sum(sum1),.carry(temp2)); and(carry1,temp1,temp2); endmodule

Prepared By: Atush Jain (jainatush@gmail.com) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology Indore(M.P.)

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Verilog HDL Lab Manual

Experiment No. 09
Write a program in Verilog HDL for 2:1 Multiplexer Block Diagram: A 2:1 Mux B Sel Boolean Equation: Output = A if {Sel = 0} Output = B if {Sel = 1}

Output

Truth Table: Input A B Sel 0 1 Output A B

a) 2:1 Mux using Conditional Assignment module mux_condi (f, a, b, sel); input a, b, sel; output f; assign f = sel ? a : b; endmodule

b) 2:1 Mux using always Statement module mux211(f, a, b, sel); output f; input a, b, sel; reg f; always@(a or b or sel) if (sel) f = a; else f = b; endmodule Prepared By: Atush Jain (jainatush@gmail.com) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology Indore(M.P.)

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Verilog HDL Lab Manual

Experiment No. 10
Write a program in Verilog HDL for 4:1 Multiplexer using Behavioral & Structural Modeling Style Block Diagram: A B C D Sel1 Sel2 Output 4:1 Mux

Truth Table: Input A B C D Sel1 0 0 1 1 Sel2 0 1 0 1 Output A B C D

a) Behavioral Modeling module test_mux41(a, s, c); input [3:0] a; input [1:0] s; output c; reg c; always @ (a or s) begin case(s) 2'b00: c = a[0]; 2'b01: c = a[1]; 2'b10: c = a[2]; 2'b11: c = a[3]; Prepared By: Atush Jain (jainatush@gmail.com) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology Indore(M.P.)

18 default: c = a[0]; endcase end endmodule

Verilog HDL Lab Manual

b) Sturctural Modeling module test_mux41_struc (a, b, s, cout); input [1:0]a, b, s; output cout; wire temp1, temp2; mux_condi la1 (.a(a[0]),.b(b[0]),.sel(s[0]),.f(temp1)); mux_condi la2 (.a(a[1]),.b(b[1]),.sel(s[0]),.f(temp2)); mux_condi la3 (.a(temp1),.b(temp2),.sel(s[1]),.f(cout)); endmodule

Prepared By: Atush Jain (jainatush@gmail.com) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology Indore(M.P.)

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Verilog HDL Lab Manual

Experiment No. 11
Write a program in Verilog HDL for 1: 2 De - Multiplexer using Behavioral Modeling Style Block Diagram: Y[0] Input 1:2 De - Mux Y[1]

Sel

Truth Table: Input A B Sel 0 1 Output Y[0] Y[1]

a)

Behavioral Modeling

module test_demux12 (a, s, c); input a; input s; output [1:0] c; reg c; always @(a or s) begin if (s) c = (a & ~s); else c = (a & s); end endmodule

Prepared By: Atush Jain (jainatush@gmail.com) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology Indore(M.P.)

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Verilog HDL Lab Manual

Experiment No. 12
Write a program in Verilog HDL for 2: 4 Decoder using Behavioral Modeling Style Block Diagram: I N P U T O U T P U T

2:4 Decoder

Truth Table: Input A 0 0 1 1 B 0 1 0 1 Output Y[0] Y[1] Y[2] Y[3]

a) Behavioral Modeling module test_decoder24 (a, b); input [1:0] a; output [3:0]b; reg [3:0] b; always @(a) begin b[3] = a[1] & a[0]; b[2] = !a[1] & a[0]; b[1] = a[1] & !a[0]; b[0] = !a[1] & !a[0]; end endmodule

Prepared By: Atush Jain (jainatush@gmail.com) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology Indore(M.P.)

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Verilog HDL Lab Manual

Experiment No. 13
Write a program in Verilog HDL for D Flip Flop using Behavioral Modeling Style Block Diagram: CLK RESET INPUT Truth Table: Input 0 1 Output 0 1 D Flip Flop OUTPUT

a) Behavioral Modeling module test_dff (d, clk, reset, q); input d, clk, reset; output q; reg q; always@ (posedge clk) begin if (reset) q <= 1'b0; else q <= d; end endmodule

Prepared By: Atush Jain (jainatush@gmail.com) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology Indore(M.P.)

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Verilog HDL Lab Manual

Experiment No. 14
Write a program in Verilog HDL for JK Flip Flop using Behavioral Modeling Style Block Diagram: CLK RESET J K Truth Table: Present State Q Q Q Q J 0 0 1 1 K 0 1 0 1 Output Q 0 1 Q

JK Flip Flop

OUTPUT

a) Behavioral Modeling module test_jk (j, k, clk, reset, q); input j, k, clk, reset; output q; reg q; always @(posedge clk or posedge reset) begin if(reset == 1'b1) q <= 1'b0; else case ({j, k}) 2'b00: q <= q; 2'b01: q <= 1'b0; 2'b10: q <= 1'b1; 2'b11: q <= ~q; default: q <= q; endcase end endmodule Prepared By: Atush Jain (jainatush@gmail.com) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology Indore(M.P.)

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Verilog HDL Lab Manual

Experiment No. 15
Write a program in Verilog HDL for T Flip Flop using Behavioral Modeling Style Block Diagram: CLK RESET INPUT Truth Table: Input 0 1 Output 1 0 T Flip Flop OUTPUT

a) Behavioral Modeling module test_tff (t, clk, reset, q); input t; input clk; input reset; output q; reg q; always @(negedge clk or posedge reset) begin if (reset == 1'b1) q <= 1'b0; else if (t == 1'b1) q <= ~ q; else if (t == 1'b0) q <= q; end endmodule Prepared By: Atush Jain (jainatush@gmail.com) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology Indore(M.P.)

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Verilog HDL Lab Manual

Experiment No. 16
Write a program in Verilog HDL for Serial In Serial Out [SISO] Shift Register using Behavioral & Structural Modeling Style Block Diagram:

Clk Input Reset D Flip Flop D Flip Flop D Flip Flop D Flip Flop OUT

a) Behavioral Modeling module test_siso (sin, clk, reset, sout); input sin; input clk; input reset; output sout; reg sout; reg r1,r2,r3; always @(posedge clk or posedge reset) begin if (reset) begin sout <= 1'b0; r1 <= 1'b0; r2 <= 1'b0; r3 <= 1'b0; end else begin Prepared By: Atush Jain (jainatush@gmail.com) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology Indore(M.P.)

25 r1 <= sin; r2 <= r1; r3 <= r2; sout <= r3; end end endmodule

Verilog HDL Lab Manual

b) Structural Modeling module test_siso_dff(sin, clk, reset, sout); input sin; input clk; input reset; output sout; wire w1,w2,w3; test_dff abc1 (.d(sin), .clk(clk ), .reset(reset), .q(w1) ); test_dff abc2 (.d(w1), .clk(clk), .reset(reset), .q(w2) ); test_dff abc3 (.d(w2), .clk(clk), .reset(reset), .q(w3) ); test_dff abc4 (.d(w3), .clk(clk), .reset(reset), .q(sout) ); endmodule

Prepared By: Atush Jain (jainatush@gmail.com) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology Indore(M.P.)

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Verilog HDL Lab Manual

Experiment No. 17
Write a program in Verilog HDL for Serial In Parallel Out [SIPO] Shift Register using Structural Modeling Style Block Diagram:

Clk Input Reset

D Flip Flop

D Flip Flop

D Flip Flop

D Flip Flop

Out4 Out1 Out2 Out3

a)

Structural Modeling

module test_sipo (sin, clk, reset, pout); input sin; input clk; input reset; output [3:0] pout; test_dff a1 (.d(sin), .clk(clk ), .reset(reset), .q(pout[0]) ); test_dff a2 (.d(pout[0]), .clk(clk), .reset(reset), .q(pout[1]) ); test_dff a3 (.d(pout[1]), .clk(clk), .reset(reset), .q(pout[2]) ); test_dff a4 (.d(pout[2]), .clk(clk), .reset(reset), .q(pout[3]) ); endmodule

Prepared By: Atush Jain (jainatush@gmail.com) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology Indore(M.P.)

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Verilog HDL Lab Manual

Experiment No. 18
Write a program in Verilog HDL for Parallel In Parallel Out [PIPO] Shift Register using Structural Modeling Style Block Diagram: Input2 Input3 Input4

Input1

Clk D Flip Flop Reset Out4 Out1 Out2 Out3 D Flip Flop D Flip Flop D Flip Flop

a) Structural Modeling module test_pipo(pin, clk, reset, pout); input [3:0] pin; input clk; input reset; output [3:0] pout; reg [3:0] pout; always @ (posedge clk or posedge reset) begin if (reset) pout <= 4'b0000; else pout <= pin; end endmodule Prepared By: Atush Jain (jainatush@gmail.com) Assistant Professor, Department of Electronics & Communication Engineering Sri Aurobindo Institute of Technology Indore(M.P.)