A

Seminar REPORT
ON
(8051 Microcontroller)
Academic Session 2013-1
S!"mitted in #artial $!l$illment o$ t%e re&!irements o$ t%e de'ree o$
BACHELOR OF TECHNOLOGY
(n
ELECTRONICS & COMMUNICATION ENGINEERING
Submitted to: Submitted by:
Mr. A!" !i#" $ro%. R. &. SINGH M'u !"'rm'
Semi'r Coordi'tor He'd o% (e)'rtmet
(E$ARTMENT OF ELECTRONICS AN( COMMUNICATION ENGINEERING
RA*ASTHAN TECHNICAL UNI+ERSITY, &OTA
-./.0-./1
AC&NO2LE(GEMENT
( )o!ld li*e to t%an*s almi'%t+ 'od $or 'i,in' me l!c* - $ait% in m+ a"ilities to com#lete t%is. (
)o!ld li*e to e/#ress m+ dee# sense o$ 'ratit!de to m+ teac%ers $or e/tendin' me t%e
o##ort!nit+ $or t%is and #ro,idin' all t%e necessar+ reso!rces and e/#ertise $or t%is #!r#ose.
( )o!ld li*e to con,e+ m+ dee#est 'ratit!de to 3Semi'r #uide4 $or s#arin' %is ,al!a"le
time $or me to disc!ss and clari$+ iss!e connected )it% t%is Seminar re#ort.

M'u !"'rm'
TABLE OF CONTENTS
C"')ter /: 5.6/ MICRONTROLLER77777777777./
1.1 (ntrod!ction00000000000000000..00..01
1.2 M12 8051 standards00000000000000..0..0...1
C"')ter -: BLOC& (IAGRAM OF 5.6/777777..-08
C"')ter 8: $IN (IAGRAM OF 5.6/77777......7..106
C"')ter 1: $ORTS OF MCU 5.6/7777777777790:
C"')ter 6: MEMORY OF MCU 5.6/77777.77777.7../.0/1
CONCLUSION...777777777777777.../6
REFERENCES...777777777777777.../9
CHA$TER0/
5.6/ MICROCONTROLLER
/./ INTRO(UCTION
T%e 8051 Microcontroller )as desi'ned in 13804s "+ (ntel. (ts $o!ndation )as on 5ar,ard
Arc%itect!re and )as de,elo#ed #rinci#all+ $or "rin'in' into #la+ in Em"edded S+stems. At $irst
it )as created "+ means o$ NMOS tec%nolo'+ "!t as NMOS tec%nolo'+ needs more #o)er to
$!nction t%ere$ore (ntel re-intended Microcontroller 8051 em#lo+in' 1MOS tec%nolo'+ and a
ne) edition came into e/istence )it% a letter 614 in t%e title name7 $or ill!stration8 80151. T%ese
most modern Microcontrollers need $e)er amo!nt o$ #o)er to $!nction in com#arison to t%eir
$orer!nners.
T%ere are t)o "!ses in 8051 Microcontroller one $or #ro'ram and ot%er $or data. As a res!lt7 it
%as t)o stora'e rooms $or "ot% #ro'ram and data o$ 9: "+ 8 si;e. T%e microcontroller com#rise
o$ 8 "it acc!m!lator - 8 "it #rocessin' !nit. (t also consists o$ 8 "it < re'ister as ma=orl+
$!nctionin' "loc*s. (t also %as a n!m"er o$ ot%er 8 "it and 19 "it re'isters.
>or internal $!nctionin' - #rocessin' Microcontroller 8051 comes )it% inte'rated "!ilt-in RAM.
T%is is #rime memor+ and is em#lo+ed $or storin' tem#orar+ data. (t is !n#redicta"le memor+
i.e. its data can 'et "e lost )%en t%e #o)er s!##l+ to t%e Microcontroller s)itc%ed O>>.
/.- MICROCONTROLLER 5.6/ STAN(AR(S:
:" o$ ROM is not m!c% at all.
128" o$ RAM (incl!din' S>Rs) satis$ies t%e !ser?s "asic needs.
#orts %a,in' in total o$ 32 in#!t@o!t#!t lines are in most cases s!$$icient to ma*e all
necessar+ connections to #eri#%eral en,ironment.
T%e )%ole con$i'!ration is o",io!sl+ t%o!'%t o$ as to satis$+ t%e needs o$ most #ro'rammers
)or*in' on de,elo#ment o$ a!tomation de,ices. One o$ its ad,anta'es is t%at not%in' is missin'
and not%in' is too m!c%. (n ot%er )ords7 it is created e/actl+ in accordance to t%e a,era'e !ser6s
taste and needs. Anot%er ad,anta'es are RAM or'ani;ation7 t%e o#eration o$ 1entral Processor
2nit (1P2) and #orts )%ic% com#letel+ !se all reco!rses and ena"le $!rt%er !#'rade.
CHA$TER0-
BLOCK DIAGRAM OF 8051
B;o<= (i'#r'm o% 5.6/ Mi<ro<otro;;er:
Microcontroller 8051 "loc* dia'ram is s%o)n "elo). Aet4s %a,e a closer loo* at eac% - e,er+
$raction or "loc* o$ t%is desi'n8
5.6/ Mi<ro<otro;;er B;o<= (i'#r'm E>);''tio:
<loc* Bia'ram o$ 8051 Microcontroller
CPU (Central Processor Unit):
As +o! ma+ "e $amiliar t%at 1entral Processor 2nit or 1P2 is t%e mind o$ an+ #rocessin'
mac%ine. (t scr!tini;es and mana'es all #rocesses t%at are carried o!t in t%e Microcontroller.
2ser %as no #o)er o,er t%e $!nctionin' o$ 1P2. (t inter#rets #ro'ram #rinted in stora'e s#ace
(ROM) and carries o!t all o$ t%em and do t%e #ro=ected d!t+.
Interrupts:
As t%e %eadin' #!t $or)ard7 (nterr!#t is a s!"-ro!tine call t%at reads t%e Microcontroller4s *e+
$!nction or =o" and %el#s it to #er$orm some ot%er #ro'ram )%ic% is e/tra im#ortant at t%at #oint
o$ time. T%e c%aracteristic o$ (nterr!#t is e/tremel+ constr!cti,e as it aids in emer'enc+ cases.
(nterr!#ts #ro,ides !s a met%od to #ost#one or dela+ t%e c!rrent #rocess7 carr+ o!t a s!"-ro!tine
tas* and t%en all o,er a'ain restart standard #ro'ram im#lementation.
T%e Micro-controller 8051 can "e assem"led in s!c% a manner t%at it momentaril+ sto#s or "rea*
t%e core #ro'ram at t%e %a##enin' o$ interr!#t. C%en s!"-ro!tine tas* is $inis%ed t%en t%e
im#lementation o$ core #ro'ram initiates a!tomaticall+ as !s!al. T%ere are 5 interr!#t s!##lies in
8051 Microcontroller7 t)o o!t o$ $i,e are #eri#%eral interr!#ts7 t)o are timer interr!#ts and one
is serial #ort interr!#t.
Memory:
Micro-controller needs a #ro'ram )%ic% is a set o$ commands. T%is #ro'ram enli'%tens
Microcontroller to #er$orm #recise tas*s. T%ese #ro'rams need a stora'e s#ace on )%ic% t%e+
can "e acc!m!lated and inter#ret "+ Microcontroller to act !#on an+ s#eci$ic #rocess. T%e
memor+ )%ic% is "ro!'%t into #la+ to acc!m!late t%e #ro'ram o$ Microcontroller is reco'ni;ed
as Pro'ram memor+ or code memor+. (n common lan'!a'e it4s also *no)n as Read Onl+
Memor+ or ROM.
Micro-controller also needs a memor+ to amass data or o#erands $or t%e s%ort term. T%e stora'e
s#ace )%ic% is em#lo+ed to momentaril+ data stora'e $or $!nctionin' is ac*no)led'ed as Bata
Memor+ and )e em#lo+ Random Access Memor+ or RAM $or t%is #rinci#le reason.
Microcontroller 8051 contains code memor+ or #ro'ram memor+ : so t%at is %as :< Rom
and it also com#rise o$ data memor+ (RAM) o$ 128 "+tes.
<!s8
>!ndamentall+ <!s is a 'ro!# o$ )ires )%ic% $!nctions as a comm!nication canal or mean $or
t%e trans$er Bata. T%ese "!ses com#rise o$ 87 19 or more ca"les. As a res!lt7 a "!s can "ear 8
"its7 19 "its all to'et%er. T%ere are t)o t+#es o$ "!ses8
1. Addre!! Bu!: Microcontroller 8051 consists o$ 19 "it address "!s. (t is "ro!'%t into #la+
to address memor+ #ositions. (t is also !tili;ed to transmit t%e address $rom 1entral
Processin' 2nit to Memor+.
2. ('t' Bu!: Microcontroller 8051 com#rise o$ 8 "its data "!s. (t is em#lo+ed to cart data.
Oscillator:
As )e all ma*e o!t t%at Microcontroller is a di'ital circ!it #iece o$ e&!i#ment7 t%!s it needs
timer $or its $!nction. >or t%is $!nction7 Microcontroller 8051 consists o$ an on-c%i# oscillator
)%ic% toils as a time so!rce $or 1P2 (1entral Processin' 2nit). As t%e #rod!cti,it+ t%!m#s o$
oscillator are stead+ as a res!lt7 it $acilitates %armoni;ed em#lo+ment o$ all #ieces o$ 8051
Microcontroller. (n#!t@o!t#!t Port8 As )e are ac&!ainted )it% t%at Microcontroller is em#lo+ed
in em"edded s+stems to mana'e t%e $!nctions o$ de,ices. T%!s to 'at%er it to ot%er mac%iner+7
'ad'ets or #eri#%erals )e need (@O (in#!t@o!t#!t) inter$acin' #orts in Micro-controller. >or t%is
$!nction Micro-controller 8051 consists o$ in#!t@o!t#!t #orts to !nite it to ot%er
#eri#%erals.Timers@1o!nters8 Micro-controller 8051 is incor#orated )it% t)o 19 "it co!nters -
timers. T%e co!nters are se#arated into 8 "it re'isters. T%e timers are !tili;ed $or meas!rin' t%e
inter,als7 to $ind o!t #!lse )idt% etc.

CHA$TER08
PIN DIAGRAM OF 8051
E>);''tio o 5.6/ $i (i'#r'm:
8051 Microcontroller Pin Bia'ram
>or e/#lainin' t%e #in dia'ram and #in con$i'!ration o$ microcontroller 80517 )e are ta*in' into
deli"eration a 0 #in B!al inline #ac*a'e (B(P). No) let4s st!d+ t%ro!'% #in con$i'!ration in
"rie$8-
$i! / ? 5:0 reco'ni;ed as Port 1. Bi$$erent $rom ot%er #orts7 t%is #ort doesn4t #ro,ide an+ ot%er
#!r#ose. Port 1 is a domesticall+ #!lled !#7 &!asi "i directional (n#!t@o!t#!t #ort.
$i ::0 As made clear #re,io!sl+ RESET #in is !tili;ed to set t%e micro-controller 8051 to its
#rimar+ ,al!es7 )%ereas t%e micro-controller is $!nctionin' or at t%e earl+ "e'innin' o$
a##lication. T%e RESET #in %as to "e set ele,ated $or t)o mac%ine rotations.
$i! /. ? /@:0 reco'ni;ed as Port 3. T%is #ort also s!##lies a n!m"er o$ ot%er $!nctions s!c% as
timer in#!t7 interr!#ts7 serial comm!nication indicators T/B - R/B7 control indicators $or
o!tside memor+ inter$acin' CR - RB7 etc. T%is is a domestic #!ll !# #ort )it% &!asi "i
directional #ort )it%in.
$i! /5 'd /::0 T%ese are em#lo+ed $or inter$acin' an o!ter cr+stal to 'i,e s+stem cloc*.
$i -.:0 Titled as Dss E it s+m"oli;es 'ro!nd (0 D) association.
$i!0 -/0-5:0 reco'ni;ed as Port 2 (P 2.0 E P 2.F) E ot%er t%an ser,in' as (n#!t@o!t#!t #ort7
senior order address "!s indicators are m!lti#le/ed )it% t%is &!asi "i directional #ort.
$i0 -::0 Pro'ram Store Ena"le or PSEN is em#lo+ed to inter#ret si'n $rom o!ter #ro'ram
memor+.
$i08.:0 E/ternal Access or EA in#!t is em#lo+ed to #ermit or #ro%i"it o!ter memor+
inter$acin'. ($ t%ere is no o!ter memor+ need7 t%is #in is dra''ed %i'% "+ lin*in' it to Dcc.
$i08/:0 A*a Address Aatc% Ena"le or AAE is "ro!'%t into #la+ to de-m!lti#le/ t%e address data
indication o$ #ort 0 ($or o!ter memor+ inter$acin'). T)o AAE t%ro"s are o"taina"le $or e,er+
mac%ine rotation.
$i! 8-08:: reco'ni;ed as Port 0 (P0.0 to P0.F) E ot%er t%an ser,in' as (n#!t@o!t#!t #ort7 lo)
order data - address "!s si'nals are m!lti#le/ed )it% t%is #ort (to #ro,ide t%e !se o$ o!ter
memor+ inter$acin'). T%is #in is a "i directional (n#!t@o!t#!t #ort (t%e sin'le one in
microcontroller 8051) and o!ter #!ll !# resistors are necessar+ to !tili;e t%is #ort as (n#!t@o!t#!t.
$i01.: termed as Dcc is t%e c%ie$ #o)er s!##l+. <+ and lar'e it is G5D B1.
5.6/ Mi<ro<otro;;er A));i<'tio!:
T%e microcontroller 8051 %as "een in a##lication in a lar'e amo!nt o$ mac%ines7 #rinci#all+
"eca!se it is sim#le to incor#orate in a #ro=ect or to assem"le a mac%ine aro!nd it. T%e $ollo)in'
are t%e *e+ s#ots o$ s#otli'%t8
1. Eer#y M''#emet: 1om#etent meas!rin' de,ice s+stems aid in calc!latin' ener'+
cons!m#tion in domestic and ind!striali;ed a##lications. T%ese meter s+stems are
#re#ared com#etent "+ inte'ratin' microcontrollers.
2. Tou<" !<ree!: A %i'% de'ree o$ microcontroller s!##liers inte'rate to!c% sensin'
a"ilities in t%eir desi'ns. Trans#orta"le de,ices s!c% as media #la+ers7 'amin' de,ices -
cell #%ones are some ill!strations o$ micro-controller inte'rated )it% to!c% sensin'
screens.
3. Automobi;e!: T%e microcontroller 8051 disco,ers "road reco'nition in s!##l+in'
a!tomo"ile sol!tions. T%e+ are e/tensi,el+ !tili;ed in %+"rid motor ,e%icles to control
en'ine ,ariations. (n addition7 )or*s s!c% as cr!ise #o)er and anti-"ra*e mec%anism %as
created it more ca#a"le )it% t%e amal'amation o$ micro-controllers.
. Medi<'; (eAi<e!: 5and+ medicinal 'ad'ets s!c% as 'l!cose - "lood #ress!re monitors
"rin' into #la+ micro-controllers7 to #!t on ,ie) t%e meas!rements7 as a res!lt7 o$$erin'
%i'%er de#enda"ilit+ in 'i,in' correct medical res!lts.
5. Medi<'; (eAi<e!: 5and+ medicinal 'ad'ets s!c% as 'l!cose - "lood #ress!re monitors
"rin' into #la+ micro-controllers7 to #!t on ,ie) t%e meas!rements7 as a res!lt7 o$$erin'
%i'%er de#enda"ilit+ in 'i,in' correct medical res!lts.

CHA$TER01
PORTS OF MCU 8051
2.3 Input/Output Pot! "I/O Pot!#
All 8051 microcontrollers %a,e (@O #orts eac% com#risin' 8 "its )%ic% can "e con$i'!red as
in#!ts or o!t#!ts. Accordin'l+7 in total o$ 32 in#!t@o!t#!t #ins ena"lin' t%e microcontroller to "e
connected to #eri#%eral de,ices are a,aila"le $or !se.
Pin con$i'!ration7 i.e. )%et%er it is to "e con$i'!red as an in#!t (1) or an o!t#!t (0)7 de#ends on
its lo'ic state. (n order to con$i'!re a microcontroller #in as an o!t#!t7 it is necessar+ to a##l+ a
lo'ic ;ero (0) to a##ro#riate (@O #ort "it. (n t%is case7 ,olta'e le,el on a##ro#riate #in )ill "e 0.
Similarl+7 in order to con$i'!re a microcontroller #in as an in#!t7 it is necessar+ to a##l+ a lo'ic
one (1) to a##ro#riate #ort. (n t%is case7 ,olta'e le,el on a##ro#riate #in )ill "e 5D (as is t%e
case )it% an+ TTA in#!t). T%is ma+ seem con$!sin' "!t don?t loose +o!r #atience. (t all "ecomes
clear a$ter st!d+in' sim#le electronic circ!its connected to an (@O #in.
I)utBOut)ut 3IBO4 )i
>i'!re a"o,e ill!strates a sim#li$ied sc%ematic o$ all circ!its )it%in t%e microcontroler connected
to one o$ its #ins. (t re$ers to all t%e #ins e/ce#t t%ose o$ t%e P0 #ort )%ic% do not %a,e #!ll-!#
resistors "!ilt-in.
Out)ut )i
A lo'ic ;ero (0) is a##lied to a "it o$ t%e P re'ister. T%e o!t#!t >E transistor is t!rned on7 t%!s
connectin' t%e a##ro#riate #in to 'ro!nd.
I)ut )i
A lo'ic one (1) is a##lied to a "it o$ t%e P re'ister. T%e o!t#!t >E transistor is t!rned o$$ and t%e
a##ro#riate #in remains connected to t%e #o)er s!##l+ ,olta'e o,er a #!ll-!# resistor o$ %i'%
resistance.
Ao'ic state (,olta'e) o$ an+ #in can "e c%an'ed or read at an+ moment. A lo'ic ;ero (0) and
lo'ic one (1) are not e&!al. A lo'ic one (0) re#resents a s%ort circ!it to 'ro!nd. S!c% a #in acts as
an o!t#!t.
A lo'ic one (1) is Hloosel+I connected to t%e #o)er s!##l+ ,olta'e o,er a resistor o$ %i'%
resistance. Since t%is ,olta'e can "e easil+ Hred!cedI "+ an e/ternal si'nal7 s!c% a #in acts as an
in#!t.
$ort .
T%e P0 #ort is c%aracteri;ed "+ t)o $!nctions. ($ e/ternal memor+ is !sed t%en t%e lo)er address
"+te (addresses A0-AF) is a##lied on it. Ot%er)ise7 all "its o$ t%is #ort are con$i'!red as
in#!ts@o!t#!ts.
T%e ot%er $!nction is e/#ressed )%en it is con$i'!red as an o!t#!t. 2nli*e ot%er #orts consistin'
o$ #ins )it% "!ilt-in #!ll-!# resistor connected "+ its end to 5 D #o)er s!##l+7 #ins o$ t%is #ort
%a,e t%is resistor le$t o!t. T%is a##arentl+ small di$$erence %as its conse&!ences8
($ an+ #in o$ t%is #ort is con$i'!red as an in#!t t%en it acts as i$ it H$loatsI. S!c% an in#!t %as
!nlimited in#!t resistance and indetermined #otential.
C%en t%e #in is con$i'!red as an o!t#!t7 it acts as an Ho#en drainI. <+ a##l+in' lo'ic 0 to a #ort
"it7 t%e a##ro#riate #in )ill "e connected to 'ro!nd (0D). <+ a##l+in' lo'ic 17 t%e e/ternal
o!t#!t )ill *ee# on H$loatin'I. (n order to a##l+ lo'ic 1 (5D) on t%is o!t#!t #in7 it is necessar+ to
"!ilt in an e/ternal #!ll-!# resistor.
Onl+ in case P0 is !sed $or addressin' e/ternal memor+7 t%e microcontroller )ill #ro,ide internal
#o)er s!##l+ so!rce in order to s!##l+ its #ins )it% lo'ic one. T%ere is no need to add e/ternal
#!ll-!# resistors.
$ort /
P1 is a tr!e (@O #ort7 "eca!se it doesn?t %a,e an+ alternati,e $!nctions as is t%e case )it% P07 "!t
can "e co$i'!red as 'eneral (@O onl+. (t %as a #!ll-!# resistor "!ilt-in and is com#letel+
com#ati"le )it% TTA circ!its.
$ort -
P2 acts similarl+ to P0 )%en e/ternal memor+ is !sed. Pins o$ t%is #ort occ!#+ addresses
intended $or e/ternal memor+ c%i#. T%is time it is a"o!t t%e %i'%er address "+te )it% addresses
A8-A15. C%en no memor+ is added7 t%is #ort can "e !sed as a 'eneral in#!t@o!t#!t #ort s%o)in'
$eat!res similar to P1.
$ort 8
All #ort #ins can "e !sed as 'eneral (@O7 "!t t%e+ also %a,e an alternati,e $!nction. (n order to
!se t%ese alternati,e $!nctions7 a lo'ic one (1) m!st "e a##lied to a##ro#riate "it o$ t%e P3
re'ister. (n tems o$ %ard)are7 t%is #ort is similar to P07 )it% t%e di$$erence t%at its #ins %a,e a
#!ll-!# resistor "!ilt-in.
$iC! Curret ;imit'tio!
C%en con$i'!red as o!t#!ts (lo'ic ;ero (0))7 sin'le #ort #ins can recei,e a c!rrent o$ 10mA. ($
all 8 "its o$ a #ort are acti,e7 a total c!rrent m!st "e limited to 15mA (#ort P08 29mA). ($ all
#orts (32 "its) are acti,e7 total ma/im!m c!rrent m!st "e limited to F1mA. C%en t%ese #ins are
con$i'!red as in#!ts (lo'ic 1)7 "!ilt-in #!ll-!# resistors #ro,ide ,er+ )ea* c!rrent7 "!t stron'
eno!'% to acti,ate !# to TTA in#!ts o$ AS series.
CHA$TER06
M$MOR% IN 8051
2.& M'(o) O*+n,-+t,on
T%e 8051 %as t)o t+#es o$ memor+ and t%ese are Pro'ram Memor+ and Bata Memor+. Pro'ram
Memor+ (ROM) is !sed to #ermanentl+ sa,e t%e #ro'ram "ein' e/ec!ted7 )%ile Bata Memor+
(RAM) is !sed $or tem#oraril+ storin' data and intermediate res!lts created and !sed d!rin' t%e
o#eration o$ t%e microcontroller. Be#endin' on t%e model in !se ()e are still tal*in' a"o!t t%e
8051 microcontroller $amil+ in 'eneral) at most a $e) :" o$ ROM and 128 or 259 "+tes o$ RAM
is !sed. 5o)e,er0
All 8051 microcontrollers %a,e a 19-"it addressin' "!s and are ca#a"le o$ addressin' 9 *"
memor+. (t is neit%er a mista*e nor a "i' am"ition o$ en'ineers )%o )ere )or*in' on "asic core
de,elo#ment. (t is a matter o$ smart memor+ or'ani;ation )%ic% ma*es t%ese microcontrollers a
real H#ro'rammers4 'ood+H.
$ro#r'm Memory
T%e $irst models o$ t%e 8051 microcontroller $amil+ did not %a,e internal #ro'ram memor+. (t
)as added as an e/ternal se#arate c%i#. T%ese models are reco'ni;a"le "+ t%eir la"el "e'innin'
)it% 803 ($or e/am#le 8031 or 8032). All later models %a,e a $e) :"+te ROM em"edded. E,en
t%o!'% s!c% an amo!nt o$ memor+ is s!$$icient $or )ritin' most o$ t%e #ro'rams7 t%ere are
sit!ations )%en it is necessar+ to !se additional memor+ as )ell. A t+#ical e/am#le are so called
loo*!# ta"les. T%e+ are !sed in cases )%en e&!ations descri"in' some #rocesses are too
com#licated or )%en t%ere is no time $or sol,in' t%em. (n s!c% cases all necessar+ estimates and
a##ro/imates are e/ec!ted in ad,ance and t%e $inal res!lts are #!t in t%e ta"les (similar to
lo'arit%mic ta"les).
5o) does t%e microcontroller %andle e/ternal memor+ de#ends on t%e EA #in lo'ic state8
EAD. (n t%is case7 t%e microcontroller com#letel+ i'nores internal #ro'ram memor+ and
e/ec!tes onl+ t%e #ro'ram stored in e/ternal memor+.
EAD/ (n t%is case7 t%e microcontroller e/ec!tes $irst t%e #ro'ram $rom "!ilt-in ROM7 t%en t%e
#ro'ram stored in e/ternal memor+.
(n "ot% cases7 P0 and P2 are not a,aila"le $or !se since "ein' !sed $or data and address
transmission. <esides7 t%e AAE and PSEN #ins are also !sed.
('t' Memory
As alread+ mentioned7 Bata Memor+ is !sed $or tem#oraril+ storin' data and intermediate res!lts
created and !sed d!rin' t%e o#eration o$ t%e microcontroller. <esides7 RAM memor+ "!ilt in t%e
8051 $amil+ incl!des man+ re'isters s!c% as %ard)are co!nters and timers7 in#!t@o!t#!t #orts7
serial data "!$$ers etc. T%e #re,io!s models %ad 259 RAM locations7 )%ile $or t%e later models
t%is n!m"er )as incremented "+ additional 128 re'isters. 5o)e,er7 t%e $irst 259 memor+
locations (addresses 0->>%) are t%e %eart o$ memor+ common to all t%e models "elon'in' to t%e
8051 $amil+. Aocations a,aila"le to t%e !ser occ!#+ memor+ s#ace )it% addresses 0-F>%7 i.e.
$irst 128 re'isters. T%is #art o$ RAM is di,ided in se,eral "loc*s.
T%e $irst "loc* consists o$ "an*s eac% incl!din' 8 re'isters denoted "+ R0-RF. Prior to
accessin' an+ o$ t%ese re'isters7 it is necessar+ to select t%e "an* containin' it. T%e ne/t memor+
"loc* (address 20%-2>%) is "it- addressa"le7 )%ic% means t%at eac% "it %as its o)n address (0-
F>%). Since t%ere are 19 s!c% re'isters7 t%is "loc* contains in total o$ 128 "its )it% se#arate
addresses (address o$ "it 0 o$ t%e 20% "+te is 07 )%ile address o$ "it F o$ t%e 2>% "+te is F>%).
T%e t%ird 'ro!# o$ re'isters occ!#+ addresses 2>%-F>%7 i.e. 80 locations7 and does not %a,e an+
s#ecial $!nctions or $eat!res.
Additio'; RAM
(n order to satis$+ t%e #ro'rammers4 constant %!n'er $or Bata Memor+7 t%e man!$act!rers
decided to em"ed an additional memor+ "loc* o$ 128 locations into t%e latest ,ersions o$ t%e
8051 microcontrollers. 5o)e,er7 it4s not as sim#le as it seems to "e0 T%e #ro"lem is t%at
electronics #er$ormin' addressin' %as 1 "+te (8 "its) on dis#osal and is ca#a"le o$ reac%in' onl+
t%e $irst 259 locations7 t%ere$ore. (n order to *ee# alread+ e/istin' 8-"it arc%itect!re and
com#ati"ilit+ )it% ot%er e/istin' models a small tric* )as done.
C%at does it meanJ (t means t%at additional memor+ "loc* s%ares t%e same addresses )it%
locations intended $or t%e S>Rs (80%- >>%). (n order to di$$erentiate "et)een t%ese t)o
#%+sicall+ se#arated memor+ s#aces7 di$$erent )a+s o$ addressin' are !sed. T%e S>Rs memor+
locations are accessed "+ direct addressin'7 )%ile additional RAM memor+ locations are
accessed "+ indirect addressin'.
Memory e>)'!io
(n case memor+ (RAM or ROM) "!ilt in t%e microcontroller is not s!$$icient7 it is #ossi"le to add
t)o e/ternal memor+ c%i#s )it% ca#acit+ o$ 9:" eac%. P2 and P3 (@O #orts are !sed $or t%eir
addressin' and data transmission.
>rom t%e !ser4s #oint o$ ,ie)7 e,er+t%in' )or*s &!ite sim#l+ )%en #ro#erl+ connected "eca!se
most o#erations are #er$ormed "+ t%e microcontroller itsel$. T%e 8051 microcontroller %as t)o
#ins $or data read RBK(P3.F) and PSENK. T%e $irst one is !sed $or readin' data $rom e/ternal
data memor+ (RAM)7 )%ile t%e ot%er is !sed $or readin' data $rom e/ternal #ro'ram memor+
(ROM). <ot% #ins are acti,e lo). A t+#ical e/am#le o$ memor+ e/#ansion "+ addin' RAM and
ROM c%i#s (5ard)ard arc%itect!re)7 is s%o)n in $i'!re a"o,e.
E,en t%o!'% additional memor+ is rarel+ !sed )it% t%e latest ,ersions o$ t%e microcontrollers7
)e )ill descri"e in s%ort )%at %a##ens )%en memor+ c%i#s are connected accordin' to t%e
#re,io!s sc%ematic. T%e )%ole #rocess descri"ed "elo) is #er$ormed a!tomaticall+.
C%en t%e #ro'ram d!rin' e/ec!tion enco!nters an instr!ction )%ic% resides in e/ternal
memor+ (ROM)7 t%e microcontroller )ill acti,ate its control o!t#!t AAE and set t%e $irst
8 "its o$ address (A0-AF) on P0. (1 circ!it F51T5F3 #asses t%e $irst 8 "its to memor+
address #ins.
A si'nal on t%e AAE #in latc%es t%e (1 circ!it F51T5F3 and immediatel+ a$ter)ards 8
%i'%er "its o$ address (A8-A15) a##ear on t%e #ort. (n t%is )a+7 a desired location o$
additional #ro'ram memor+ is addressed. (t is le$t o,er to read its content.
Port P0 #ins are con$i'!red as in#!ts7 t%e PSEN #in is acti,ated and t%e microcontroller
reads $rom memor+ c%i#.
Similar occ!rs )%en it is necessar+ to read location $rom e/ternal RAM. Addressin' is
#er$ormed in t%e same )a+7 )%ile read and )rite are #er$ormed ,ia si'nals a##earin' on t%e
control o!t#!ts RB (is s%ort $or read) or CR (is s%ort $or )rite).
Addre!!i#
C%ile o#eratin'7 t%e #rocessor #rocesses data as #er #ro'ram instr!ctions. Eac% instr!ction
consists o$ t)o #arts. One #art descri"es C5AT s%o!ld "e done7 )%ile t%e ot%er e/#lains 5OC
to do it. T%e latter #art can "e a data ("inar+ n!m"er) or t%e address at )%ic% t%e data is stored.
T)o )a+s o$ addressin' are !sed $or all 8051 microcontrollers de#endin' on )%ic% #art o$
memor+ s%o!ld "e accessed8
(ire<t Addre!!i#
On direct addressin'7 t%e address o$ memor+ location containin' data to "e read is s#eci$ied in
instr!ction. T%e address ma+ contain a n!m"er "ein' c%an'ed d!rin' o#eration (,aria"le). >or
e/am#le8
Since t%e address is onl+ one "+te in si;e (t%e lar'est n!m"er is 255)7 onl+ t%e $irst 255 locations
o$ RAM can "e accessed t%is )a+. T%e $irst %al$ o$ RAM is a,aila"le $or !se7 )%ile anot%er %al$
is reser,ed $or S>Rs.
MOV A,33h; Means: move a number from address 33 hex. to accumulator
Idire<t Addre!!i#
On indirect addressin'7 a re'ister containin' t%e address o$ anot%er re'ister is s#eci$ied in
instr!ction. Bata to "e !sed in t%e #ro'ram is stored in t%e letter re'ister. >or e/am#le8
(ndirect addressin' is onl+ !sed $or accessin' RAM locations a,aila"le $or !se (ne,er $or
accessin' S>Rs). T%is is t%e onl+ )a+ o$ accessin' all t%e latest ,ersions o$ t%e microcontrollers
)it% additional memor+ "loc* (128 locations o$ RAM). Sim#l+ #!t7 )%en t%e #ro'ram
enco!nters instr!ction incl!din' HLI si'n and i$ t%e s#eci$ied address is %i'%er t%an 128 ( F>
%e/.)7 t%e #rocessor *no)s t%at indirect addressin' is !sed and s*i#s memor+ s#ace reser,ed $or
S>Rs.
MOV A,@R0; Means: Store the value from the register whose address is in the
R0 register
into accumulator
On indirect addressin'7 re'isters R07 R1 or Stac* Pointer are !sed $or s#eci$+in' 8-"it addresses.
Since onl+ 8 "its are a,ila"le7 it is #ossi"le to access onl+ re'isters o$ internal RAM t%is )a+
(128 locations )%en s#ea*in' o$ #re,io!s models or 259 locations )%en s#ea*in' o$ latest
models o$ microcontrollers). ($ an e/tra memor+ c%i# is added t%en t%e 19-"it BPTR Re'ister
(consistin' o$ t%e re'isters BPTRA and BPTR5) is !sed $or s#eci$+in' address. (n t%is )a+ it is
#ossi"le to access an+ location in t%e ran'e o$ 9:.
CONCLUSION
(n t%is #a#er ( %a,e tried to 'i,e an o,er,ie) on Microcontroller 8051 s+stem o$
o#comm!nication. A %i'% s#eed comm!nication de,ices needs to "e de,elo#ed $or
interconnectin' t%e net)or* o$ internet and com#!ters. (n man+ net)or*s M12 8051 is !sed
"eca!se it !sed as a ,erstile de,ice in sin'le c%i#..
( %a,e learned a"o!t t%e #orts7 timers7 memor+ o$ M12.
5ence in t%e last ( can sa+ t%at M12 8051 is an emer'in' de,ice in s#ite no)ada+s not a
sin'le internet)or*in' a##lication is im#ossi"le )it%o!t s!c% an eas+ so!rce o$ electronics.

REFERENCES
Microcontroller details8
.ttp///000.(,1o'.2o(/2.+pt'!/3,'0/45/2.+pt'52580515(,2o2onto66'5
+2.,t'2tu'/
(ntrod!ction a"o!t M12 8051 and timers
%tt#8@@))).8051intel.com@doc!ments@introd!ction@
%tt#8@@))).em"ededelectronics.com
Fundamentals of Microcontroller
Genius publication