Solder Mask Design Basics
Solder Mask Design Basics
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SOLDER
MASK DESIGN BASICS
US
Standards
Information on the use of solder mask is contained in IPC-SM-840C Qualification and Performance of Permanent
Solder Mask. The specification is intended to facilitate evaluation of solder mask by a vendor using a standard
board system, and to enable designer, manufacturer, and user together to qualify a production board process.
The test methods and conditions in IPC-SM-840C are based on end use and environmental reliability
requirements for two classes1 of user:
1
Older IPC documents refer to Class 1, Class 2, and Class 3. For all practical purposes there is no Class 1
Class of application, T or H
Physical size of the board
Thickness of the conductors and the type of metallisation finish
Track density on the surface, and how evenly spread the tracks are
How many holes there are, of what size, and with what annular ring tolerance
Whether components are placed on top of tracks
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Layout Issues
Figure 2 shows in schematic a typical solder mask application. Notice the very definite three-dimensional nature
of the board surface.
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It is important that:
The solder mask should be kept away from any plated through-hole and its associated land or pad
Each conductor track should be covered
The laminated area should be completely covered
Adjacent conductors should not be exposed (not as Figure 3)
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Excessively thick solder mask can cause drawbridging where used between component pads, and omitting mask
between chip component pads is sometimes recommended to reduce this effect, and also make cleaning easier.
This of course is not possible when tracks are run in the spaces between pads. The two different types of solder
mask window needed are shown in Figure 5, from which it is clear that pocket windows need solder mask that is
much better defined and in register than gang windows.
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