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SystemVerilog Interface

SystemVerilog introduces interfaces which allow signals to be grouped together and represented as a single port. This simplifies design by avoiding duplicated signal declarations across modules and reducing errors. Interfaces can define communication protocols and checks. Modports allow modules to view only relevant interface signals. Interface methods implement communication protocols and can be imported or exported between modules through interfaces. Interfaces support transaction level modeling by encapsulating communication details between modules.

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Ranadheer Reddy
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562 views

SystemVerilog Interface

SystemVerilog introduces interfaces which allow signals to be grouped together and represented as a single port. This simplifies design by avoiding duplicated signal declarations across modules and reducing errors. Interfaces can define communication protocols and checks. Modports allow modules to view only relevant interface signals. Interface methods implement communication protocols and can be imported or exported between modules through interfaces. Interfaces support transaction level modeling by encapsulating communication details between modules.

Uploaded by

Ranadheer Reddy
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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SystemVerilog Interfaces

Gi-Yong Song
Chungbuk National University, Korea

SystemVerilog

SystemVerilog extends the Verilog language with a


powerful interface construct. Interfaces offer a new
paradigm for modeling abstraction. The use of
interfaces can simplify the task of modeling and
verifying large, complex designs.

Interface concepts
The Verilog language connects modules together
through module ports. This is a detailed method of
representing the connections between blocks of a
design that maps directly to the physical
connections that will be in the actual hardware.

For large designs, however, using module ports to


connect blocks of a design together can become
tedious and redundant

Disadvantages of Verilogs
module ports
Declarations must be duplicated in multiple
modules.
Communication protocols must be duplicated in
several modules.
There is a risk of mismatched declarations in
different modules.
A change in the design specification can require
modifications in multiple modules.

Advantages of SystemVerilog
interfaces

SystemVerilog adds a powerful new port type to


Verilog, called an interface. An interface allows a
number of signals to be grouped together and
represented as a single port. The declarations of
the signals that make up the interface are
contained in a single location.

Each module that uses these signals then has a


single port of the interface type, instead of many
ports with the discrete signals.

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In example above, all the signals that are in


common between the major blocks of the design
have been encapsulated into a single locationthe
interface declaration called main_bus

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The top-level module and all modules that make


up these blocks do not repetitively declare these
common signals. Instead, these modules simply
use the interface as the connection between them.

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SystemVerilog interface contents

The discrete signal and ports for communication


can be defined in one location, the interface
Communication protocols can be defined in the
interface.
Protocol checking and other verification routines
can be built directly into the interface.
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Differences between modules and


interface(1)

Unlike a module, an interface cannot contain


instances of modules or primitives that would
create a new level of implementation hierarchy.

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Differences between modules and


interface(2)

An interface can be used as a module port, which


is what allows interfaces to represent
communication channels between modules. It is
illegal to use a module in a port list.

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Differences between modules and


interface(3)

An interface can contain modports, which allow


each module connected to the interface to see the
interface differently.

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Using interface as module ports

With SystemVerilog, a port of a module can be


declared as an interface type, instead of the
Verilog input, output or inout port directions.

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Explicitly named interface ports

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Generic interface ports

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Interface modports

SystemVerilog interfaces provide a means to


define different views of the interface signals that
each module sees on its interface port.
The definition is made within the interface, using
the modport keyword. Modport is an abbreviation
for module port.

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Specifying which modport view to


use

As part of the interface connection to a module


instance
As part of the module port declaration in the
module definition

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Using modports to different sets of


connections

In a more complex interface between several


different modules, it may be that not every module
needs to see the same set of signals within the
interface.
Modports make it possible to create a customized
view of the interface for each module connected.

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Interface methods

SystemVerilog allows tasks and functions to be


declared within an interface. These tasks and
functions are referred to as interface methods.

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The code for communication between modules is


only written once, as interface methods, and
shared by each module connected using the
interface.

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Within each module, the interface methods are


called, instead of implementing the communication
protocol functionality within the module.

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Importing interface methods

If the interface is connected via a modport, the


method must be specified using the import
keyword. The import definition is specified within
the interface, as part of a modport definition.

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Import using just the task or function name


Import using a full prototype of the task or function

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Import using a task or function


name

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Import using a task or function


prototype

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Exporting tasks and functions

SystemVerilog interfaces and modports provide a


mechanism to define a task or function in one
module, and then export the task or function
through an interface to other modules.

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Exporting a task or function to the


entire interface

A task or function can also be exported to an


interface without using a modport.
This is done by declaring an extern prototype of
the task or function within the interface.

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Restrictions on exporting tasks


and functions

It is illegal to export the same task name from two


different modules, or two instances of the same
module, into the same interface, unless an extern
forkjoin declaration is used. The multiple export of
a task corresponds to a multiple response to a
broadcast.

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Parameterized interface

Parameters can be used in interfaces to make


vector sizes and other declarations within the
interface reconfigurable using Verilogs parameter
redefinition constructs.

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Behavioral and Transaction


Level Modeling

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Transaction level modeling in


SystemVerilog

Whereas behavior level modeling raises the


abstraction of the block functionality, transaction
level modeling raises the abstraction level of
communication between blocks and subsystems,
by hiding the details of both control and data flow
across interfaces.

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In SystemVerilog, a key use of the interface


construct is to be able to separate the descriptions
of the functionality of modules and the
communication between them.

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Transaction level modeling is a concept, and not a


feature of a specific language,

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A fundamental capability that is needed for TLMs


is to be able to encapsulate the lower level details
of information exchange into function and task
calls across an interface. The caller only needs to
know what data is sent and returned, with the
details of the transmission being hidden in the
function/task call.

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Transaction level models via


interface

This broadcast request with single response can be


conveniently modeled with the extern forkjoin task
construct in SystemVerilog interfaces.

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References
Stuart Sutherland, Simon Davidmann and Peter Fla
ke, SystemVerilog for Design (2nd Edition): A Gui
de to Using SystemVerilog for Hardware Design an
d Modeling, Springer, 2006.
Chris Spear, SystemVerilog for Verification (2nd E
dition): A Guide to Learning the Testbench Langua
ge Features, Springer, 2008.
Mike Mintz, Robert Ekendahl, Hardware Verificatio
n with SystemVerilog : An Object-Oriented Framew
ork, Springer, 2007.
Mark Zwolinski, Digital System Design With
SystemVerilog, Addision-Wesley,2010.
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