Design Compiler

Training Course of Design
Compiler
T. W. Tseng, ARES Lab 2008 Summer Training Course of Design Compiler
REF:
CIC Training Manual Logic Synthesis with Design Compiler, July, 2006
TSMC 0.18um
0 18um Process 1.8-Volt
1 8-Volt SAGE-XTM Stand Cell Library Databook
Databook, September,
September 2003
TPZ973G TSMC 0.18um Standard I/O Library Databook, Version 240a, December 10, 2003
Artisan User Manual
Speaker:
T. J. Chen
p
Advanced Reliable
Systems (ARES) Lab.
Outline
Basic Concept of the Synthesis
Synthesis Using Design Compiler
Advanced Reliable Systems (ARES) Lab.
Basic Concept of the Synthesis
Cell-Based Design Flow

Spec.
System Level
MATLAB/ C/ C++/ System C/

ADS/ Covergen (MaxSim)
Verilog/ VHDL
NC-Verilog/ ModelSim
Debussy (Verdi)/ VCS
Logic Synthesis
Conformal/
Formality
Design/ Power Compiler
Design for Test
DFT Compiler/ TetraMAX
Gate Level
NC-Verilog/ ModelSim
Debussy (Verdi)/ VCS
Layout Level
SOC Encounter/ Astro
Post-Layout
Verification
Syntest
Ph
hysical Com
mpiler/
Mag
gma Blast Fusion
RTL Level
Memory Generator
GDS II
DRC/ LVS (Calibre)
PVS: Calibre xRC/ NanoSim
(Time/ Power Mill)
Tape Out
What is Synthesis
Synthesis = translation + optimization + mapping
if(high_bits == 2b10)begin
residue = state_table[i];
[ ];
end
else begin
residue = 16h0000;
end
Translate (HDL Compiler)
HDL Source
(RTL)
No Timing Info.
Generic Boolean
(GTECT)
Optimize + Mapping
(Design Compiler)
Timing Info.
The synthesis is constraint driven
and technology independent !!
Target Technology
5
Compile
Optimized Design
RTL code
or netlist
Compile
Attributes &
Constraints
Schematic
Reports
Technology
Lib
Library
(Can be set by the GUI
interface or user-defined
Script File !!)
(Gate-Level Netlist)
(Timing,
(
g, Area,, Power,, ,, etc)
)
Flatten
Structure
Logic Level Optimization
Gate Level Optimization

Technology
Library
Map
6
Synthesizable Verilog
Verilog Basis
p
parameter
declarations
wire, wand, wor declarations
reg declarations
input output
input,
output, inout declarations
continuous assignments
module instructions
gate instructions
always blocks
task statements
function definitions
for, while loop
Synthesizable Verilog primitives cells
and, or, not, nand, nor, xor, xnor

bufif0,, bufif1,, notif0,, notif1
Synthesizable Verilog (Cont)

Operators
Binaryy bit-wise ( ~, &, ||, ^, ~^ )

Unary reduction ( &, ~&, |, ~|, ^, ~^ )
Logical ( !, &&, || )
2s
2
s complement arithmetic ( +,
+ -, *, /,
/ %)
Relational ( >, <, >=, <= )
Equality ( ==, != )
Logic shift ( >>, << )
Conditional ( ?: )
Concatenation ( { } )
Notice Before Synthesis

Area
Your RTL design
Better
Functional verification by some high-level language
Cycle
Time
Also, the code coverage of your test benches should be verified (i.e. VN)
Coding style checking (i.e. n-Lint)

n Lint)
Good coding style will reduce most hazards while synthesis
Better optimization process results in better circuit performance
Easy
E
debugging
d b
i after
f synthesis
h i
Constraints
The area and timing of your circuit are mainly determined by your
circuit architecture and coding style
There is always a trade-off between the circuit timing and area
In fact, a super tight timing constraint may be worked while synthesis,
but failed in the Place & Route (P&R) procedure
Synthesis Using Design Compiler
10
Related Files
Folder
GTL
Name
Description
.synopsys
y p y _dc.setup
p
Design
g compiler
p
setup
p file
my_script.tcl
Synthesis script file
my_design.v
Verilog files
tmy_design.v
Test bench
tsmc18.v
Verilog model of standard cells
Ex:
11
<.synopsys_dc.setup> File
link_library : the library used for interpreting input description
Any cells instantiated in your HDL code

Wire load or operating condition modules used during synthesis
target_library : the ASIC technology which the design is mapped

symbol library : used for schematic generation
symbol_library
search_path : the path for unsolved reference library
synthetic_path
y
_p
: designware
g
library
y
12
<.synopsys_dc.setup> File (Cont)

MEMs libraries are also included in this file
Ex:
Add a search path
MEM Libraries (.db file)
((.synopsys_dc.setup
y p y _
p File))
Note that the MEM DB files are converted from
the LIB files which are generated from the Artisan !!
13
Settings for Using Memory

Convert *.lib to *.db
any memory LIB file
%> dc
dc_shell
shell t
dc_shell-t> read_lib t13spsram512x32_slow_syn.lib
dc_shell-t> write_lib t13spsram512x32 -output \
user library name, which should
t13spsram512x32_slow_syn.db
Modify <.synopsys_dc.setup> File:
be the same as the library name

in the Artisan
set link_library * slow.db t13spsram512x32_slow.db

dw_foundation.sldb
memory DB file
add to the file
set target
target_library
library slow
slow.db
db t13spsram512x32_slow.db
t13spsram512x32 slow db
add a search path to this file
Before the synthesis,

y
, the memoryy HDL model should be
blocked in your netlist
14
Synthesis Flow
Design Import
DFT Insertion
Setting Design
Environment
Compile After
DFT
Setting Clock
Constraints
Assign Violation
Avoidance
Setting Design
Rule Constraints
Naming Rule
Changing
Compile the
Design
Save Design
15
Getting Started
Prepare Files:
*.v files
*.db files (i.e. memory is used)
S h i script
Synthesis
i fil
file (i
(i.e. d
described
ib d llater))
linux %> dv& (XG Mode)

Tool Bar
Logic Hierarchy
View
Log Window
Command Line
((GUI view of the Design

g Vision))
16
Read File
Design Import
Read netlists or other design descriptions into Design Compiler

File/Read
Supported formats
Verilog: .v
VHDL: .vhd
System Verilog: .sv
EDIF
PLA (Berkeley Espresso): .pla
Synopsys internal formats:
DB (binary): .db
db
Enhance db file: .ddc
Equation: .eqn
State table: .st
st
{ Command Line }
read file format

read_file
format verilog file name
17
PAD Parameters Extraction

Input PAD
Input
p delay
y
Input driving
Output PAD
Output
O
t t delay
d l
Output loading
(delay, driving)
CORE.v
(delay, loading)
(chip_const.tcl)
CHIP v
CHIP.v
{ Command Line }
current_design CHIP
characterize [get_cells CORE]
current_design CORE
write script format
write_script
format dctcl o
o chip_const.tcl
chip const.tcl
18
Uniquify
Select the most top design of the hierarchy
Hierarchy/Uniquify/Hierarchy
(Log Window)
(Design View)
uniquify
{ Command Line }
19
Design Environment
Setting Design
Environment
Setting Operating Environment

Setting Input Driving Strength
Setting Output Loading
Setting Input/Output Delay
Setting Wire Load Model
20
Setting Operating Condition

Attributes/Operating Environment/Operating Conditions
Setup/Hold time is evaluated
{ Command Line }
set_operating_conditions max slow max_library slow min fast\

min_library
library fast
fast
-min
21
Setting Drive Strength/Input Delay for PADs

Assume that we use the input PAD PDIDGZ
my design
Input PAD
FF
PAD
(PDIDGZ)
{ Command Line }
set_drive [expr 0.288001] [all_inputs]

set_input
p _delay
y [[expr
p 0.34]] clock clk [[all_inputs]
p
]
22
Setting Load/Output Delay for PADs

Assume that we use the output PAD PDO24CDG
my design
D
clk
Output PAD
FF
PAD
I
OEN
(PDO24CDG)
{ Command Line }
set_load [expr 0.06132] [all_outputs]
set_output_delay
_
p _
y [expr
[ p 2]] [all_outputs]
[ _
p
]
23
Setting Wire Load Model

Attributes/Operating Environment/Wire Load
(Worst Case)
Recommend
{ Command Line }
set_wire_load_model name tsmc18_wl10 library slow

set wire lode mode top
set_wire_lode_mode
top
24
Clock Constraints
Setting Clock
Constraints
Period
Waveform
Uncertainty
Skew
Latency
Source latency
Network latency
Transition
Input transition
Clock transition
Combination Circuit Maximum Delay Constraints
25
Sequential Circuit Specify Clock

Select the clk pin on the symbol
Attributes/Specify
p
y Clock
set_fix_hold:
t fi h ld respectt the
th hold
h ld time
ti
requirement of all clocked flip-flops
set_dont_touch_network: do not re-buffer
the clock network
{ Command Line }
creat_clock period 10 [get_ports clk]

set_dont_touch_network [get_clocks clk]
set fix hold [get_clocks
set_fix_hold
[get clocks clk]
26
Setting Clock Skew

Different clock arrival time
Ex:
FF
clk
FF
FF
FF
experience
Small circuit: 0.1 ns

Large circuit: 0
0.3
3 ns
(Ti i Report)
(Timing
R
t)
{ Command Line }
set clock uncertainty 0.1 [get_clocks

set_clock_uncertainty
[get clocks clk]
27
Setting Clock Latency

Source latency is the propagation time from the actual clock origin to
the clock definition point in the design
This setting can be avoid if the design is without the clock generator
Ex:
Your Design
3ns
Origin of Clock
experience
Source Latency
Small circuit: 1 ns
Large circuit: 3 ns
{ Command Line }
set clock latency 1 [get

set_clock_latency
[get_clocks
clocks clk]
28
Setting Ideal Clock

Since we usually let the clock tree synthesis (CTS)
procedure performed in the P&R (i
(i.e.
e
set_dont_touch_network), the clock source driving
capability is poor
Thus, we can set the clock tree as an ideal network
without driving issues
Avoid the hazard in the timing evaluation
{ Command Line }
set ideal network [get_ports

set_ideal_network
[get ports clk]
29
Setting Clock Transition

set_clock_transition
create_clock
CLK
experience
< 0.5ns
CIC tester: 0.5
0 5 ns
{ Command Line }
set input
set_
put_ttransition
a s t o max
a 0.5
0 5 [all
[a _inputs]
puts]
30
Combination Circuit Maximum Delay

Constraints
For combinational circuits primarily (i.e. design with no clock)
Select the start & end points of the timing path

Attributes/Optimization Constraints/Timing Constraints
Ex:
Maximum
Delay
Constraint
(5ns = 200 MHz)
Minimum
Delay
Constraint
31
Design Rule Constraints
Setting Design
Rule Constraints
Area Constraint
Fanout Constraint
32
Setting Area/Fanout Constraint

Attributes/Optimization
Constraints/Design
Constraints
If you only concern the circuit
area but dont
area,
don t care about the
timing
You can set the max area

constraints to 0
{ Command Line }
set_max_area 0
set max fanout 50 [get
set_max_fanout
[get_designs
designs CORE]
33
Compile the Design
Compile the
Design
Design/Compile Design
{ Command Line }
compile map_effort high boundary_optimization

34
Assign Problem
Assign Violation
Avoidance
The syntax of assign may cause problems in the LVS

assign \A[19] = A[19];
assign \A[18] = A[18];
assign \A[17] = A[17];
assign \A[16] = A[16];
assign \A[15] = A[15];
assign ABSVAL[19] = \A[19];
g ABSVAL[16]
[ ] = \A[16];
[ ]
assign
BUFX1 X37X( .I(A[19]), .Z(ABSVAL[19]) );

{ Command Line }
set_fix_multiple_port_nets all constants buffer_constants [get_designs *]

35
Floating Port Removing

Due to some ports in the standard cells are not used in
your design
{ Command Line }
remove_unconnected_ports blast_buses [get_cells hierarchical *]

36
Chang Naming Rule Script
Naming Rule
Changing
Purpose: Let the naming-rule definitions in the gate-level netlist are

the same as in the timing file (e.g. *.sdf file)
Also, the wrong naming rules may cause problems in the LVS
{ Command Line }
set bus_inference_style {%s[%d]}
set bus_naming_style {%s[%d]}
set hdlout_internal_busses true
change_names -hierarchy -rule verilog
define_name_rules name_rule -allowed "A-Z a-z 0-9 _" -max_length 255 -type cell
define_name_rules name_rule -allowed "A-Z a-z 0-9 _[]" -max_length 255 -type net
define name rules name
define_name_rules
name_rule
rule -map {{
{{"\\*cell\\*""cell"}}
\\ cell\\ cell }}
define_name_rules name_rule -case_insensitive
change_names -hierarchy -rules name_rule
37
Save Design
Save Design
Five design files:
*.spf: test protocol file for ATPG tools (i.e. TetraMax)

*.sdc: timing constraint file for P&R
*.vg: gate-level netlist for P&R
*.sdf:
sdf: timing file for Verilog simulation
*.db: binary file (i.e. all the constraints and synthesis results are
recorded)
{ Command Line }
write_test_protocol -f stil -out "CHIP.spf"
write sdc CHIP
write_sdc
CHIP.sdc
sdc
write -format verilog -hierarchy -output "CHIP.vg"
write_sdf -version 1.0 CHIP.sdf
y -output
p "CHIP.db"
write -format db -hierarchy
38
Synthesis Report
Report Design Hierarchy

Report Area
Design View
Report Timing
Critical Path Highlighting
Timing Slack Histogram
39
Report Design Hierarchy

Hierarchy report shows the component used in your each block & its
hierarchy
Design/Report Design Hierarchy
Ex:
40
Report Area
Design/Report Area
Ex:
(0.18um Cell-Library: 1 gate 10 um2)

(0.13um Cell-Library: 1 gate 5 um2)
(um2)
41
Design View
List/Design View
Ex:
All the block area are listed !!
42
Report Timing
Timing/Report Timing
Ex:
setup time
Critical Path
max: setup time

min: hold time
Slack = Data Require Time Data Arrival Time
43
Critical Path Highlighting

View/Highlight/Critical Path
Ex:
44
Timing Slack Histogram

Timing/Endpoint Slack
Totally 190 paths are in the slack range between

0 to 1.78
Ex:
Resolution
45
Edit Your Own Script File

For convenient, you should edit your own synthesis script file.
Whenever you want to synthesis a new design, you just only change
some parameters in this file.
Ex:
Execute Script File
File/Execute Script
Or use source your_
script.dc
p
in dc_shell
command line
46
Gate-Level Simulation
Include the Verilog model of standard cell and gate-level netlist to
your test bench
Standard Cell Library
Gate- Level Netlist
Add the following Synopsys directives to the test bench
*.sdf File
Instance Name
Delay
47
Lab.
cp r f /usr2/grad97/tjchen/tutorial_of_DV/Lab .
48

Design Compiler

Uploaded by

Design Compiler

Uploaded by

Training Course of Design

Advanced Reliable Systems (ARES) Lab.

Basic Concept of the Synthesis

Advanced Reliable Systems (ARES) Lab.

Cell-Based Design Flow

MATLAB/ C/ C++/ System C/

Design/ Power Compiler

Design for Test

DFT Compiler/ TetraMAX

SOC Encounter/ Astro

Translate (HDL Compiler)

Logic Level Optimization

Gate Level Optimization

Synthesizable Verilog primitives cells

and, or, not, nand, nor, xor, xnor

Advanced Reliable Systems (ARES) Lab.

Synthesizable Verilog (Cont)

Binaryy bit-wise ( ~, &, ||, ^, ~^ )

Advanced Reliable Systems (ARES) Lab.

Notice Before Synthesis

Your RTL design

Functional verification by some high-level language

Coding style checking (i.e. n-Lint)

Synthesis Using Design Compiler

Advanced Reliable Systems (ARES) Lab.

Synthesis script file

Verilog model of standard cells

Advanced Reliable Systems (ARES) Lab.

Any cells instantiated in your HDL code

target_library : the ASIC technology which the design is mapped

Advanced Reliable Systems (ARES) Lab.

<.synopsys_dc.setup> File (Cont)

Add a search path

MEM Libraries (.db file)

Settings for Using Memory

any memory LIB file

Modify <.synopsys_dc.setup> File:

be the same as the library name

set link_library * slow.db t13spsram512x32_slow.db

Before the synthesis,

Advanced Reliable Systems (ARES) Lab.

Advanced Reliable Systems (ARES) Lab.

linux %> dv& (XG Mode)

((GUI view of the Design

Read netlists or other design descriptions into Design Compiler

read file format

PAD Parameters Extraction

Setting Operating Environment

Advanced Reliable Systems (ARES) Lab.

Setting Operating Condition

Setup/Hold time is evaluated

set_operating_conditions max slow max_library slow min fast\

Setting Drive Strength/Input Delay for PADs

set_drive [expr 0.288001] [all_inputs]

Setting Load/Output Delay for PADs

set_load [expr 0.06132] [all_outputs]

Setting Wire Load Model

set_wire_load_model name tsmc18_wl10 library slow

Combination Circuit Maximum Delay Constraints

Advanced Reliable Systems (ARES) Lab.

Sequential Circuit Specify Clock

creat_clock period 10 [get_ports clk]

Setting Clock Skew

Small circuit: 0.1 ns

set clock uncertainty 0.1 [get_clocks

Setting Clock Latency

set clock latency 1 [get

Setting Ideal Clock

set ideal network [get_ports

Setting Clock Transition

Combination Circuit Maximum Delay

Select the start & end points of the timing path

(5ns = 200 MHz)

Advanced Reliable Systems (ARES) Lab.

Design Rule Constraints

Advanced Reliable Systems (ARES) Lab.