HI TECH

Institute of Engineering and Technology

Faculty Name: Raj Gopal Mishra

Department :ECE

Subject Name: Microprocessor

Subject Code : EE-402

Semester : 4th
Total Number of Students: 40
L.No.
1
2

Topic Planed

Evolution of microprocessors

4
5

General architecture of a MP
Instruction classification
Overview of the 8085 Instructi
General architecture of a MP

Pin Diagram and Internal Arch

Timings and Machine cycle

Memory Interfacing

9
10

Stacks & Stack pointers

11

Classification & Structure of In

12

Simple Program

13

Pin Diagram of 8086

14

Internal Architecture

15

Working of Architecture

Addressing Modes

16

Minmum and Maximum Mode

17 8084 bus controller
18

memory organization
19 Addressing Modes
20

instruction set and templates

21

Interrupt structure

22

Assembly language programm

23

Simple Programs

24
25
26

Assembler
statement syntax
Common Assembler Directive

27

Creating Source file

Planned
Date

Taken
Date

Remark

HOD
Signature

Topic Planed
28
29
30
31
32
33
34
35

memory mapping
I/O mapped peripherals
parallel I/O 8255-PPI
Modes 0 & 1 of 8255
Serial I/O (8251)
RS- 232C
8253/54 timer Counter
8259 interrupt controller

36
37
38
39
40

AD converter
DA converter
Their interfacing with micropr
Introduction to different types
Memory organization

Planned
Date

Taken
Date

Remark

HOD
Signature

1.1.Traditional Block diagram of digital computer Page 7

1.2. Interl Microprocessors: Historical Prospective Page 9
1.3. Organization of Microprocessor-Based System Page 9-12
1.4. low level language, High level Language, Assembly Language Page 13-17
1.5. Summery: Key terms-> MPU,BUS,RAM,ROM,R/WM,Word,Instruction,Mnemonic,Machine language
2.1. Hardware Model Page 32
2.2. 8085 Programming Model Page 33
2.3. Flags* (Details will be covered in Architecture)

Page 33-34

3.1. The 8085 instruction set Page 35-36

3.2. Instruction Word Size: 1-byte,2-byte,3-byte instruction, Data Format

Page 37-41

3.3. Example : How Microprocessor Interprets any number Page 41-42

3.4. Instruction and Data Storage: Memeory Page 41
4.1. Symbols and Data Transfer (Copy) Instructions. Page 48
4.2. Arithmetic Instuction. Page 48
5.1. Logic and Bit Manipulation Instructions Page 49
5.2. Branch Instructions. Page 49
5.3. Machine Control Instructions. Page 50
6.1. Various Function perfomed by Micriprocessor Page 58
6.2. Micoprocessor Initiated Operation Page 59
6.3. Peripheral (or externally initiated) operations Page 62-63
6.4. 8085 Bus Organization Page: 59-60
7.1.Memory Classification Page 76
7.2. Logic Devices for Interfacing: Tri-State Devices, Buffer, Bi-Directional Buffer, Decoder (2x4, 3x8), En
7.3. Flip-Flop or Latch as a Storage Element Page 64

8.1.Memory Map and Addresses Page 69

8.2. Example 3.1 Page 70
8.3. Memory Address Range of a 1K memory chip, Example 3.2 Page 72-73
8.4. Memory Address Lines, Example 3.3 and Example 3.4 Page 74
9.1. Memory and Instruction Fetch Page: 75
9.2. I/O with 8-Bit Addresses (Peripheral -Mapped I/O) Page 80
9.3. I/Os with 16-Bit Addresses (Memory-Mapped I/O) Page 81
10.1. Multiplexed Address/Data Bus Page 98
10.2. Control and Status Signals Page 98
10.3. Externally Initiated Singals, Including Interrupts Page 99-100
10.4. Power Supply and Clock frequency 98-99
10.5. Serial I/O Ports Page 100
11.1. Example 4.1 Page 100-101
11.2. Opcode Fetch Timing Cycle Page 102
11.3. Demultiplexing the Bus AD7-AD0 Page 103
11.4. Generating Control Signals Page 104-105
12.1. ALU Page 107
12.2. Flags Detail Page 107
12.3. Timing and contol Unit Page 108
12.4. Instruction Register and Decoder Page 108
12.5. Register Array Page 108
12.6. Example 4.2 Page 108
12.7. Review of Important Concepts Page 108-109
13.1. Opcode Fetch Machin Cycle Page 111
13.2. Memory Read Machin Cycle Page 118
13.3. Memory Write Cycle page 119
13.4. Example 4.3 Page 112
14.1. Memory Structure and Its Requirements Page 116-117
14.2. Basic Concepts in Memory Interfacing
14.3.Address Decoding, Interfacing Circuit and Memory Addresses Page 119-121
14.4. Memory Designing Problem Page 127
16.1.Peripheral I/O Instructions Page 140-141
16.2. I/O Execution Page 141-143
16.3. IN Instruction page 143-144
16.4. Device Selection and Data Transfer Page 144 and Page 145
16.5. Absolute vs. Partial Decoding Page 146-147
17.1. Input Inferfacing Page 147-148

17.2. Interfacing I/Os Using Decoders Pages 148-149

17.3. Review of Important Concepts
18.1. Example 5.2.1 with cirucite analysis Page 150-151
18.2. Seven -Segment LED Display as an Output Device Page 152-153
18.3. Interfacing Circuit and its analysis Page 154
19.1. Data Input from DIP Switches Page 155
19.2. hardware (74LS244-tri-state octal buffer) Page 155
19.3. Interfacing Circuit Page 156
19.4. Multiple Port Addresses Page 156
20.1. Memory mapped I/O technique Page 157
20.2. Execution of Memory-related Data transfer Instructions Page 158-159
20.3. Output Port and Its Address Page 159 and Page 161
20.4. Input Port and its Address Page 161
20.5. Comparison of Memory-Mapped I/O and Peripheral I/O Page 162
21.1. Data transfer (copy) operation Page 177-179
21.2. Flow Chart Page 181
21.3. Example 6.1.2 Page 180
21.4. Prgramming Format Page 182
21.5. Example 6.1.3. Page 185
22.1. Arithmetic operations
22.2. Example 6.3 Page 189
22.3. Example 6.2.2 Page 191
22.4. Example 6.2.3 (Subtraction) Page 193
22.5. Example 6.2.4 (Subtraction of two unsigned number) page 194
23.1. Logic operatins Page 196-197
23.2. Example 6.3.2 (Data Masking with Logic AND) Page 198
23.3. Example 6.3.3 OR, Exclusive-OR, and NOT Page 199-200
23.4. Example 6.3.4 Setting and Resetting Specific Bits Page 200
24.1. Branching operation Page 204
24.2. Example 6.4.2 ( Unconditional Jump to Set Up a continuous Loop) Page 205
24.3 Conditional Jumps Page 206
24.4 Example 6.4.4 ( Testing of the Carry Flag) Page 207

25.1. Example 6.4.5 Page 211-213

25.2. Lopping: Continous Loop and Conditional Loop
25.3. Counting Page 230
25.4. Indexing Page 230
25.5. Example of Looping, Counting and Indexing

27.1
27.2
27.3
27.4
27.5
27.6

16-Bit Data Transfer to Register Pair (LXI) Page 232

Data transfer (Copy) from Memory to Microprocessor Page 233
Data transfer (Copy) from Microprocessor to Memory Page 235
Example 7.3 Page 234
Example 7.4 Page 236
Example 7.5 Page 238

28.1
28.2
28.3
28.4

Example 7.2.6 (Block Transfer of Data Bytes) Page 238-239

Arithmetic Operation related to Memory Page 242
Example 7.6 Page 242-243
Example 7.7 Page 243-244

29.1
29.2
29.3
29.4

Example 7.3.2 (Addition with Carry) Page 244-245

Logic operation: Rotate Page 248-249
Example 7.9 Page 248
Example 7.10 Page 249

30.1 Example 7.4.2 (Checking Sign with Rotate Instructions) Page 250
30.2 Logic operation Compare Page 254
30.3 Example 7.5.8 (Use of Compare Instruction to Indicate End of Data string) Page 256-259
31.1 Example 7.5.3 (Program: Sorting) Page 259
31.2 Counter and Time Delays Page 276
32.1
32.2
32.3
32.4

Time Delay Using One Register Page 276

Time Delay Using a Register Pair page 278
Time Delay Using a Loop with a Loop Techique Page 279
Counter Design with Time Delay Page 281

33.1 Program: Hexadecimal Counter Page 282

33.2 Program: Zero-To- Nine (Modulo Ten)* Counter Page 285
34.1 Program: Generating Pulse Waveforms Page 289
34.2 Program for Debugging Page 291-292
35.1 Stack, Additional Instruction Related Stack Page 296-297
35.2 Example 9.1 Page 297
35.3 Example 9.2 Page 298
36.1 Example 9.1.2 (Program: Resetting and Displaying Flags) Page 307
36.2 Subroutine , Instructin (Call, Ret) Page 305
36.3 Example 9.3 Page 307
36.4 Program Exection: Call and RET Page 315-316
37.1 Program Traffic Signal Controller Page 310-311
38.1 Restart, Conditinal Call, And Return Instructions Page 315

38.2 Advanced Subroutine Concepts (Nesting, Multiple-Ending Subroutines) Page 316

39.1 The 8085 Interrupt Page 377
39.2 RST (Restart) Instructions Page 378
39.3 Example 12.1.2 (An Implementation of the 8085 interrupt) Page 379
40.1 Multiple Interrupts and Priorities Page 384
40.2 8085 Vectored Interrupts Page 385
40.3 Example 12.1, Example 12.2, Example 12.3 Page 389
41.1 Exaple 12.2.3 Interrupt-Driven Clock Page 390
43.1 Block Diagram of 8255A:Control Logic, Control Word Page 460
43.2. Modes of 8255A Page 461
44.1 BSR (Bit Set/Rset) Mode Page 466
44.2 Example 15.2 Page 467
44.3 Mode 0: Simple Input or Output Page 463
44.4 Example 15.1 Page 463-464
45.1 Mode 1: Input Control Signal Page 473
45.2 Control and Status Words Page 474
45.3. Programming the 8255A in Mode 1 Page 474-475
46.1 Mode 1: Output Control Signals Page 475
46.2 Control and Status Words Page 475
46.3 Example 15.1.6 (An Application of the 8255A in the Handshake Mode ) Page 476-477
47.1 Mode 2: Bidirectional Data Transfer Page 479
47.2 Block Diagram of the 8254 Page 494
47.3 Data Bus Buffer Page 494
47.4 Control Logic Page 494
47.5 Control Word Register Page 495-496
48.1 Mode 0: Interrupt on terminal Count Page 499
48.2 Mode 1: Hardware-Retriggerable One-Shot (Programmable One shot) Page 500
48.3 Mode 2: Rate Generator Page 500
48.4 Mode 3: Square - wave Generator Page 501
48.5 Mode 4:Software Triggered Strobe Page 502
48.6 Mode 5:Hardware Triggered Strobe Page 503
49.1 Programming the 8254 Page 497
49.2 Example 15.4.3 (The 8254 as a Counter) Page 497
49.3 Example 15.3 Page 501
49.4 Example 15.3 Page 502
50.1 Basics of DMA
50.2 The 8237 DMA Controller Page 514

50.3 DMA Channels and interfaceing Page 515

50.4: System Interface Page 518
50.5 DMA Execution Page 519
50.6 Example 15.8 Page 518-519

51.1 Block Diagram of 8259A Page 505

51.2 Read/Write Logic Page 506
51.3 Control Logic Page 506
51.4 Interrupt Registers and Priority Resolver Page 506
51.5 Interrupt Operation Page 506
51.6 Priority Modes and Other Features of 8259A Page 508
51.7 Additional Features of the 8259A Page 509
52.1 Interfacing Keyboard and Seven segment display Page 479-487
52.1.1 Problem Aalysis
52.1.2 Circuit of Interfacing a Keyboard and a Seven Segment LED Page 481
52.1.3 Keyboard: Flow Chart and Program for Key Check, keycode and key debounce Page 482-485
52.1.4 Seven Segment Display Program Page 486
52.1.5 Main Program Page 486

e,Assembly Language,low-level language,High-level language, Compiler, Interpreter, Assembler, Monitor Program.

coder,D-Flip-Flop and clock Page 89-90