Question 1: Sequential Circuit Design

The ABC Saw Mill is the smallest Canadian producer of fire wood. They wish to
automate their log-cutting efforts and have decided to design the conveyor belt
system shown in Figure 1. You have been commissioned to develop the
synchronous sequential saw controller that can detect the length of wood logs
and cut only the logs that are long. For simplicity, you may assume that all logs
are of only two sizes, either LONG or SHORT. Using two sensors (S 1 and S2),
the SHORT logs will never pass under both sensors at the same time, however,
the LONG logs will. The sensor input will be set to logic high when a log is under
the sensor, otherwise the input it will remain at zero. After a LONG log is
detected (i.e. the end of the log passes sensor S 2), the SAW output must be
asserted, which will pause the conveyor belt and lower the saw to cut the log.
You may also assume that there will always be sufficient space between logs
such that two logs will never be under the sensors at the same time.
For all input sequences that are not physically possible, ensure that your system
returns to the initial state. Furthermore, all unused states should return your
system to the initial state.
1) Draw the State Transition Diagram for the sequential saw controller.
2) Derive the State Transition Table for the sequential saw controller.
3) Draw the sequential circuit diagram for the sequential saw controller using
only positive edge-triggered JK flip-flops. Minimize any combination logic
using K-maps.

Figure 1: Circuit used in Question 1: Sequential Circuit Design

SOLUTION to Question 1

PRESENT
STATE
A
B
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1

INPUTS
S1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

S2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

NEXT
STATE
A+
B+
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0

FF INPUTS
JA
0
0
0
0
0
0
0
1
X
X
X
X
X
X
X
X

KA
X
X
X
X
X
X
X
X
1
0
1
0
1
1
1
1

JB
0
0
1
0
X
X
X
X
0
0
0
0
X
X
X
X

OUTPUT
KB
X
X
X
X
1
1
0
1
X
X
X
X
1
1
1
1

SAW
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0

SOLUTION to Question 1
S1 S2
AB
00

00

01

11

10

1
X
X

X
X

01

11

10

X
X
01
X
X
11
1
1
10
1
KA = B + S2

X
X
1

X
X
1
1

01

X
X
X
X
JA = BS1S2
11

10

S1 S2
AB
00

00

S1 S2
AB
00

00

01

11

10

X
X

X
X

X
X

1
X
X

11

10

01
11
10

JB = AS1S2
S1 S2
AB
00

00

01

X
X
X
X
01
1
1
1
0
11
1
1
1
1
10
X
X
X
X
KB = A + B + S1 + S2

Question 2: Sequential Circuit Analysis

The sequential circuit in Figure 2 is a sequence detector that asserts its output Z
when a 4-bit serial input sequence is detected. The serial input is denoted X.
This circuit is synchronized with respect to the clock signal CLK. The 16x3 ROM
has the following programming table:
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

INPUTS
A2
A1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1

A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

OUTPUTS
Y2
Y1
Y0
0
0
0
0
1
0
1
1
0
1
0
0
0
1
0
1
1
0
0
1
0
0
1
1
0
0
0
1
0
1
1
1
0
0
1
1
1
0
0
1
1
1
1
0
0
1
0
1

a) Derive the state transition table.

b) Draw the state transition diagram.
c) What four bit sequence does this circuit detect? (Hint: State 00 is the initial
state.)

Figure 2: Circuit used in Question 2: Sequential Circuit Analysis

SOLUTION to Question 2
(a)
Present States
QA
QB
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1

Input
X
0
1
0
1
0
1
0
1

FF Inputs
DA
TB
0
0
0
1
0
1
1
1
1
1
1
0
0
1
0
1

Next State
QA(t+1) QB(t+1)
0
0
0
1
0
0
1
0
1
1
1
0
0
0
0
0

Output
Z
0
0
0
0
0
0
0
1

(b)

(c) 1101

Question 1 (Arithmetic)
Let ADD4 be a 4-bit adder. We will use this adder as a building block to design other
arithmetic circuits.
1- Consider MUL3 circuit shown in Figure 1(a). This circuit has a 4-bit input A and a 6bit output P such that P = 3*A. Design this circuit using a single ADD4 component and
HA/FA cells.

2- Consider the 4-bit adder shown in Figure 1(b). We call this adder ADD4_MOD. The
behavior of the circuit depends on the values of inputs M1 and M0 as shown in Table 1 .
For instance, the circuit performs the addition of the two 4-bit numbers A and B modulo 8
when M1M0 = 01. The result of this addition appears at output S. Output Cout is the
carry-out of adding A and B when M1M0 = 00, in all other modes Cout = 0. Design
ADD4_MOD using the following components : ADD4, multiplexers and logic gates.
M1

M0

Operation

0 A+B

1 (A+B)mod8

0 (A+B)mod4
Table 1

3- Carry-select adders (CSA) are used to cope with the carry propagation delays
encountered in ripple-carry adders. A typical CSA is made of smaller adder -blocks.
Some blocks are replicated to consider the cases when the carry-in is 0 and when the
carry-in is 1. An incomplete 12-bit CSA is shown in Figure 2. Complete this figure by
adding the missing components and connections.

Solution
1-

2-

3- Straightforward.

Question 2 (PLDs)
The truth table of a binary to excess-3 encoder is shown in Table 2. We like to implement
this circuit using a PLA.
1- Derive, using K-maps, the simplified expressions for each output and its complement.
2- Deduce a programming table for the PLA. You should minimize the number of product
terms.

ABCD

WXYZ

0000

0011

0001

0100

0010

0101

0011

0110

0100

0111

0101

1000

0110

1001

0111

1010

1000

1011

1001

1100

1010

0000

1011

0001

1100

0010

1101

1101

1110

1110

1111

1111
Table 2.

Solution
1- W = BD + BC + AB'C'
W' = B'C + BC'D' + A'B'C'
X = A'BC'D' + A'B'D + A'B'C + AC'D + ABC
X' = B'C'D' + AC'D' + A'BD + A'BC + AB'C
Y = C'D' + A'CD + ABC
Y'= C'D + A'CD' + AB'C

Z = A'D' + B'C'D' + ABD + ACD

Z' = A'D + B'C'D + ABD' + ACD'
2- Functions : W, X', Y' and Z will be implemented. Total number of product terms 13.
Outputs F1,F2,F3 and F4 produce W,X,Y and Z, respectively.

Productterm

Inputs

Outputs

ABCD

(T)(C)(C)(T)
F1F2F3F4

BC

1 11

BD

2 11

AB'C'

3 100

B'C'D'

4 000

11

AC'D'

5 100

A'BD

6 010

A'BC

7 011

AB'C

8 101

11

C'D

9 01

A'CD'

10 010

A'D'

11 00

ABD

12 "111"

ACD

13 111

Q1:
(A) Simplify the following expressions using Boolean Algebra;

V = X Y Z + X Y Z + X Y Z + X Y Z + ( X + Y + Z )
P = A B C + A B C +A B C + ( A + B ) C
R=((M(N+K))(M+(NK)))

(B) In the circuit shown,

12345-

Obtain the logic expression for the output (not simplified).

Obtain the truth table.
Convert the expression to all NAND form.
Implement the all NAND circuit.
Simplify the original output expression (as in 1).

1
3
2
1

3
2
1

3
1

2
1
3
2
1
2
13

A
C

12

Q2: (A) Show:

1- how two inputs NOR gate can be constructed from 2 inputs NAND
gates.
2- how you construct Y= ABCD using only 2 inputs NAND gates.
3- how 7486 XOR chip (contains 4 XOR) can be used to make an
XNOR gate using only 7486 chip.
(B) Design a logic circuit that will detect various inputs conditions for 4 inputs
(DCBA). The circuit will generate the following outputs:
- Output GT will be HIGH if the input value is greater than 9.
- Output LT will be LOW if the input value is less than 4.
- Output RNG will be HIGH if the input is greater than 6 and less than 11.
- Output signal TEN will be LOW if the input is equal to 10.
The design should include; Truth Table, K-Maps, and Logic equations.
Solutions
Q1 (A)

V = X Y Z + X Y Z + X Y Z + X Y Z + ( X + Y + Z )

= X Z (Y +Y ) + X Y (Z+Z) + X Y Z
= X Z + X(Y + Y Z )
= X Z + X(Y + Z)
= Z + X Y
P = A B C + A B C +A B C + ( A + B ) C
= (A+A ) BC +A B C + A B C
= B C + C B (A + A )
= B C + C B
=C
R=((M(N+K))(M+(NK)))
= (M (N + K) (M + (N k) ) )
= ((M N K ) ( M N K ))
=1
Q1 (B)
(1) Z = A C + C B + (A B C)
(2)
A
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1

C
0
1
0
1
0
1
0
1

Z
1
1
1
1
1
1
0
1

(3) Z = (( A C + C B + (A B C)) )
= ( (A C) . (C B ) . (A B C) )
(4)

C
U4B
U3B
1
2

4
5

4
5

U1A
74HC00N
74HC00N

U2B
3
4
5

74LS12N

U2A

U1D

12
13

11

2
13

74HC00N

74LS12N

U1C
9
10

74HC00N

(5) Z= A C +B C + A + B + C
= A ( C + 1) + B (C + 1) + C
= A + B + C
Q2 (A)
(1)
U5D
12
13

11

U7D

74HC00N
U6D

12
13

11

74HC00N

12
13

U8D

12
13

11

74HC00N

11

74HC00N

(2)

U13D

12

13

U9D
11

12
13
74HC00N

13

U10D
11

12
13
74HC00N

U11D
12

74HC00N

U14D

11

13

74HC00N

12

74HC00N
11

U12D
11

12
13
74HC00N

11 Y

12

(3)
U15A

A
B

1
2

U15B
4
5

7486N

7486N

1(High)

Q2 (B) Truth Table:

Dec
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

C
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

GT
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1

LT
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1

RNG
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0

TEN
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1

K-Maps
BA
00 01
DC 00
01
11
10

DC 00
01
11
10

BA
00

01

11 10
1
1

1
1

GT = DC
(LT) = D

+DB
C

11 10
1

RNG = B D C + A D C + D C B A

0
(TEN) = D C B A