NPTEL Electrical & Electronics Engineering Semiconductor Nanodevices

PRINCIPLE OF SET SET CIRCUIT DESIGN

COMPARISON BETWEEN FET AND SET

R. John Bosco Balaguru

Professor
School of Electrical &Electronics Engineering
SASTRA University
B. G. Jeyaprakash
Assistant Professor
School of Electrical & Electronics Engineering
SASTRA University
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Table of Content
1. PRINCIPLE AND CONSTRUCTION OF SINGLE ELECTRON
TRANSISTOR ...3
1.1 WHAT IS SINGLE ELECTRON TRANSISTOR? ..3
1.2 CONSTRUCTION OF THE SET .6

2. OPERATION OF SET ..9

2.1 OPERATION TEMPERATURE .11
2.2 THE DIFFERENT WAYS TO INCREASE E c INCLUDE .11

3. APPLICATIONS OF SET ..12

3.1 SET BASED FLIP-FLOP.....12
3.2 RING MEMORY ....12
3.3 SET BASED HALF ADDER ..13
3.3.1
Working 14
3.3.2
Truthtable ....15
3.4 TIMING DIAGRAM ANALYSIS ..15
3.4.1
Assumption ...15
3.4.2
State changes analysis .....15
3.5 SET BASED AND GATE ...17
3.6 TIMING DIAGRAM ANALYSIS OF SET BASED AND GATE ..19
3.6.1
Assumption ...19
3.6.2
State change analysis for AND gate .......19
3.7 COMPARISON BETWEEN SET AND FET .19
3.8 ANALYSIS .21

4. SOLVED PROBLEMS ...22

5. REFERENCES ....26

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1 Principle and construction of single electron transistor

1.1 What is Single Electron Transistor?
These are devices operating at the quantum/nanoscale that have switching
properties controlled by the removal or injection of a single electron; a device
through which only one electron can be transported at a time.
Before discussing about the principle and construction of Single Electron
Transistor
(SET),Let us see why SET is important?

In electrometry: It provides the possibility of measuring the electron addition

energies (and hence the energy level distribution) in quantum dots and other
nanoscale objects

The SETs have also been used in the first measurements of single-electron effects
in single-electron boxes and traps.

A modified version of the transistor has been used for the first proof of the
existence of fractional-charge excitations in the quantum hall effect.

Low power logic gates and their derived devices

Applications in quantum computers

Straight forward co-integration with traditional CMOS circuits

Single electron transistors (SETs) have high input impedances. Besides this, these
are also very sensitive to random background charges.

The difference between a FET/BJT and a SET is shown in the following table:
FET/BJT
SET
Based on its input current (BJT) or input The single electron transistor is a new type of
voltage (FET), a transistor allows a precise switching device that uses controlled electron
tunneling to amplify current or switch the state.
amount of current to flow through it.
The word single electron means that oneelectron-precision charge transfer through
tunneling, which is based on the Coulomb
blockade effect
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One of the most exciting challenges of microelectronics is the vision of realizing a

switching device that can be controlled by single electrons. This had been realized by
using the concept of coulomb blockade (conduction is achieved when potential is
sufficient to overcome the energy of charge correlation)and electron tunneling that used
to develop Single Electron Transistors (SET)
Let us analyze the terms Coulomb blockade and electron tunneling to
understand the working principle of SET:
SET consists of a metal island of a few hundred nanometers across, coupled to
two metal leads via tunnel barriers. At temperatures below 1 K, no current can pass
through the island with low bias voltage. This effect is known as the Coulomb blockade,
which is the result of the repulsive electronelectron interactions on the island. Coulomb
blockade is the repelling energy of previous electron present in the island to the next
electron coming towards the island. The concept of Coulomb blockade refers to the
phenomenon that tunneling through an island may be inhibited at low temperatures and
small applied voltages. The reason is that the addition of a single electron to such a
system requires an electrostatic charging energy.
In metals, the Coulomb-blockade oscillations are essentially a classical
phenomenon, since the energy spectrum of the confined region may be treated as a
continuum. This is not the case in semiconductor nanostructures which have dimensions
comparable to the Fermi wave length.
Electron Tunneling: Tunneling refers to the ability of using the quantum wave
properties of an electron to allow transmission through a thin voltage-potential barrier.
According to the laws of classical electrodynamics, no current can flow through an
insulating barrier. But quantum mechanics says that there is a finite probability for an
electron on one side of the barrier to reach the other side.
When a bias voltage is applied, there will be a current. This tunneling current will
be proportional to the bias voltage. In electrical terms, the tunnel junction behaves as a
resistor with a constant resistance. An arrangement of two conductors with an insulating
layer in between not only has a resistance, but also a finite capacitance. The insulator is
also called dielectric in this context; the tunnel junction behaves as a capacitor.
We know that for two conductors separated by an insulator, charge and voltage are
proportional.
Q =CV

(1)

where Q is the charge on the conductors, C the capacitance and V is the voltage between
the conductors.
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The electrostatic energy stored in the conductors is given by

Q2
1
E = CV 2 =
2
2C

(2)

The total energy E depends on the amount of charge on the capacitor and on the
electric potential V. The energy of the capacitor C that is charged with n electrons is
equivalent to

1 n2q2
En =
2 C

(3)

The energy difference on the capacitor C for the two charge situations of n and
n+1 electrons correspond to

E n+1 E n =

q2
(2n + 1)
2C

(4)

An electron can only pass the barrierthrough tunneling if this energy difference is less
than or equal to the energy of the electron. The energy of the electron is expressed as
E= qV

(5)

This implies that the value of Voltage V should not exceed the value

V=

q(2n + 1)
, n = 1,2,3,4,.......
2C

(6)

For the normalized voltage the location of the steps is equivalent to

VC (2n + 1)
=
q
2

(7)

1.2 Construction of the SET

The single-electron transistor describes a single electron transport through a
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quantum dot. A quantum dot is a semiconductingnanoparticle whose electrons are

confined in all three spatial dimensions
There are many variations to the structure of the single-electron transistor. The
main components of the single- electron structure are shown in Fig. 1.

Fig. 1. Single Electron Transistor

The island is the quantum dot which is connected to the drain and source
terminals. Electron exchange occurs only with the drain and source terminals, which are
connected to current and voltage meters.
The gate terminal provides electrostatic or capacitive coupling. When there is no
coupling to the source and drain, there is an integer number N of electrons in the quantum
dot (island). The total charge on the island is quantized and equal to qN. (Since tunneling
is a discrete process, the electric charge that flows through the tunnel junction flows in
multiples of the charge of electrons e)
The formulation of the Coulomb blockade model is only valid, if electron states
are localized on islands. In a classical picture it is clear, that an electron is either on an
island or not. That is the localization is implicit assumed in a classical treatment.
However a more precise quantum mechanical analyses describes the number of electrons
localized on an island N in terms of an average value,<N>which is not necessarily an
integer. The Coulomb blockade model requires.
|N-<N>|2<<1
Clearly, if the tunnel barriers are not present, or are insufficiently opaque, one can not
speak of charging an island or localizing electrons on a quantum dot, because nothing
will constrain an electron to be confined within a certain volume
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If tunneling is allowed between the island, drain, and source terminals, then the
number of electrons N adjusts itself until the energy of the total system is minimized.
The tunneling junctions (barriers) are made thick enough so that the electrons
exist in the island, source, or drain, such that the quantum fluctuation in the number N
due to tunneling through the barrier is much smaller thanone.
The electrostatically influenced electrons traveling between the source and the
drain terminals need to tunnel through two junctions (barriers). The island is charged and
discharged as the electrons cross it, and the relative energies of the island containing zero
or one extra electron depends on the gate voltage.
Thus, the charge of the island changes by a quantized amount q. The change in the
Coulomb energy associated with adding or removing an electron from the island is
usually expressed in terms of the island capacitance C.
The charging energy E c can be expressed as

Ec =

q2
C

(8)

This charging energy becomes important when it exceeds the thermal energy k B T. The
time t needed to charge or discharge the island can be expressed as
t = R t C,
whereR t is the lower-bound tunnel resistance.
From the Heisenberg uncertainty principle we have, R t > /q2. The quantity / q2 =
25.813 k is called the quantum resistance or quantum conductance (G= 38.74S).
Thus, two conditions must be met to observe the charge quantization:
Rt >>

q2

>> k B T
and
C
q2

(9)

The capacitance can be made small by reducing the quantum dot size since C =
4 s R for a sphere and C = 8 s R for a flat disc, where R is the radius and s is the
permittivity of the material.
The gate voltage V g is applied to change the island electrostatic energy in a
continuous manner. The total gate voltage-induced charge on the island is expressed as q
= C g V g . This charge is considered continuous.
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By sweeping the gate voltage, the buildup of induced charge will be compensated
in a periodic interval due to the tunneling of discrete charges. The competition between
the induced charges and the discrete compensation leads to so-called Coulomb
oscillations.
Consider that the gate voltage is fixed for the single-electron transistor while the
drain-source voltage is varied. The current-voltage results exhibit a staircase-like
behavior known as a Coulomb stair-case and is shown in Fig. 2.

7
6
5
4
3
2
1
0
e
c

2e
c

3e
c

4e
c

5e
c

6e
c

7e
c

Drain voltage

Fig. 2. Coulomb Stair-case

In this case, the charge carriers i.e. electrons enter through one junction and then
escape to second junction due to the presence of high resistance. Now, electrons moves
from one junction to another very rapidly. Thus this rapid movement of excess electrons
from one junction to another raises the total charge of the island. If the bias is increased,
it will tend to increase the population of electrons in the island. In this case the IV- Curve
represents Stair-like characteristics, which are commonly referred to as the Coulomb
Staircase.

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2 Operation of SET
Continuing with our discussion on the working of SET, this lecture shall give
further insights to its operation. The basic operation of the single-electron transistor is
shown in Fig.1, where the tunneling junctions are presented as barriers. The island is
represented as a valley or well between thetwo barriers.
A mathematical understanding shall make the behavior of SET more authentic.
The energy required to move one electron from the full top energy level to the
bottom empty level in the island can be derived as follows.
If we observe the working of SET, as described in Lecture -1, the entire discussion
was focused on moving a single electron from Source to Drain.
The Fermi energy levels of the island (dot), the drain, and the source are shown in
the Fig. 1 as E F D, E F dot, and E F S, respectively. The Fermi energy level is the potential
energypossessed by the electron, when it is in different regions
When a drain-source bias voltage is applied, these Fermi energy levels are no
longer aligned, as shown in the Fig. 1, as opposed to the case of absolute zero. At zero
temperature (zero thermal energy), the current is zero as the gap between the bottom
empty state and the top full state is aligned with E F D and E F S . This is called Coulomb
blockade.
From basics of semiconductor Physics, we know that the minimum energy
required to add an electron to the dot is E F = E N E N 1 where N is the total number of
electrons in the dot (island). For the linear response time, E F dot can be written as

N No
2 qC g
Vg
E Fdot ( N ) = E N + q 2

C
C

(10)

Where N o = Number of electrons in island V G = 0'

N = Number of electrons at dot with gate voltage V G
C = C s +C g +C d
The energy E (N) is single particle energy for the Nth electron measured from the
bottom of the conduction band. When an electron is added to the island at a constant gate
voltage, the Fermi energy becomes

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N No
2 qC g
E Fisland (N + 1) = E N +1 + q 2

Vg
C
C

(11)

By taking the difference between Eqs. (10) and (11), one can find that

E Fisland ( N + 1) E Fisland ( N ) = E F ( N + 1) E F ( N ) +

q2
q2
= E +
C
C

(12)

where E is the energy separation between the energy levels in the quantum dot.
If E is too small, then the energy gap between the filled (solid lines) and empty (dashed
lines) states is approximately q2/C.
The energy levels in the dot can be adjusted by applying a gate voltage as shown
in Fig. 3b and c such that the electron can tunnel from the source to the drain.

Fig. 3. Working of SET

Note: Can be viewed only on Acrobat 9.0 and above

2.1 Operation Temperature

The smaller the capacitance C of the quantum dots, the larger the quantum
confinement energy E p , the larger is the coulomb energy E c, thus the larger is the
Operational temperature.

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Ep =

2 2
mol 2

q2
Ec =
+ E p >> k B T
2C

(13)

(14)

Where mois the effective mass,

l is the diameter of the island or quantum dot,
q is the effective charge,
K B is the Boltzmann constant.
To allow single- electron device operation, the Coulomb energy must be the
dominating energy in the system. Depending on the error rate that can be tolerated, one
shall choose how much larger the Coulomb energy should be compared to the thermal
energy. The range in the literature goes from E c > 3KT to Ec> 100KT.
Thus, one shall have the aim of increasing the Coulomb energy for proper
operation of a single electron device

2.2 The different ways to increase E c include

As we observe from our analysis, if we decrease the capacitance, Coulomb energy
E c and the quantum confinement increases

Reducing spatial dimensions

Using different dielectric materials with a lower dielectric constant to reduce the
capacitance, or
Materials that show much higher quantum confinement energies than metals, such
as semiconductors.

3 Applications of SET
As discussed in the previous lectures, the aim is to explore the possibility of
producing circuits that combine large scale integration and low power dissipation.
Though several single-electron circuits have been proposed, the fundamental designs are
elaborated in the following sections:

3.1 SET based Flip-Flop

One design possibility is to mimic conventional memory design with SET devices,
such as a static SET memory cell or flip-flop .The operation is equivalent to a
conventional flip-flop.
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In Fig. 4. Junctions J 2 and J 3 form a SET transistor.

J 1 is the load resistance

C out the load capacitance is much bigger than the conventional capacitance C.
which means that C out /C represents one bit of information.
V IN =16mV (logic 1), and V IN =0V (logic 0)
Tunnel resistance (Rj) is 100K;

The free energy of the circuit should always be kept least possible, as otherwise, it may
result in undesirable outputs.
Vb

Vout

J1

Cout

J2

J3

Vin, set

Vout
Cout
C

Vin, reset

Fig. 4. A SET based Flip-Flop

3.2 Ring memory

A different idea which is a generalization of the bistable quantum cell for cellular
automata is shown in Fig. 5. On the circuit level it is also similar to the electron trap
memory, because it is a trap connected to a ring, a so called ring memory cell. However
the operation is different.

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Vin

0
Vout

Vout

Co

e
e

1
e

Fig. 5. SET based Ring Memory.

An even number n (in our case n=6) of tunnel junctions is connected to a ring, and
n/2 electrons are inserted into the ring. Due to their Coulomb interaction, they will repel
each other and thus can form two stable configurations.
Applying positive or negative voltage pulses atV in will switch the state of the ring
to either one of the stable configurations. The capacitors C o should be small compared to
the capacitances of the tunnel junctions, so that the electrons have a large influence on
their neighbors and keep their distance.

3.3 SET based Half Adder

The single-electron half-adder is shown in Fig.6. The following design illustrates
how SET can produce the effect of a half adder.

The circuit comprises six islands N1- N6

The islands are bounded by nine tunnel junctions J1- J9, with the capacitance of
each junction being 10-18 F.

Junctions J8 and J9 are less transparent in order to prevent electron transport

from the ground (V ss ) to islands N5 and N6 respectively, and vice versa.

The voltage V dd is constant and its value is 0.095 V.

From Fig.7
Voltage source
V1
V2
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Voltage (V)
0.0
20.1

Logic Level
Logic 1
Logic 0
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3.3.1 Working
The presence of positive charge corresponds to logic `1', whereas no charge
corresponds to logic `0'. The following table illustrates the arrangement and the
subsequent table explains the working:
Input Voltage
V1
V2

Nodes to which voltage is applied

N1,N2
N3,N4

Voltage applied through the Capacitor(s)

C1,C2
C3,C4

All four capacitors have the same capacitance, 10-18 F. The output signals of the
half-adder are taken from nodes N5, which is the Sum, and N6, which is the Carry.
+ Vdd

V1
|+

V2
|+

C1

J2

J1

N1

C2
C3

J3

N2
J4

N3

C4

N4
J6

J5

J7
N6

N5

J9

J8

Vss
Fig. 6. SET based half adder.

3.3.2 Table 1: Truth table

Input A
1
1
0
0

Input B
0
1
0
1

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Sum
1
0
0
1

Carry
0
1
0
0
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The timing diagram for the half adder operation is shown in Fig. 5.

3.4 Timing Diagram Analysis

3.4.1 Assumption
During the first time step it is assumed that one of the two input vectors [0 0] or [1
1] is applied to the circuit in order to have a logic 0at the Sum output(and hence no
positive charge is present at N5)

3.4.2 State changes - Analysis

Time
Step
2

3/4

Input Vector

Working

The input vector

changes and hence
an
electron
is
transported
from
N5 to N3(through
J5)
The free energy of
the
system
increases
[1 1] or [0 0] (The Electron
is
complement of the
transported from N3
first state)
to V dd through J1
Hence a positive
charge is present at
node5
Free
energy
decreases
[1 0] or [0 1]

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Effect on Sum

Effect on Carry

1
Since the free
energy increases

1/0
Electron
is
transported
from N2 to
V dd through
J3
(hence
logic 1 shall
be present at
the
carry
output)

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Fig. 7.Operation of the Half-adder. (a) time variation of input voltage V1, (b) time variation of input voltage V2, (c) time
variation of the charge at the sum output node N5, (d) time variation of the charge at the carry output node N6

Fig. 8.Free energy history of the circuit for the output transition from 0 to 1. (a) Sum output node N5 to V dd through N3,

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(b) Sum output node N5 to V dd through N1, (c) Carry output node N6 to V dd .

3.5 SET based AND gate

Now, let us analyze the single-electron three-input AND gate. Consider Fig. 9.
The circuit comprises of:

Four islands, N1-N4, with N4 corresponding to the output node.

The presence of a positive charge on this island (N4) corresponds to the logic `1',
whereas the absence of positive charge corresponds to the logic `0'.
The islands are bounded by five tunnel junctions J1-J5 and three capacitors C1C3.
The tunnel junctions J1-J4 are identical.
Tunnel junction J5 is less transparent, in order to prevent electron transport from
the ground (V ss ) to island N4 and vice versa.
Junction
J1-J4
J5

Resistance ()
10 5
10 7

Capacitance (F)
10-18
10-18

Table: Resistance and Capacitance of the tunnel Junctions

The voltage V dd = 0.115 V, which is a constant.

V1, V2 and V3 are the inputs to the AND gate.
It can take only two values, -0.1 V, which corresponds to the logic `1', and 0.1 V,
which corresponds to the logic `0'.

The input voltages are applied to the corresponding nodes through the capacitors C1, C2
and C3.

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+ Vdd
J1
|+

V1

N1
C1

J2

|+

V2

N2
C2

J3

|+

V3

N3
C3

J4
N4
J5

Vss

Fig. 9. SET based AND Gate

Fig. 10. The operation of three-input AND gate, (a), (b) and (c) time variation of input voltagesV1, V2, V3, respectively, (d)
Time variation of the charge at the output node N4

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3.6 Timing diagram analysis of SET based AND gate

3.6.1 Assumption
At first time step, one of the seven input vectors, apart from [1 1 1], is applied to the gate
so that no positive charge exists. Hence the output is zero.
During the input vector [1 1 1] the output changes in the following steps

3.6.2 State change analysis for AND gate

Time step

Node to which electron is

transported

Effect on free
energy

N4 to N3 through J4

Increases

N3 to N2 through J3

Decreases slightly

N2 to N1 through J2

Increases slightly

N1 to V dd through J1

Significant
increase shall be
observed

Output

3.7 Comparisonbetween SET and FET

Though, the structure of Single electron transistors [SETs] is almost same as that
of MOSFETs (in terms of source, drain and gate) but still there are some differences
between the SETs and MOSFETs. The following table illustrates the differences and
similarities between them.

SET
SETs have tunnel junction
A small conducting island [quantum dot]
the tunneling electrons are transferred oneby-one through the island from source to
drain due to the effect of Coulomb
blockade

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MOSFET
In the case of MOSFETs, it is a p-n
junction
Has a channel region
Number of electrons is transferred through
the channel at a time. Thus many electrons
simultaneously participate to the drain
current.

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Due to the Coulomb blockade effect, an

electron approaching a small negative
charged
region
experiences
the
electrostatic repulsion by the previous
electron in that region. This regulates the
number of electrons one-by-one in the
channel and hence the drain current varies
accordingly.

In case of SETs, the drain current (I d ) does

not depend on the number of electrons
transferring through the channel or on the
Fermi velocity. The I d -V g characteristic of
SET is periodic which shows a finite drain
current only for the specific gate voltages
where the energies for N and N+ 1 electron
in the channel are degenerated

In case of FETs, the drain current (Id)

depends on the number of electrons passes
through the channel. i.e. more electrons in
the channel, larger the drain current

The common phenomenon in both of these two devices is the electrostatic effect
that rules on both of them (i.e. SETs & MOSFETs). But in case of SETs, electrons are not
free to move from source to drain due to the presence of tunnel junctions. Unlike ideal
FETs, the source and drain of the SETs are separated from the channel by sufficiently
large resistances which are acting as tunnel barriers.

Note: Can be viewed only by Acrobat 9.0 and above

The comparison between FET and SET as well as their circuit designs, within the
power-delay diagram, is a very interesting issue. Although the power-delay diagram only
offers a simplified view of both concepts, the fields for the potential applications can be
derived.
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W
S0

FET

104

103

100 electrons
102

SE
T

50kT
W
S0

10

0.1
10

0.1

We observe from thisFigure that the FET behavior is recovered when the
temperature exceeds the charging energy.

3.8 Analysis
The switching energy of a FET decreases as the device dimensions decrease,
because the number of electrons in the channel as well as its capacitance scales with the
factor 2. When the scaling procedure is continued until the last electron in the channel,
the FET model turns into the SET model, since the charge of the last electron in the
channel cannot be scaled.
Therefore, the switching energy scales from this point on with -1, which actually
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means that the switching starts to increase for smaller dimensions. To operate CMOS
circuits at 300 K the SET device dimensions have to be very small, while the FET device
dimensions have to be relatively large. In between these two extremes a save operation is
only possible via cooling. This consideration is of fundamental relevance for
nanoelectronics: For relatively large device dimensions the energy stored in the capacitor
can only cope with the above-mentioned constraints if the thermal energy is reduced via
cooling. For smaller device dimensions the switching energy becomes higher than the
thermal energy and no additional cooling is necessary.

4 Solved problems
1 . For the tunnel junction with C = 1.2 aF and R t = 100 k, what is the temperature at
which coulomb blockade is expected to occur?
Answer
We know that
q2
k BT

Cs<

from which we have the temperature as

T=

q2
k B Cs

So, the temperature is 1549.372K.

2. Assume that initially there are n = 100 electrons on the quantum dot. If C a = C b = 1.2
aF. What is the on V s for the electron to tunnel?

Answer
We have
Vs >

q
1
n+
2C
2

Therefore the condition on V s is given as

V s > 6.709V
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3. For a SET with C a = C b = 10 aF and gate capacitance C g = 1.4 * 10-16 F, and gate
voltage V g as 0.1 V with initial electrons n = 175, what is the condition on V s for
tunneling to occur.

Answer
We have the condition for V s as
Vs >

1
1

C g V g q n +
(C g + Cb )
2

upon substitution of the given data we get, V s > 0.2797V

4. Atoms are arranged in a cubic lattice where the smallest distance between any two
atoms is r 0 . Assuming one free electron per atom, what is the Fermi energy? Calculate
E F in eV when r 0 = 0.5 nm.

Answer
We know that

2
h 2 3N 3
EF =

2m 8 V
where n =

N
is the number density
V

E F can be written as

2 2
3
E F = 3 n 3 therefore n can be given as
8

n=

r 03

, therefore the Fermi energy is given as

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NPTEL Electrical & Electronics Engineering Semiconductor Nanodevices

2
h2 3 3 1
EF =

2m 8 r0 2

upon substituting the given values we get the Fermi energy as

E F = 1.5eV
5. Consider a single-electron transistor with a gate capacitance that can be represented
as two parallel plates with a material having a dielectric constant of 13 and an area of 100
nm2 . Calculate the separation between the plates that can yield a capacitance of 1.0aF.

Answer

We know that
C=

A
d

where A is the area and d is the distance between the plates.

Upon mathematical manipulation we get
d=

A
C

substituting the values of and A we get

d = 1300 nm

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NPTEL Electrical & Electronics Engineering Semiconductor Nanodevices

6. For the tunnel junction C = 0.5aF and R t = 100k, what is the RC time constant.
Answer
The Time constant is given by

= Rt C
Therefore the value of the time constant is given as
= 0.005 * 10 -11 s
this denotes the switching speed of the SET.

7. Apply the concept of SET to design an Inverter.

VDD
P-type

N-type

8. Build an programmable logic gate using SETs.

VDD

OUT= A.B
For CTRL=0

CTRL
B

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NPTEL Electrical & Electronics Engineering Semiconductor Nanodevices

9. Design a Memory device using SET and explain its operation

J6

J5

J4

J3

J2

J1

Cg

QD

Vout

A.

A small number of electrons, or even just a single electron, is stored on a single

quantum dot. Their presence on the quantum dot QD corresponds to logical 1 and their
absence to 0. The line of tunnel junctions introduces an energy barrier for electrons
entering or leaving QD. Thus, stored electrons residein a local energy minimum.To write
in this cell a voltage pulse is applied at V g , which eliminates the energy barrier. V g
forces electrons to tunnel through junctions positive pulse onto island QD.

5 References
1. George W. Hanson, Fundamentals of Nanoelectronics, Pearson, 2011
2. K. Goser, P. Glosekotter, V. Dienstuhl, Nano electronics & Nano Systems,
Springer, 2004.
3. Omar. Manarseh, Semiconductors, Heterojunctions and Nanostructures,
TMH. 2005.
4. C. Wasshuber, A comparative study of single-electron memories, IEEE
Transactions on electron devices, 1998.

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