Assembly Programming
Assembly Programming
The table below gives a subset of the assembly language instructions for a computer with a single
general-purpose register, the Accumulator (ACC), and an index register (IX).
Instruction
Explanation
Opcode
(mnemonic)
Operand
LDD
<address>
0000 0100
LDV
<number>
0000 0101
STO
<address>
0001 0000
LDI
<address>
0000 0110
LDX
<address>
0000 0111
INC
<register>
0000 0011
OUTCH
1000 0001
IN
1001 0000
1100 1000
1111 1111
JMP
END
UCLES 2014
<address>
Opcode
(binary)
9691/31/O/N/14
9
The diagram shows a program loaded in main memory starting at location 100.
Locations 200 onwards contain data which are used by the program.
(a) (i)
ACC
IX
[2]
LDI
OUTCH
LDD
INC
STO
JP
END
150
203
ACC
150
100
150
200
200
201
202
203
204
205
65
76
65
77
32
32
IX
[3]
(b) The given table of instructions shows the binary number used for each instructions opcode.
All instructions in machine code are stored as a 16-bit pattern, with the opcode as the first 8
bits and the operand as the second 8 bits.
(i)
What is the maximum number of different instructions this processor could have?
.......................................................................................................................................[1]
(ii)
UCLES 2014
9691/31/O/N/14
[Turn over
10
(iii)
(iv)
What is the hexadecimal number for the instruction shown in part (b)(ii)?
...................................................
[1]
LDI 150
[2]
(vi)
LDV 15
[2]
(vii)
UCLES 2014
9691/31/O/N/14
11
(c) Use the ASCII code table to trace the first four iterations of the given program.
ASCII code table (part)
Character
Decimal
Character
Decimal
Character
Decimal
<Space>
32
73
82
65
74
83
66
75
84
67
76
85
68
77
86
69
78
87
70
79
88
71
80
89
72
81
90
ACC
Location
150
OUTPUT
100
101
102
103
104
105
106
107
LDI
OUTCH
LDD
INC
STO
JP
END
150
150
ACC
150
100
150
200
200
201
202
203
204
205
65
76
65
77
32
32
[5]
UCLES 2014
9691/31/O/N/14
[Turn over
12
5
MAR [PC]
PC [PC] + 1
MDR [[MAR]]
CIR [MDR]
UCLES 2014
9691/31/O/N/14
13
(c) The address bus and data bus are used during the fetch-execute cycle.
(i)
(ii)
[1]
(d) Consider two assembly language instructions which were given in Question 4.
Instruction
Opcode
(mnemonic)
Explanation
Operand
LDV
<number>
LDD
<address>
LDV 35
Case 1 / Case 2
Explanation .......................................................................................................................
...........................................................................................................................................
.......................................................................................................................................[2]
(ii)
LDD 35
Case 1 / Case 2
Explanation .......................................................................................................................
...........................................................................................................................................
.......................................................................................................................................[2]
UCLES 2014
9691/31/O/N/14
[Turn over
1
1
[2]
1
1
1
[3]
[1]
1
1
[2]
(iii) Fewer digits to write // less chance of an error in writing the code // easy conversion
to/from binary code
[1]
[1]
1
1
[2]
1
1
[2]
(vi) LDV 15
0
Opcode
Operand
(vii) True
OUTCH / IN // END or using a good explanation (only) of either
[2]
(c)
ACC
Location 150
65
OUTPUT
A
200
201
201
76
201
202
202
65
202
203
203
77
203
204
204
Mark as shown
5
[5]
1
1
1
1
[max 2]
The (contents of) the program counter/PC are copied to the Memory Address Register
The contents of the Program Counter are incremented
Identify the address in the Memory Address Register. Go to this address and copy its
contents to the Memory Data Register
The (contents of) the Memory Data Register are copied to the Current Instruction
Register
[4]
[1]
(ii) read/write
interrupt
reset
clock signal
bus request/bus grant
[max 1]
1
1
(ii) Case 2
The instruction is for directed addressing
The address bus is loaded with address 35
1
1
[2]
[2]
10
4
The table below gives a subset of the assembly language instructions for a computer with a single
general purpose register, the Accumulator (ACC), and an index register (IX).
Instruction
Opcode
(mnemonic)
Operand
LDD
<address>
LDV
STO
Explanation
Opcode
(binary)
0000 0100
<number>
0000 0101
<address>
0001 0000
0000 0110
0000 0111
0000 0011
1000 0001
1001 0000
1100 1000
1100 1001
1110 0111
LDI
<address>
LDX
<address>
INC
<register>
OUTCH
IN
JMP
<address>
CMP
<number>
JPE
<address>
(a) The given table of instructions shows the binary number used for each instruction's opcode.
All instructions in machine code are stored as a 16-bit pattern, with the opcode as the first
8 bits and the operand as the second 8 bits.
(i)
What is the maximum number of memory locations which can be directly addressed?
.......................................................................................................................................[1]
(ii)
UCLES 2014
9691/32/O/N/14
11
(iii)
(iv)
What is the hexadecimal number for the machine code instruction shown in part (b)(ii)?
............................................................
(v)
[1]
[2]
(vi)
UCLES 2014
9691/32/O/N/14
[Turn over
12
(b) Use the ASCII code table to trace execution of the given program.
ASCII code table (part)
Character
Decimal
Character
Decimal
Character
Decimal
<Space>
32
73
82
65
74
83
66
75
84
67
76
85
68
77
86
69
78
87
70
79
88
71
80
89
72
81
90
ACC
Location
450
OUTPUT
300
301
302
303
304
305
306
307
308
LDI
CMP
JPE
OUTCH
LDD
INC
STO
JMP
END
450
32
308
450
ACC
450
300
450
500
500
501
502
503
504
65
74
65
90
32
[5]
UCLES 2014
9691/32/O/N/14
Page 6
4
(a) (i)
(ii)
Mark Scheme
Cambridge International A Level October/November 2014
Syllabus
9691
Paper
32
256
[1]
[2]
(iii)
[1]
(iv)
05C1 hex
[1]
(v)
JPE 204
1
Op code
Operand
(vi)
1
1
[2]
True
OUTCH // IN // END // or using a good explanation (only) of either
(b)
ACC
65
Address
450
[2]
OUTPUT
A
500
501
501
74
501
502
502
65
502
503
503
90
503
504
504
32
[5]