WRC ele earl) shnical Publications Pune’Syllabus (Microprocessors & Microcontrollers) Unit I (Chapter 1) Introduction to Pentium Microprocessor Historical evolution of 80286, 386 and 486 processors, Pentium features and architecture, Pin description, Functional description, Pentium real mode, Pentium RISC features, Pentium super-scalar architecture - pipelining, Instruction paring rules, Branch prediction, Instruction and data caches The floating-point unit. Unit 11 (Chapter 2, 3) Bus Cycles and Memory Organisation Initialization and configuration, Bus operations-reset, Non pipelined and pipelined (read and write), Memory organisation and /O organisation, Data transfer mechanism-8 bit, 16 bit, 32 bit data bus interface. Pentium programming Programmer's model, Register set, Addressing modes, Instruction set, Data types, Data transfer instructions, String instructions, Arithmetic instructions, Logical instructions, Bit manipulation instructions, Program transfer instructions and Processor control instructions. Unit II (Chapter 4) Protected Mode Introduction, Segmentation-support registers, Related instructions descriptors, Memory management through segmentation, Logical to linear address translation, Protection by segmentation, Privilege level-protection, Related instructions, Inter-privilege level transfer of control, Paging-support registers, descriptors, Linear to physical address translation, TLB, Page level protection, Virtual memory, Unit 1V (Chapter 5, 6,7) Multitasking, Interrupts Exceptions and /O Multitasking - Support registers, Related descriptors, Task switching, /O Permission bit map. Virtual mode - features, Address generation, Privilege level, Instructions and registers available, entering and leaving V86 mode. Interrupt structure - Real, Protected and Virtual 8086 modes, /O handling in Pentium, Comparison of all three modes. Unit V (Chapter 8, 9) 8051 Micro-controller Micro-controller MCS-51 family architecture, On-chip data memory and program memory organization - Register set, Register bank, SFRs, External data memory and program memory, Interrupts structure, Timers and their programming, Serial port and programming, Other features, Design of minimum system using 8051 micro-controller for various applications. Unit VI (Chapter 10) PIC Micro-controller Overview and features of PIC16C, PIC 16F8XX, Pin diagram, Capture mode, Compare mode, PWM mode, Block diagram, Programmer's mode! PIC, Reset and clocking. (2)Memory organization - program memory, data memory, Flash, EEPROM, PIC 16F8XX addressing modes, Instruction set, programming, /O ports, Interrupts, Timers, ADC. Hardware Laboratory 1) File 1/O : Write Assembly Language Program (ALP) using Program Segment Prefix (PSP) to provide following file handling utility functions. a. Create file b. Read file c. Display file in dump and text mode d. Modify a file ¢. Delete a file + rename a file 2. Write an ALP to carry out complex arithmetic operations using coprocessor 3. Disk 1/0 : Write inline code (Interfacing 'C’ with assembly language) for the following a. Boot sector display for 1.44 MB Floppy disk b. Display file contents using Root directory and FAT 4, Write an Installable DOS Device Driver for a printer. Study of Windows Device Drivers 5. Study Assignments a, Study and troubleshooting of Mother board, Memory, Video, Adaptors, Keyboard, FDD, HDD, Serial Parallel ports etc. b, Study of PC diagnostic tools ¢. Study of PC Add-on card 6. PC Assembly, Setup and installation : Assembly the PC and carry out CMOS and other setting, Partition the hard disk, Install dual operating systems say Windows and Linux, Install necessary drivers for peripheral such as printer, modem, scanner, zip drive, pen drive, CDROM, LAN card, Camera ete and configure the system for Internet and Internet access 7. PC-to-PC communication using NULL MODEM connection (using 'C’ language only) 8. Write an ALP to understand working of a Mouse. The program first tries to determine if a mouse river is present. Ifso, it will show Mouse's X and Y positions that will be updated as per the mouse movement. The program will make the speaker beep whenever moitse gets near the center of the screen. The program will display a target say a{*] on the screen and will terminate whenever, the mouse button is pushed while the cursor is over *. The program will also terminate if the user enters the key 'Q’. The Program will hide or show the mouse if the user presses 'H' and 'S' keys respectively. 9. Write assembly language program to perform detection of DOS Protected Mode Interface (DPIM), Make CPU Identification, Capture Machine Status Word and Display the contents of Task Register, GDTR, IDTR and LDTR. 10. Simulation of Cache Memory algorithm using "SMP Cache". 11, Assignments based on Programming 8051 Micro-controller using 8051 hardware or kits to cover following topics a, Bit addressable area, Register Banks External data memory, External program, Memory (MOVX, MOVC etc) b. Timer programming : ISR based ¢. Serial port programming : ISR based @)12. PIC 16FXX programming (using simulator only) a. /O ports-programming b. ADC programming Note : Assembly Language Programming to be written using MASM or NASM. Table of Contents : Chapter-1___ Introduction to Pentium Microprocessor 4 - 1 to 1 - 42) Chapter-2 Bus Cycles & Memory & I/O Organisation (2-1 to 2 -18) Chapter-3 Pentium Programming (3-1 to 3-92) Chapter-4 Protected Mode (4-1 to 4-46) Chapter-5 Multitasking (6-1 to5-14) Chapter-6 Virtual Mode (6-1 to 6-6) Chapter-7 _Interrupts, Exceptions and I/O. (7-1 to 7-22) Chapter-8 The 8051 Micro-controller (8-1 to 8-44) Chapter-9 Minimum System Design using 8051 Microcontroller (9-1 to 9-62) Chapter-10 PIC Microcontroller (10 - 4 to 10 - 86) Hardware Laboratory (1 to 104) Appendix-A 8051 Instruction Set (105 to 144) Appendix-B 8051 Programming Assignments (145 to 167) Solved Papres (P-1 to P-22) Best of Technical Publications As per Revised Syllabus of Pune University - 2003 Course TE. (Computer), Semester - I Database Management Systems Data Communications Chitode, Bagad, Dhotre | Microprocessors & Microcontrollers Godse | Digital Signal Processing Chitode | Theory of Computer Science Sane | 4)Microprocessors & Microcontrollers Beas Atul P. Godse M. S. Software Systems (BITS Pilani) B.E. Industrial Electronics Formerly Lecturer in Department of Electronics Engg. Vishwakarma Institute of Technology Pune Mrs. Deepali A. Godse B.E. Industrial Electronics, M. E. (Computer) Assistant Professor in Bharati Vidyapeeth's: Women’s College of Engineering Pune Visit us at: www.vtubooks.com e [ps Technical Publications Pune”@ et Microprocessors & Microcontrollers ISBN 978 - 81 - 8431 - 297-3 All rights reserved with Technical Publications. No part of this book should be reproduced in any form, Electronic, Mechanical, Photocopy or any information storage ond retrieval system without prior permission in writing, from Technical Publications, Pune. Published by : ‘Technical Publications Pune” ‘#1, Amit Residency, 412, Shaniwar Peth, Pune - 411 030, Indie. Printers : Vikram Printers: (34, Parvati Industrial Estate Pune - 411009.Thanks to professors, students and authors of various technical books for their overwhelming response to our books. Looking at the feedback and the response we received from previous books, we are very pleased to release a text book on Microprocessors & Microcontrollers. The purpose of this book is to fulfil a need for text stating in plain, lucid. and simple everydoy language. This book provides o logical method for explaining and it prepares a background of the topic with essential illustrations. This text is provided with number of solved design examples which helps students to understand the applications of microprocessors and microcontrollers based systems. The rapid spread of microprocessor/microcontroller in society has both simplified ond complicated our lives. The aim of this text is to introduce concepts related to microprocessor and with the background of microprocessor discuss details of microcontroller family. The text basically covers details of Pentium Microprocessor & 8051 Microcontroller, its architecture, instruction set and programming, and interfacing of it with keyboard, display and other devices. It also discusses operating modes of Pentium processor, its /O organisation and memory ‘organisation. The text also introduces PIC microcontrollers.We wish to express our profound thanks to all those who helped in making this book a reality. Much needed moral support and encouragement is provided on numerous occasions by our whole fomily We are speciolly grateful to the great teacher Prof. A.V. Bakshi for his time to time, much needed, valuable guidance. Without the full support and cheerful encouragement of Mr. Uday Bakshi the book would not have been completed in time. Finally, we wish to thank Mr. Avinash Wani, Mr. Ravindra Wani and the entire team of Technical Publications who hove taken immense pain to get the quality printing in time. ‘Any suggestions for the improvement of the book will be acknowledged and appreciated. Atul Godse Deepalt GodseTable of Contents 1.1 Historical Evolution of Microprocessors ..... 1.3 Pentium Architecture and Functional Description 1.4 Pin Description... 1.5 Pentium Real Mode..... 1.5.1 Real Mode Programming Model . . 1.5.2 Memory Addressing in Real Mode 1.5.3 Handling Interrupts and Exceptions in Real Mode 1.6 Pentium RISC Features..... 1.7 Pentium Super-scalar Architecture 1.8 Pipelining .. 1.9 Instruction Pairing Rules 1.10 Branch Prediction... 1.11 The Instruction and Data Caches 1.11.4 Cache Memory . . 1.11.2 Two Level Cache System . . 11.1.3 Pentium Cache Organisalion...........00cccececeeeeeeeeeeeeeeeeeeeeeeees 1.12 Floating Point Unit. Review Questions..... -42 2.1 Introduction .. 2.2 RESET Operation .. 2.3 Bus Operations and Bus Cycles 2.4 Bus Cycle States...2.5 Non-Pipelined Bus Cycles . 2.5.1 Non-pipelined Read Cycle . one 2.5.2 Non-pipelined Write Cycle 2... .....ccececceceseveevevevevsvsseeeeeeeees 2.6 Pipelined Read/Write Cycle 2.7 Burst Cycle. 2.8 Memory Organisation. 2.9 VO Organisation... 2.9.1 0 Mapped I/O .. . 2.9.2 Memory Mapped 1/0 . 2.10 Data Transfer Mechanism - 8-bit, 16-bit, 32-bit and 64-bit .. Review Questions 3.1 Introduction .. 3.2 Programmer's Model. 3.2.1 General Purpose Registers . 3.2.2 Segment Registers . 3.2.3 Index, Pointers, and Base Registers . 3.2.4 EFLAGs Register. 3.2.4.1 Status Flags 3.2.4.2 Control Flags . 3.2.4.3 System Flags . 3.2.5 More about EFLAGs . 3.2.6 System Address Registers 3.2.7 System Registers 3.2.7.1 Control Registers . 327.2 Debugs Registers... 32.73 TestRegisters. 3.3 Pentium Addressing Modes 3.4 Pentium Data Types .. 3.5 Instruction Set Summa 3.5.2 Binary Arithmetic Instructions .3.5.3 Decimal Arithmetic Instructions 3.54 Logical Instructions... 3.555 Shift and Rotate Instructions . 3.5.6 Bit and Byte Instructions 3.5.7 Control Transfer Instructions . 3.5.8 String Instructions ........sssscsveseseseees 3.5.11 Flag Control (FLAG) Instructions 3.5.12 Segment Register Instructions ... 3.6.2 Binary Arithmetic Instructions ............ss+eeesereeeereeeeeereeeerererens 3-43 6.3 Decimal Arithmetic 7 3-50 BE IG svi sices sess ta sisesas sss asszeeseese? aaseme 3.6.5 Shift and Rotate Instructions . 3651ShfR. 2... 3.6.6 Bit and Byte Instructions ones 3.6.7 Control Transfer Instructions... ..c.c secs tcc c cette eet BOD 3.6.8 String instructions 3.6.10 ENTER and companion LEAVE instructions 3.6.11 Flag Control (EFLAG) Instructions .. .. 3.6.12 Segment Register Instructions ........:........0... esses esses eee sis Review Questions... 4.1 Introduction .... 4.2 Protected Mode-Support Register 4.3 Logical to Physical Address Translation ..4.4 Segmentation .. 4.5 Segment Descriptors and Memory Management through Segmentation. 45.1 Types of Segment Descriptors .................22-..sseseesseeeeeeee eee 4.5.1.1 Non-system Segment Descriptor... 2... ss. er 4-9 fee eat se perp aoe pocrepe ap aa EE 4-1 4.5.2 Descriptor Tables . 4.5.3 More about Sonat eet. 4.6 Paging... 4.6.1 Support Registers and Tables. 4.6.2 POE Descriptor .........0.eseeeesereerereeeerene 4.6.3 PTE Descriptor ..... . 4.7 Translation Lookaside Buffer or Page Translation Cache 4.8 Paging Operation... 4.9 Protection... 4.9.1 Protection By Segmentation 4.9.2 Privilege Level Protection 4.9.2.1 Restricting Access to Data 5 4.9.2.2 Accessing Data in Code Segments . 4.9.2.3 Restricting Control Transfers. 4.9.3 Inter-privilege Level Transfer of Control . 4.9.3.1 Conforming Code Segment . 4.9.3.2 Call Gates. 4.9.4 Changing Stacks 4.9.5 Page Level Protection "4.9.5.1 Restricting Addressable Domain... . . . . 495.2 Type Checking... 4.10 Privileged Instructions... 4.10.1 Privileged Instructions . 4.11 Special Protection Mode Instruction: 4.12 Demand Paging 4.13 Moving to Protected Mode...; 4.14 Switching Back to Real Address Mode.. ' 4.15 Virtual Memory. 4.15.1 Address Translation. 5.2 Scheduling Methods for Multi-user Operating System. 5.2.1 Time-Slice Scheduling..................5 ee 5.2.2 Pre-emplive - Priority Based Scheduling, 5.2.3 Context Switching 5.3 Support Registers and Related sett for Multitasking .... 5.3.1 Task State Segment (TSS). §.3.2 TSS Descriptor 5.3.3 Task Register (TR) 5.3.4 Task Gates and Task Gate Descriptor 5.4 Task Switchiny 5.4.1 Task Switching Without Task Gate . 5.4.2 Task Switching with Task Gate 5.4.3 Nested Tasks. . 5.5 I/O Protection... 5.5.1 1/0 Privilege Level. . 5.5.2 /O Permission Bit Map . 6.2 Entering and Leaving 8086 Virtual Mode... 6.2.1 Entering 8086 Virtual Mode. 6.2.2 Leaving 8086 Virtual Mode 6.3 Registers and Instructions ..6.3.2 Instructions .... 6.4 Address Generation in 8086 Virtual Mode 6.5 Paging in Virtual Mode.. 6.6 Protection and I/O Permission Bitmap .. 7.2 Interrupts and Exception Conditions in Pentium ... 7.3 Enabling and Disabling Interrupts 7.3.1 NMI Masks Further NMIs. 7.3.3 RF Masks Debug Faults 7.4 Priority Among Simultaneous Interrupts and Exceptions. 7.5 Handling Interrupts and Exceptions in Real Mode..... 7.6 Handling Interrupts and Exceptions in Protected Mode... 7.7 Returning from an Interrupt Procedure ..... 7.8 Interrupts and Exceptions in Virtual 8086 Mode 7-81 Protected Mode ASR a POG 7.8.2 8086 Style ISR. 7.9 /O Handling In Pentium 7.9.1 VO Port Addressing... 7.9.2. UO Port Hardware .. 7.9.3 10 Address Space 7.9.4 Memory-Mapped /O . 7.9.50 Instructions .. . 7.9.6 Protected-Mode VO 79.7 Ordering VO... .. 0. cesecececeeeeceececesseeeeseeeseeseseceeneeeeeee® Review Questions.....8.3 MCS-51 (8051) Family Architecture... 8.3.1 Pin-out of 8051 8.3.2 Central Processing Unit (CPU) ............sssssseeeeeeeeeeeeeeeeeeee seen 8.3.3 On-chip Data Memory and Register Bank. 8.3.4 On-chip Program Memory . 8.3.6.1 Register A (Accumulator). . ind a3 B362RegsIeB. ee 8.3.6.3 Program Status Word (Flag Register). . 8.3.6.4 Stack and Stack Pointer... 8.365 Data Pointer (DPTR) . . . . BSABPOPEMCOMI co5 eas cnet eens s eH w ered 8.36.7 Special Function Registers . 8.3.7 The 8051 Oscillator and Clock . . 8.4 Memory Organization in 8051... 8.5 Input/Output Pins, Ports and Circuits 8.6 External Data Memory and Program Memory ... 8.6.1 Extemal Program Memory. 8.6.2 Extemal Data Memory. . 8.6.3 Important Points to Remember in Accessing External Memory ..........-..-e200+ 8-22 8.7 Timers/Counters and their Programming 8.7.1 Timers/Counters . 8.7.2 Timer/Counter Control Logic . 8.7.3 Timer 0 and Timer 1 8.7.4 Programming... . 8.8 Serial Port and their Programming... 8.8.1 Operating Modes for Serial Port . 8.8.2 Serial Port Control Register. .8.8.3 Generating Baud Rates. meen mESLSLSCeS Pimseuns ea 8.8.4 Programming 8051 for Serial Data Transfer . 8.8.5 Programming 8051 for Receiving Serial Data 8.9 Interrupt Structure... 8.9.1 Priority Level Structure 8.9.2 External Interrupts. . . 8.9.3 Single-Step Operation 8.10 Other Features .. 8.10.1 Power Saving Options... . 8.10.2 Idle Mode 8.10.3 Power Down Mode . 8.10.4 Multiprocessor Communication in 8051 Review Questions..... 9.1 Introduction ... 9.2 Minimum System 9.2.1 Supporting Circuits 9.2.1.1 Clock Circuits sae sen eee 9.2.1.2 DemultiplexingP,, -Pog- eee sows O88 9.2.1.3 Reset Circuit 9.2.1.4 Bus Drivers. . 9.2.2 Memory Interfacing . . 9.2.3 Interfacing Example. 9.3 8051 I/O Expansion using 82565... 9.4 Interfacing Keyboard.. 9.4.1 Key Debounce using Hardware. 9.4.2 Key Debouncing using Software . 9.4.3 Simple Keyboard Interface .. 9.4.4 Matrix Keyboard Interface . . 9.5 Interfacing Display 9.5.1 LED Displays. . . 9.5.2 Inteffacing LED Displays9.6 Interfacing LCD Display .. 9.7 Interfacing DAC to 8051.. 9.7.1 IC DAC 1408 9.7.1.1 Important Electrical Characteristics for IC 1408. . 9.7.2 Interfacing DAC 1408 / DAC 0808 with 8051 9.8 Interfacing ADC to 8051...... 9.8.1 ADC 0804 Family .. 9.8.2 ADC 0808/0809 Family 9.8.3 Interfacirig of ADC 0803/0804/0805 with 8051 . 9.9 Stepper Motor Interfacing ... 9.10 Typical MCS-51 Based System . 9.11 Interfacing Examples Review Questions... 10.1 Introduction ..... 10.2 Features of PIC Microcontrollers 10.3 PICs with Key Features .... 10.4 PIC16CXx.... 10.4.1 Features of 16C6X Microcontroller . . 10.4.1.1 Core Features... 2... 10.4.1.2 Peripheral Features . . 10.4.2 Block Diagram. 10.4.3 Pin Diagram... . 10.4.4 Memory Organization . 10.4.4.4 Program Memory... 2... . .- 1044.2DataMemory. oe eee 10.5 PIC16F8XX.... 10.5.1 Features of PIC16F87X Microcontroller 10.5.1.1 Core Features . . 10.5.1.2 Peripheral Features... 2... 10.5.2 Block Diagram 10.5.3 Pin Diagram. .40.5.4 Memory Organization .... = 10.5.4.1 Program Memory Organization. 10-16, 10.5.4.2 Data Memory Organization. ©... ee eee 10-16 10.6 Reset and Clocking in PIC. 10.6.1 Reset. 106.11 Poweron Reset POR) : 10.6.1.2 Brown-out Reset (BOR) . . 10.6.1.3 Watch Dog Timer (WDT) 10.6.2 Clocking. .. 10.6.2.1 Clocking SchemelInstruction Cycle 10.6.2.2 Instruction Flow/Pipelining . . . . 10.7 Architectural Details in PIC1 ec61 and Pict 6F877 10.7.1 Harvard Architecture 10.7.2 Address and Data Bus. . 10.7.3 ALU . 10.7.4 Registers 10.7.5 PCL and PCLATH in PIC16C6X and PICIGF87X..... 2.6... 6c cece eee ee eee 10.7.6 Program Memory Paging .. . 10.8 I/O Ports in PIC16C6X and PIC16F87X 10.8.1 PORTA and TRISA Register 10.8.2 PORTB and TRISB Register 10.8.3 PORTC and TRISC Register...... 00.0... 0eceeeeeeeeeeeee nee ee renee eeeee 10.8.4 PORTD and TRISD Registers. 10.8.5 PORTE and TRISE Registers . 10.8.6 Parallel Slave Port (PSP) 10.9 Interrupts in PIC16C6X and PIC16F87xX .. 10.9.1 INT Interrupt . 10.9.2 TMRO Interrupt . 10.9.3 PorB INTCON Change 10.9.4 Context Saving During Interrupts 10.10 Timers in PIC16C6X and PIC16F87X.. 10.10.1 Timer0 Module. . 10.10.2 Timer1 Module.10.10.3 Timer2 MCdUIC. 0... eee cece cece eee e eee nee ee eee ee ee tense en een ene 10-43 10.11 Capture/Compare/PWM Modules in PIC16C6X and PIC16F87X.10 - 44 10.11.1 Capture Mode 10-46 10.11.2 Compare Mode 10-47 10.1.3 PWM Mode (PWM) . .. 10.11.31 PWM Period . . . 10.11.32 PWM Duly Cycle... . . ae 10.11.33 Setup for PWM Operation... .. . . 10.12 Data EEPROM and Flash Program Memory in PIC16F87x. 10.12.1 EECON1 and EECON2 Registers. 10.12.2 Reading the EEPROM Data Memory . 10.12.3 Writing to the EEPROM Data Memory .. 10.12.4 Reading the FLASH Program Memory 10.12.5 Writing to the FLASH Program Memory . 10.13 ADC in PIC16F87X. 10.14 Addressing Modes in PIC16C6X and PIC16F87X. 10.14.1 Direct Addressing 10.14.2 Indirect Addressing .........0secsessscsseeeseecseeseeeenesseseeeneees 10.15 Instruction Set of PIC16CXX and PIC16F8XxX. 10.15.1 Instruction Descriptions Review Questions ..image not availableimage not availableimage not availableimage not availableimage not availableMicroprocessors and Microcontrollers 1-5 Intro. to Pentium Microprocessor 9. It is available in two versions ; 80486 DX and 80486SX. The only difference between these two versions is that the 80486SX does not contain the numeric coprocessor. 10. Most of the 80486 instructions require only one clock instead of two clocks required by the 80386. 11. It supports five-stage instruction pipeline scheme that allows it to execute instructions much faster than 80386. 12. It executes conditional JUMP instructions more efficiently. When the 80486 decodes a conditional jump instruction, it autorhatically prefetches one or more instructions from the jump destination address just in case the jump is taken. Therefore, if the branch is taken, the 80486 does not have to wait through a bus cycle for the first instruction at the branch address. 13. It has built-in parity check/generator unit to implement parity detection and generation for memory reads and writes. 14, It supports burst mode memory reads and writes to implement fast cache fills. 15. It executes a few new instructions that control the internal cache memory and allow addition (ADD) and comparison (CMPXCHG) with an exchange and a byte swap (BSWAP) operation. Other than these few additional instructions, the 80486 is 100 percent compatible with the 80386 and 80387. 16. It supports built-in-self-test. It tests microprocessor, coprocessor, and cache at reset time. If the 80486 passes the test, EAX contains a zero. 17. It has additional test registers (TR3 - TR5) to test the cache memory. The Pentium, introduced in 1993, was similar to the 80386 and 80486 microprocessors. It contained larger internal cache and data bus width is extended to 64-bit. The table 1.2 shows the comparison between various pentium processors. Memory | L1 cache size | Data-Code Pentium 60 MHz 4 GByte 66 MHz 120 MHz 133 MHz 233 MHzMicroprocessors and Microcontrollers 1-6 Intro. to Pentium Microprocessor Pentium i! 350 MHz 1997 64 64 GByte | 16K- 16K | 512K 100 MHz 400 MHz 450 MHz Pentium it Xeon 6 64 GByte | 16K - 16k [512K or 1M] 100 MHz Pentium ill 1 GHz 64 64 GByte | 16K- 16K | 512k 100 MHz Slot 1 version Pentium ill 1 GHz 100 MHz Flip chip version Pentium ill 1 GHz 66 MHz Celeron Pentium IV 1.3 GHz 100 MHz 1.4 GHz 1.5 GHz 1.2 Pen Table 1.2 Comparison between pentium processors Pentium IV uses the RAMBUS memory technology in place of SDRAM technology used in other pentium processors. im Features The pentium processor family architecture contains all of the features of the 80486 microprocessor and provides significant additions and enhancements as given below : Wider Data Bus Width : The Pentium processors have a wider data bus width. The data bus width has been increased from 32-bit to 64 bit to improve the data transfer rate. Burst read and burst write back cycles are supported by the Pentium processors. In addition to 64-bit bus, bus cycle pipelining has been added to allow two bus cycles to be in progress simultaneously. Faster Floating Point Unit : The floating-point unit has been completely redesigned over the 80486 CPU. Faster algorithms provide up to ten times speed-up for common operations including add, multiply, and load. Improved Cache Structure : Pentium processors include separate code and data caches integrated on-chip to meet performance goals. Each cache is 8 Kbytes in size, with a 32-byte line size and is 2-way set associative. Each cache has a dedicated Translation Lookaside Buffer (TLB) to translate linear addresses to physical addresses. The data cache is configurable to be write back or write through on a line-by-line basis and follows the MESI protocol. The data cache tags are triple ported to support two data transfers and an inquire cycle in the same clock. The code cache is an inherently write-protected cache. The code cache tags are also triple ported to support snooping and split line accesses. Individual pagesMicroprocessors and Microcontrollers 1-7 Intro. to Pentium Microprocessor can be configured as cacheable or non-cacheable by software or hardware. The caches can be enabled or disabled by software or hardware. = Dual Integer Processor : Pentium processor has a dual integer processor. It allows execution of two instructions per clock. = Branch Prediction Logic : The Pentium uses technique called branch prediction to check whether a branch will be valid or invalid. To implement branch prediction Pentium processor has two prefetch buffers, one to prefetch code in a linear fashion, and one that prefetches code according to the Branch Target Buffer (BTB). Therefore, the needed code is almost always prefetched before it is required for execution. "= Data Integrity and Error Detection : The Pentium processors have added significant data integrity and error detection capability. Data parity checking is still supported on a byte-by-byte basis. Address parity checking, and internal parity checking features have been added along with a new exception, the machine check exception. = Functional Redundancy Checking : The Pentium processors have implemented functional redundancy checking to provide maximum error detection of the processor and the interface to the processor. When functional redundancy checking is used, a second processor, the "checker" is used to execute in lock step with the “master’ processor. The checker samples the master's outputs and compares those values with the values it computes internally, and asserts an error signal if a mismatch occurs. «= Enhancement Virtual 8086 Mode : Enhancements to the virtual 8086 mode have been made to increase performance by reducing the number of times it is necessary to trap to a virtual 8086 monitor. = Superscalar Processor : Processors capable of parallel instruction execution of multiple instructions are known as superscalar processors. The Pentium is capable, under special circumstances, of executing two integer or two floating point instructions simultaneously and thus it supports superscaler architecture. The Pentium Pro is a still faster version of the Pentium, and it contains a modified internal architecture that can schedule up to five instructions for execution, and an even faster floating point unit. It also contains a 256 K-byte or 512 K-byte level two cache in addition to the 16 K-byte (8 K for data and 8 K for instruction) level one cache. The Pentium Pro includes error correction circuitry (ECC) to correct a one bit error and indicate a two bit error. It provides four additional address lines which makes it possible to access 64 Gbytes of directly addressably memory space.-Microprocessors and Microcontrollers 18 Intro. to Pentium Microprocessor 1.3 Pentium Architecture and Functional Description Fig. 1.2 shows internal architecture of Pentium processor. As shown in the Fig. 1.2, it is. a complex processor with many interlocking parts. At the heart of the processor there are . two pipelines, the U pipeline and the V pipeline. The U-pipeline can execute all integers and floating point instructions. The V pipeline can execute simple integer instructions and the FXCH floating-point instructions. Further more, during execution, the U and V pipelines are capable of executing two integer instructions at the same time, under special conditions. Fig. 1.2 Pentium architecture block diagramMicroprocessors and Microcontrollers 4-9 Intro. to Pentium Microprocessor Bus Unit The Pentium communicates with the outside world via a 32-bit address bus and a 64-bit data bus. The bus unit is capable of performing burst reads and writes of 32 bytes to memory, and through bus cycle pipelining it allows two bus cycles to be in progress simultaneously. It consists of following functional entities : ‘Address Drivers and Receivers : During bus cycles the address drivers push the address onto the processor's local address bus (As, : A, and BE, : BE). The address bus transfers addresses back to the Pentium address receivers during cache snoop cycles. Only address lines Ay, : As are input during cache snoop cycles. Write Buffers : The Pentium processor provides two write buffers, one for each of the two internal execution pipelines. This architecture improves performance when back-to-back writes occur. Data Bus Transceivers : The transceivers send data onto the Pentium processors's local data bus during write bus cycles, and receive data into the processor during read bus cycles. Bus Control Logic : The Bus Control Logic controls whether a standard or burst bus cycle is to be run. Standard bus cycles are run to access 1/O locations and non-cacheable memory locations, as well as cacheable memory write operations. During these bus cycles the transfer size will be either 8, 16 or 32 bits as specified by the instruction. Burst cycles are run by the Pentium processor during cache line fills and during cache write-back bus cycles from the data cache. Four quad-words are transferred during each burst bus cycle. Receivers: Bus Master Control Level 2 Cache Control Internal Cache Control Parity Generation And Control Fig. 1.3 Th Bus Master Control : Bus Master control signals allow the processor to request the use of the buses from the arbiter and to be preempted by other bus masters in the system. ments comprising the Pentium processor bus unitMicroprocessors and Microcontrollers 1-10 Intro. to Pentium Microprocessor = Level Two (L2) Cache Control : The Pentium processor includes the ability to control a L2 (secondary) external cache operation. = Internal Cache Control : Internal Cache Control logic monitors input signals to determine when to snoop the address bus and output signals to notify external logic, the results of a snoop operation. It also ensures proper cache coherency. = Parity Generation and Control : It generates even data parity for each of the eight data paths during write bus cycles and checks parity on read bus cycles. It also generates a parity bit for the address during write bus cycles and checks address parity during external cache snoop operations. Code Cache An 8 KB instruction cache is used to provide quick access to frequently used instructions. It holds copies of the most frequently used instructions, and it is dedicated to supplying instructions to each of the processor's execution pipelines. The cache is organized as a two-way set associative cache with a line size of 32 bytes.. The cache directory is triple ported to allow two simultaneous accesses from the prefetcher and to support snooping. When an instruction is not found in the code (instruction ) cache, it is read from the external memory and a copy is placed into the code cache for future references. Prefetcher Prefetcher requests for Instructions from the code cache. If the requested instruction is not in the cache, a burst bus cycle is run to external memory to perform a cache line fill. Prefetch Buffers Pentium provides four prefetch buffers. They work as two independent pairs. When instructions are prefetched from the cache, they are placed into one set of prefetch buffers, while the other pair remains idle. When a branch operation is predicted in the Branch Target Buffer (BTB), it requests the predicted branch's target addresses from cache, which are placed in the second pair of buffers that was previously idle. To do this processor gets the new instruction from branch address in no time. Instruction Decode Unit Pentium provides two stage decoding. The instructions are decoded in two stages known as Decode 1 (D1) and Decode 2 (D2). During D1, the opcode is decoded in both pipelines to determine whether the two instructions can be paired according to the Pentium processor's pairing rules. If pairing is possible, the two instructions are sent simultaneously to the stage 2 decode. During D2 the address of memory resident operands are calculated.Microprocessors and Microcontrollers 1-14 Intro. to Pentium Microprocessor Control Unit It is also referred to as the Microcode Unit. This control unit consists of the following sub-units : = Microcode Sequencer = Microcode Control ROM This unit interprets the instruction word and microcode entry points fed to it by the Instruction Decode Unit. It handles exceptions, breakpoints and interrupts. In addition, it controls the integer pipelines and floating-point sequences. Arithmetic/Logic Units (ALUs) Pentium provides two ALUs to perform the arithmetic and logical operations specified by the instructions in their respective pipeline. The ALU for the "U" pipeline can complete and operation prior to the ALU in the "V" pipeline, but the opposite is not true. Address Generators Pentium provides two Address Generators (one for each pipeline). They generates the address specified by the instructions in their respective pipeline. Data Cache A separate internal Data Cache holds copies of the most frequently used data requested by the two integer pipelines and the Floating Point Unit. The internal data cache is an 8KB write-back cache, organized as two-way set associative with 32-byte lines. The Data Cache directory is triple ported to allow simultaneous access from each of the pipelines and to support snooping. Paging Unit It is enabled by setting the PG bit in CRp. It translates the linear address (from the address generator) to a physical address. It can handle two linear addresses at the same time to support both pipelines. Floating-Point Unit The floating point unit performs floating point operations. It can accept up to two floating point operations per clock when one of the instruction is an exchange instruction. 1.4 Pin Description The Fig. 1.4 shows the pin diagram of pentium processor and the Fig. 1.5 shows the pin diagram of pentium processor with functional grouping.2 1-12 Intro. to Pentium Microprocessor wie se ws 6 7 ee 10 Microprocessors and Microcontrollers woe eo ze oe ss ez eo ef eo + 3 > Fo 40 do do Fo ¥o $o Fo Lo $0 #0 $0 $o Lo $0 $0 Fo Fo Fo Fo FO}s 80 G0 Jo go Zo Go $0 Fo fo $0 #0 #0 $0 #o Jo Foo ¥0 Fo Zovola 0 G0 0 3o £0 30 GO Fo Zo EO Joo 40 20 20 L020 £0 LO £0 zOl2 $0 $0 Jo $0 30 FO GO GO 0 $0 Joho EoKo Yo ¥ofo go £0 Fo Loe 80 $0 fo go £0 £0 20 Solr 80 $0 Go go £0 £0 $0 Sole 80 $0 §o go 20 20 £0 fol £0 30 go go €0 £0 20 $0] 80 $0 go go €0 20 $0 So]? 80 20 so §o le 20 20 $0 Sol $0 $0 £0 go fee £0 £0 80 So}= 0 gO FO Fo z £0 £0 $0 So}e sO FO Fo Fo . . 40 $0 $0 So} $0 £0 0 f0 sO £0 fo $oj= $0 0 go fo Fopo Zo fo}~ 80 $0 Go go Hoo fo Sole $0 $0 go go Bofko go Z0]- $0 40 40 0 60 50 60 FORohokofoBoBowo Soo Soyo ¥o $o|- fo x0 $0.0 so 20 sofo Bow oo koto x0 Sofofoflogokoe ° 50 $0 Bo $0 F0 Zo 20 fo 20 $0 $0 Fo £0 $0 f0 $0 30 Foo Joko|~ Zo =0 $0 30 $0 $0 $0 #o 20 40 fo $0 $0 $0 Yo o So $o $oFovo}~ ze oe we FS Yo eS ee Oe oe SS Fig, 1.4 Pin diagram of Pentium processorMicro} ors and Microcontrollers jum Microprocessor Clock cLK Initialization Dual. Branch processing trace Probe mode Power ——— management _ STPCL! Address bu Breakpoint/ 7 Performance nono aan Rom © Address mask (Bus frequency) (Data bus) Address Parity Tap Data Port parity Pentium Processor {Internal Parity Error) Functional (System Error) Redundancy checking FRCMC ‘System management Bus Bus Page cacheabilty Cache Control Bus arbitration Cache ‘snooping! ‘consistency (Write ordering) EWBE (Cache fiush) FLUSH Fig. 1.5Microprocessors and Microcontrollers 1-14 Intro. to Pentium Microprocessor Pentium Hardware Signals Common Signals Changed Functionality A20M 1 Address Mask : When asserted, forces pentium to limit addressable memory to 1 MB to emulate the memory space of the 8086. This signal is active only in the real mode. As:As ° ‘These 29 address lines, together with the byte enable outputs, form the Pentium’s 32-bit address bus. With this 32-bit address a memory space of 4 gigabytes can be accessed. | es ul ° Address Strobe : When low, indicates the begining of a new bus cycle. AHOLD 1 ‘Address hold : This signal is used to place the Pentium’s address bus into a high impedance state so that an inquire cycle can be run. AP vo ‘Address parity is driven by the Pentium processor with even parity information. It is generated in the same clock that the address is driven. Even parity must be driven back to the Pentium processor during inquire cycle on this pin in the same clock. APCHK ° ‘The address parity check status pin is asserted if the Pentium oycles. processor has detected a parity error on the address bus during inquire BOFF APICEN: 1 ‘Advanced Programmable Interrupt Controller (APIC) Enable : This signal is used to enable or disable the Pentium's internal APIC interrupt Controller circuitry. BE; -BEs ° The byte enable pins are used to determine which bytes must be oi a v0 written to external memory, or which bytes were requested by the CPU BE, -BE, for the current cycle. The byte enables are driven in the same clock as the address lines (A3,-Ag). See the purpose of each byte enable Output Data Bus Enabled BE, Do-Dz BE Ds- Dis, BE: Dis Das BES Da - Ds Dn -Dwy BE Do-Dy BE. Das - Dss BE; Ds - Des ‘BFo, BR 1 _ These inputs are sampled during reset and they control the ratio of bus| frequency 10 CPU core frequency. Bhi = 1 buslcore ratio = 2/3 BR = 0 bus/core ratio = 1/2 Back off : This input causes the processor to terminate any bus cycle! ‘currently in process and tristate its buses. Execution of the interrupted bus cycle is restarted when BOFF goes high.icroprocessors and Microcontrollers 1-15 intro. to Pentium Microprocessor BP [3 : 2] PM/BP [1:0] The breakpoint pins (BPs-P9) correspond to the debug registers, DR,-ORp. These pins externally incicate a breakpoint match when the debug registers are programmed to test for breakpoint matches. BP; and BP, are multiplexed with the performance monitoring pins (PM, and PM,). The PB, and PB, bits in the Debug Mode Control Register determine if the pins are configured as breakpoint or performance monitoring pins BRDY Burst Ready : In Pentium BRDY signal is used to indicate that the external device is ready to transfer data. BREQ Bus Request : This signal when active indicates that the pentium has generated a bus request. BT; -BTp The branch trace outputs provide bits 2-0 of the branch target linear address and the default operand size on BT». These output become valid during a branch trace special message cyde. BUSCHK CACHE The bus check input allows the system to signal an unsuccessful completion of a bus cycle. If this pin is sampled active, the Pentium processor will laich the address and control signals in the machine check registers. If, in addition, the MCE bit in CR, is set, the Pentium processor will vector to the machine check exception. ° The output indicates whether the data associated with the current bus| cycle is being read from or written to the data cache. cLK 1 This is the clock signal for the Pentium. it decides the operating| frequency of the Pentium. For example, to operate the Pentium at 66 MHz, we apply a 66 MHz clock to this pin “CPU Type : Hig used spey te rocoeer pe 3 al rose system. i Data/Code : It indicates that the current bus cycle is accessing code (DIC = 0) or data (DIC = 4). (DuaviPrimary) : sue oat deans ee, Son dual-procassing system. These are the 64 data lines for the processor, Lines Dy-Dg define the least significant byte of the data bus ; lines Dgy-Dsg define the most significant byte of the data bus. vo These are the data parity pins for the processor. There is one for each| byte of the data bus. They are driven by the Pentium processor with ‘even parity information on writes in the same clock as write data. Even parity information must be driven back to the Pentium processor on these pins in the same clock as the data to ensure that the correct parity check status is indicated by the Pentium processor DP, applies to Dg3-551 DPy applies to D,-Dp. “Dual Processing Enabli “pressor onan Fp on pe pimary proceso 8 dal oceaha] “Signal is an’ output. on the dualors and Microcontrollers 1-16 Intro. to Pentium Microprocessor FLUSH 1 ° External Address Strobe : It is used to indicate that an extemal address may be read by the address bus during an inquire cycle. 1 The external write buffer empty input, when inactive (high), indicates that a write cycle Is pending in the external system, ° Floating Point Error : This output goes low when floating point unit of pentium processor generates an error. When asserted, the cache flush input forces the Pentium processor to write back all modified lines in the data cache and code cache, ‘The functional redundancy checking masterichecker mode input is used to determine whether the Pentium processor is configured in master made or checker mode. When configured as a master, the Pentium processor drives its output pins as required by the. bus protocol. When configured_as @ checker, the Pentium processor tristates all outputs (except IERR ) and sampies the output pins. ‘The configuration as a masterichecker is set after RESET and may ‘not bbe changed other than by a subsequent RESET. ‘The hit indication is driven to reflect the outcome of an inquire cycie. If an inguire cycie hits a valid line in either the Pentium processor data or instruction cache, this pin is asserted two clocks after EADS is sampled asserted. If the inquire cycle misses the Pentium processor cache, this pin is negated two clocks after EADS. — ‘The hit to a modified line output is driven to reflect the outcome of an inquire cycle. It is asserted after inquire cycles which resulted in a hit to @ modified line in the data cache. It is used to inhibit another bus ‘master from accessing the data until the line is completely written back. Hold Acknowledge : This output goes high in response to HOLD] fequest to indicate that the pentium has been placed in the hold state. When high, the pentium tri-states its bus signals and activates HLDA. Instruction branch taken indicates that the Pentium has taken an instruction branch. The internal error pin is used to indicate two types of errors, internal Parity errors and functional redundancy errors. if @ parity error occurs 90 a read from an intemal aay, the Pentium processor will assert the TERR pin for one clock and then’ shutdown. if the Pentium processor is configured as a checker and a mismatch occurs between the value sampled on the pins and the corresponding value computed internally, the Pentium processor will assert IERR two clocks after the mismatched value is returned. Ignore Numeric Exception : A low on this input allows the processor to continue executing floating-point instructions, even if an error is| generated. INIT 1 The Pentium processor initialization input pin forces the Pentium processor to begin execution in @ known state. The processor state after INIT is the same as the state after RESET except that the internal caches, write buffers.and floating point registers retain the values they had prior to INIT. If INIT is sampled high when RESET transitions from high to low, the Pentium processor wil perform built-in self test prior to the start of program execution.Microprocessors and Microcontrollers 1-17 Intro. to Pentium Microprocessor Inv 1 ‘The invalidation input determines the final cache line state (shared or invalidated) in case of an inquire cycie hit u ° This output goes high for one clock cycle each time an instruction completes in U pipeline Vv ° This output goes high for one clock cycle each time an instruction completes in V pipeline. KEN 1 Cache Enable : This signal is used to determine whether current cycle| Is cacheable or not tock ° Bus Lock : This signal goes low to indicate that the current bus cycle is locked and may not be interrupted by any other bus master. ° (Memorylinput-Output) : This signal indicates the type of current bus cycle. MiO=0 — 110 cycle MiO = 1_- memory cycle NA ' ‘An active next address input indicates that the external memory system. is ready to accept a new bus cycle although all data transfers for the current cycle have not yet completed. NMI 1 This is @ non-maskable interrupt signal of pentium. PBGNT ° Private Bus Grant : This signal is used ina dual-processing system to| z fr whi t indicate when private bus arbitration Is allowed. | PBREQ ° Private Bus Request : This signal is used to request a private bus| ‘operation in a dual-processing system. Peo ° The page cache disable pin reflects the state of the PCD bit in CR, the Page Directory Entry, or the Page Table Entry. The purpose of PCD is to provide an external cacheabilly indication on a page by page basis. PCHK Data Parity Check : This output goes low, if the Pentium detects a parity error on the data bus. But in Pentium parity checking has been extended ; if PEN is also asserted low during the same cycle, the Pentium will save a copy of the address and control signals in an internal machine check register. Additionally, if the MCE bit in the new GRé rogister is set, a machine check exception is generated PEN Parity Enable : If this input is low during the same cycle a parity error detected, the Pentium will save @ copy of address and control signals in an internal machine check register PHIT ° Private Hit : It is used to maintain the local cache coherency in @ dual processor sytem, Private Modified Hit : It is used in conjunction with PHIT to maintain the local cache coherency is a dual-processor system. (Programmable interrupt Controller Clock) : This signal controls the seria) data rate in the internal APIC interrupt controller. Programmable Interrupt Controller Data : These two signals are used to exchange data with the intemal APIC interrupt controller. The probe ready output pin indicates that the processor has stopped normal execution in response to the R/S pin going active, or probe Mode being entered. This output is used for debugging purpose.Microprocessors and Microcontrollers 1-18 Intro. to Pentium Microprocessor Pwr ° The page write through pin reflects the state of the PWT bit in CRy, the page directory entry, or the page table entry. The PWT pin is used to provide an external write back indication on a page-by-page basis. 5 ‘The runistop input is an asynchronous, edge-sensitive interrupt used to stop the normal execution of the processor and place it into an idle state. RESET 1 This signal forces pentium to initialize its registers to known state, invalidate code and data cache, and fetch ts first instruction from address FFFFFFFOH. This signal must be active for at least 1 ms after Power on. seve ° The split cycle output is asserted during misaligned LOCKed transfers to indicate that more than two cycles will be locked together. This signal is defined for locked cycles only. Smi 1 The system management interrupt causes a system management interrupt request to be latched intemally. When the latched SMI is recognized on an instruction boundary, the processor enters System Management Mode. ‘SMIACT ° An active system management interrupt active output indicates that the processor is operating in System Management Mode. ‘STeciK 1 ‘Stop Clock : When low, this signal causes the pentium to stop its intemal clock, E ————————————— TcK 1 The testability clock input provides the clocking function for the Pentium processor boundary scan in accordance with the IEEE Boundary Scan interface (Standard 1149.1). To! ' ‘The test data Input is a serial input for the test logic. TAP instuctions data are shifted into the Pentium processor on the TD pin on the fising edge of TCK when the TAP controller is in an appropriate stato. TDo ° ‘Test Data Output : Thi the falling edge of TCK. ignal ig used to send serial test information on’ ' ‘The value of the test mode select input signal sampled at the rising edge of TCK controls the sequence of TAP controller state changes. T™S TRST ' When asserted, the test reset input allows the TAP controller to be’ asynchronously initialized. wk ° Write/Read : This signal indicates whether the current bus cycle is read cycle of write cycle. WIR=0 — Read cycle WIR = 1 Write cycle we/wT 1 The write back/write through input allows @ data cache line to be defined as write back or write through on a line-by-line basis. Table 1.5 a Non-shaded signals are of Pentium processor (510\60, 567\66) and shaded signals are the additional signal provided in Pentium processor (610\75, 735\90, 815\100, 1000\120, 1110\133).Microprocessors and Microcontrollers E Intro. to Pentium Microprocessor Pin Grouping According to Function Table 1.6 organizes the pins with respect to their function. Function Pins Clock Initialization Address Bus Address Mask CLK RESET, INIT Data Bus Dgg-Dp Address Parity AP, APCHK Data Parity P;-DP9, PCHK, PEN Internal Parity Error JERR ‘System Error BUSCHK Bus Cycle Definition wid, DIG Wik CACHE, SCYC, LOCK Bus Control ‘ADS, BROY, NA Page Cacheabil PCD, PWT Cache Control KEN, weAWT. Cache Snooping/Consistency Cache Flush Write Ordering Bus Arbitration AHOLD, EADS, HITHITM, INV FLUSH EWBE BOFF, BREQ, HOLD, HLDA Interrupts” INTR, NM Floating Point Error Reporting FERR, IGNNE ‘System Management Mode ‘SMi, SMIACT Functional Redundancy Checking FROMC (IER) TAP Port TCK, TMS, TD, TDp. TRST. Breakpoinv/Performance Monitoring PMIBPo, PM/BP;, BP5-8P, Power Management STPCLK Probe Mode R/S PROY Branch Trace BTy8Tp, (BT Dual Processing CPUTYP, DIP, DPEN, PBGNT, PBREQ, PHIT, PHITM Programmable !nterrupt Control Bus Frequency PICCLK, PICDg, PICD,, APICEN BFo - BF; Table 1.6 Pin functional groupingMicroprocessors and Microcontrollers __1-20 Intro. to Pentium Microprocessor 1.5 Pentium Real Mode The Pentium microprocessor can operate basically in either Real Mode, or Protected Mode. When Pentium is reset or powered up it is initialized in Real Mode. The Pentium maintains the compatibility of the object code with 8086, 80286, 80386, and 80486 running in real mode. In this mode, the Pentium supports same architecture as the 8086, but it can access the 32-bit register set of Pentium. In real mode, it is also possible to use addressing modes with the 32-bit override instruction prefixes. In this section, we will see operation of Pentium in real mode. 1.5.1 Real Mode Programming Model The programming model makes it easier to understand the microprocessor in a programming environment. The real mode programming model gives the programming environment for Pentium in real mode. It shows only those parts of the microprocessor which the programmer can use such as various registers within the microprocessor. Fig. 1.6 shows the real mode Programming Model for Pentium microprocessor. In the diagram, only the shaded portion is a part of real mode. It consists of eight 16-bit registers (IP, CS, DS, SS, ES, FS, GS and Flag register) and eight 32-bit registers (BAX, EBX, ECX, EDX, ESP, EBP, ESI, EDI). In real mode, Pentium can access CRO, which is used to enter into the protected mode. The Protection Enable bit (PE) is used to switch the Pentium from real to protected mode. From this description it can be seen that Pentium in real mode is a 8086 with extended registers and two additional data segment registers such as FS and GS. It also implements separate memory and I/O address space. Memory space is 1,048,576 bytes (IM byte) and the I/O address space is 65,536 bytes (64 Kbytes), which is similar to 8086 memory and 1/O address space. ; 1.5.2 Memory Addressing in Real Mode ‘As mentioned earlier, in Real Mode, memory size is limited to 1 Mbyte. Due to this, only A;-Ajy address lines are active. The higher address lines Azo-Ay, are normally high. But in case of intersegment jump or call, during CS-relative memory, these address lines (Agg-A3)) are low. Eventhough 1Mbyte memory address space is available in real mode, all this memory cannot be active at one time. Actually, the 1M bytes of memory is partitioned into 64K (65536) byte segments. A segment represents an independently addressable unit of memory consisting of 64K consecutive byte-wide storage locations. Each segment has its own starting address ie the lowest-addressed byte storage location. The segment registers hold the starting addresses of the active segments in the entire memory. In Pentium, only six out of 16 (IMbyte / 64Kbyte) 64 Kbyte segments can be active at a time. (Code Segment, Stack Segment, Data Segment, ES, FS and GS). Fig 1.7 shows the active memory segments.Microprocessors and Microcontrollers 1-21 Intro. to Pentium Microprocessor 020006 EXTERNAL MEMORY [ADORESS SPACE CODE SEGMENT (cS) eek evres, DATA SEGMENT (05) ‘eR OvIES. co" 'STAGK SEGMENT ($8) ook ovres 64K NpuTIouTPUT, [ADDRESS SPACE EXTRA SEGMENT €5) ‘eek BYTES FFF DATA SEGMENT (F5) ‘aKevTES DATASEGMENT (68) ‘akovtes. FFFFF 9 Fig. 1.6 Real mode programming model for Pentium processorMicroprocessors and Microcontrollers __1-22 Intro. to Pentium Microprocessor - cs Code Segment ‘Stack Segment 15 cs Data Segment $s 0s Data Segment eS FS Gs Data Segment ‘Segment Registers Data Segment Fig. 1.7 Active segments of memory 000004 Paging mechanism in Pentium is not active in the real mode. Thus, in real mode the linear addresses are the same as physical addresses. Physical addresses are generated in Real Mode by adding the contents of the appropriate segment register which are shifted left by 4 bits to an effective address. If there is a carry generated after addition of shifted segment —_ register contents and effective address, unlike 8086, resulting 21-bit address is a linear address. This means that in 8086, the carried bit is truncated, whereas in Pentium the carried bit is stored as bit 20 of the linear address. Fig. 1.8 shows the real address mode —_—_address formation and the 21-bit address formation when carry is generated. 4 Bit shifted 16 Bit Segment Selector 19 3 0 Pan an a [oon] + 19 16 Bit Effective Address 15 0 qait fotaat ftgaa |aads 0000 21 Bit Linear Address 2119 3 0 - Fee an ee] cary bit Fig. 1.8 Real address mode addressingMicroprocessors and Microcontrollers _1-23 Intro. to Pentium Microprocessor All segments in Real mode FFFEFH are maximum 64K bytes long. These segments may be read, [a] written, or executed. The | Pentium generates general protection (interrupt 13) _—_—DATADS exception, if effective address is — [>] cove cs beyond legal range from 0 to re] FFFFH. STACK SS All segment registers are Ls] accessible to the programmers. So programmer can store F patars values in the segment registers to set them contiguous, GDATAGS. L adjacent, disjointed, or even overlapping. Fig, 1.9 shows all EXTRA ES possible ways of defining xine segments in the memory. For example, segments A and B are Fig. 1.9 Contiguous, adjacent, disjointed and contiguous, whereas segments overlapping segments B and C are overlapping. 1.5.3 Handling Interrupts and Exceptions in Real Mode The Pentium supports Real Mode interrupts and exceptions much like the 8086. In Pentium, addresses from 0 through 3FFH (400H memory locations) are dedicated for Interrupt Descriptor Table (IDT) after Reset. This table contains pointers that define the starting point of the interrupt service routines. Each pointer in the table requires four bytes of memory. Thus, it contains upto 256 (4 256 = 1024 = 400H ) interrupt pointers. Four bytes in each pointer represent two words. The word having higher memory address holds the segment base address, whereas the word having lower memory address holds offset. Fig. 1.10 shows the Interrupt Descriptor Table (IDT). Like 8086, interrupts are recognized by their numbers/types. Each time when interrupt occurs, Pentium multiplies interrupt number/type by four to generate an index into the interrupt descriptor table. In Pentium, the Interrupt Descriptor Table is relocatable. The base address of interrupt descriptor table is present in the IDTR (Interrupt Descriptor Table Register ). The Programmer can change this address by loading different address in the IDTR. This is possible using LIDT instruction. The LIDT instruction allows the relocation of base address and it also used to specify the size of the IDT. If an interrupt occurs and the corresponding entry in the interrupt table is beyond the limit stored in IDTR, a general protection fault (exception 8) will occur. Table 1.7 (see on next page) summarises Pentium Real Address Mode exceptions.Microprocessors and Microcontrollers__1-24 Intro. to Pentium Microprocessor 15 0 Segment Base | word 1 word 2 Gate for interrupt #1. Gate for interrupt # n-1 cpu — inerpt tt Increasing c memory address Gate for interrupt # 0 a OTR ~y 4 Fig. 1.10 Interrupt descriptor table Description Cause of Exception bly, IoIv Divide error 1 All Debug exceptions 3 INT Breakpoint 4 INTO Overflow 5 BOUND Bounds check 6 Any undefined opcode or LOCK used | Invalid opcode with wrong instruction 7 | esc or Warr Coprocessor not available 8 _|_ INT vector is not within IDTR mit Interrupt table limit too small ott Reserved 12 | Memory operand crosses offset 0 or | Stack fault OFFFFH 8 Memory operand *vosses offset OFFFFH | Pseudo-protection exception or attempt to execute past offset OFFFFH or instruction longer than 15 bytes 16 ESC or WAIT | Coprocessor error ome | wre | atin a Table 1.7 Pentium real-address mode exceptionsMicroprocessors and Microcontrollers __1-25 Intro. to Pentium Microprocessor Note 1: Some debug exceptions point to the faulting instruction, others to the next instruction. By examining the contents of DR6, it is possible to determine whether the debug is pointing to the faulting instruction or to the next instruction. Note 2 : The coprocessor errors are reported on the first ESC or WAIT instruction after the ESC instruction that caused the error. 1.6 Pentium RISC Features Because of the advances in microelectronic manufacturing technology, a number of changes in the computer architectures are taking place from the last decade. It became possible to cram a large logic into the small space of silicon wafer. The new computers were designed which use processors with complex instructions and addressing modes, which we call as Complex Instruction Set Computer (CISC). But the problem arised with the CISC machines was their instructions required multiple clock cycles to execute because of cramming of large logic into a single package. This degraded the performance of CISC machines. This problem is solved by a new design technique called Reduced Instruction Set Computer (RISC). The important factor considered while designing RISC machines is that it uses fewer instructions and simpler addressing modes. Because of the fewer instructions, the number of operations are reduced and can easily be implemented on silicon wafer which results in increase in the speed and hence improves the performance. In this section, we will discuss the features of RISC processor, which of them are applied: to design Pentium processor. 1, Reduced accesses to main memory Ideally, computer memory should be fast, large and inexpensive. Unfortunately, it is impossible to meet all the three of these requirements simultaneously. Increased speed and size are achieved at increased cost. Very fast memory of system can be achieved if SRAM chips are used. These chips are expensive and for the cost reason it is impracticable to build a large main memory using SRAM chips. The only alternative is to use DRAM chips for large main memiories. Processor fetches the code and data from the main memory to execute the program. The DRAMs which form the main memory are slower devices. So it is necessary to insert wait states in memory read/write cycles. This reduces the speed of execution. Thus, though the great advances are made in memory technology, processors are much faster than memories. Since the speed of operation of processor is much faster than that of memory, the processor has to wait during each memory access. The RISC design includes a technique which reduces the number of accesses to main memory. Most of the computer programs work with only small sections of code and data at a particular time. In the memory system small section of SRAM is added along with main memory, referred to as cache memory. The program which is to be executed is loaded in the main memory, but the part of program (code) and data that work at a particular time is usually accessed from the cache memory. This is accomplished by loading the active part of code and data from main memory to cache memory. Whenever