Sample Final Uccs

ECE 4242/5242 Department of Electrical and Computer Engineering
Advanced Digital Design Methodology University of Colorado at Colorado Springs

Sample Final "Engineering for the Future"
Dr. Greg Tumbush, gtumbush@uccs.edu
Sample Final 600 points
1. Minimize the following expression and then check your answer using a Karnaugh Map.
30pts.
(, , ) = + + +
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2. Using a synchronizer design a circuit in gates that will de-bounce a switch with 3ms of bounce.
When the switch is bouncing it only stays at 0 or 1 for a maximum of 500us. See the figure
below for an example of the input. Be sure to clearly denote the clock speed that the de-bounce
circuit will operate at. 30pts
3ms 3ms
async_in
500us 500us

3. Design in Verilog a module that will implement the synchronizer from problem 2. 30pts

4. Suppose the following circuit has been designed:
a
or2x1
b and2x1
or2x1 out
c
d
The delay through a gate in ns is equal to its number of inputs. The timing constraint (i.e. the
maximum delay on the longest path from input to output) on this circuit is 5.25ns.
a. Does this circuit meet the timing constraint? Explain. 25pts
b. What can be done to achieve the same functionality and meet timing? Explain and if a
new circuit is the solution, draw it. 25pts

5. Write a Verilog procedure (task or function) that will accept two 8-bit inputs, data_in,
and address, and print out the values in hex. 30pts
6. Repeat problem 5 but wait for 10 time steps in the procedure before printing out the
values. 15pts

7. Create a controller in Verilog for the Cypress SRAM we went over in class. The
controller will act as a slave and the master will be an ARM processor as in Figure 1. The
controller will support single and bursting writes and reads as well as write followed by
read or read followed by write. Your controller must be synthesizable. Assume an active
high reset is provided. 90pts
AHB-Lite Bus SRAM Bus

ARM Processor SRAM Controller Cypress SRAM
Figure 1: SRAM Control Design Environment
The AHB-Lite bus is in Table 1. Directions are from the ARM Processors perspective
Signal Width Direction Description

HCLK 1 output Clock
HADDR 21 output Address
HWRITE 1 output Write flag. 1=write, 0=read
HTRANS 2 output The transaction type. 2b00 = IDLE, 2b10 =
NONSEQ
HWDATA 8 output Data to write
HRDATA 8 input Data that was read
Table 1: The AHB-Lite Bus
Timing diagrams of a single write and single read for the AHB-Lite bus are in Figures 2 and 3
respectively.

Address Data
Address Data
phase phase phase
phase
HCLK HCLK
HADDR A HADDR A
Data
HTRANS NONSEQ valid
HTRANS NONSEQ
HWRITE HWRITE
HWDATA Data(A) HRDATA Data(A)
Figure 2: AHB-Lite Write Transaction Figure 3: AHB-Lite Read Transaction
The Cypress SRAM I/O is in Table 2. Directions are from the Cypress SRAMs perspective
Signal Width Direction Description

A 21 input Address
CE_b 1 input Chip enable, active low
WE_b 1 input Write enable, active low
OE_b 1 input Output enable, active low
DQ 8 inout Bi-directional data for read or write
Table 2: Cypress SRAM I/O
Timing diagrams of a write and read for the Cypress SRAM are in Figure 4 and Figure 5
respectively.
A Address A Address
WE_b WE_b
CE_b CE_b
OE_b OE_b
DQ Data DQ Data
Figure 4: Cypress SRAM Write Transaction Figure 5: Cypress SRAM Read Transaction




8. Answer the following questions:

a) When should the blocking assignment operator (=) should be used? 10pts
b) When should the non-blocking assignment operator (<=) be used? 10pts
c) Complete the verilog code to implement the following boolean equation. 20pts
f ab ab
always @(a or b) begin
end

d) Complete the verilog code to implement a registered version of the same boolean
equation. 20pts
always @(posedge clk or negedge reset)) begin
end
9. Without using primitives, write the verilog code, complete the timing diagram below
and draw the resulting circuit using the OSU 0.5um library for a positive edge triggered
flip-flop with active low asynchronous reset and active low synchronous set. Recall that
the reset and set inputs for the DFFSR flip-flop in the OSU 0.5um library are active low.
50pts

clk
reset
set
data_in
data_out
10. The following design will create 2 multipliers. Redesign it to use 1 multiplier. 20pts
`default_nettype none
module resource_sharing (input wire multab,
input wire [31:0] a, b, c,
output wire [??:0] out);
wire [??:0] out_multab = a*b;

wire [??:0] out_multac = a*c;
assign out = multab ? out_multab : out_multac;
endmodule

11. What is the bit-width of the output out in problem 10? Why? 10pts
12. Answer the following question about the PROM circuit in the figure below. 15pts each
Programmable
OR-Plane (2n x m)
Fusible Link
in[0]
.
in[1]
Address
.
Decoder
n to 2n
.
in[n-1]
En_bar
out[0]
out[1]
out[m-1]
Figure 6
a) Purpose of the decoder
b) Action when a row is asserted and the fuse on the BJTs emitter is intact.

c) Action when a row is asserted and the fuse on the BJTs emitter is not intact.
d) How a PROM can be used as a memory
e) How a PROM can be used to implement a combinatorial logic equation.
13. For the circuit in the figure below and the noted fault answer the following questions.
a s-a-1
b
c w1
d w2 x
e
a. Determine the test vector (i.e. the input values) to sensitize the noted fault. Why
does this test vector sensitize the noted fault? 20pts

b. Determine the test vector (i.e. the input values) to propagate the noted fault to
an output. Why does this test vector propagate the noted fault to an output?
20pts
14. Explain using words, not an equation, a flip-flops setup time constraint. 15pts
15. Explain using words, not an equation, a flip-flops hold time constraint. 15pts
16. What are the valid start points for a timing arc? 10pts
17. What are the valid stop points for a timing arc? 10pts

18. For the following circuit draw all possible timing arcs. 20pts
tclk_q tcomb tclk_q

t1_comb tcomb_2
tA
A
tA_1 D Q comb D Q t2_B
B
tB
1 2
clk
C
tcomb_C tC

Sample Final Uccs

Uploaded by

Sample Final Uccs

Uploaded by

ECE 4242/5242 Department of Electrical and Computer Engineering

Advanced Digital Design Methodology University of Colorado at Colorado Springs

Sample Final 600 points

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4. Suppose the following circuit has been designed:

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AHB-Lite Bus SRAM Bus

Figure 1: SRAM Control Design Environment

Signal Width Direction Description

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HWDATA Data(A) HRDATA Data(A)

Figure 2: AHB-Lite Write Transaction Figure 3: AHB-Lite Read Transaction

Signal Width Direction Description

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8. Answer the following questions:

b) When should the non-blocking assignment operator (<=) be used? 10pts

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always @(posedge clk or negedge reset)) begin

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wire [??:0] out_multab = a*b;

assign out = multab ? out_multab : out_multac;

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d) How a PROM can be used as a memory

e) How a PROM can be used to implement a combinatorial logic equation.

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tclk_q tcomb tclk_q

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