Pic 14000

PIC14000
28-Pin Programmable Mixed Signal Controller

High-Performance RISC CPU: Pin Diagram
Only 35 single word instructions to learn
All single cycle instructions except for program PDIP, SOIC, SSOP, Windowed CERDIP
branches which are two cycle
Operating speed: DC - 20 MHz clock input RA1/AN1 1 28 RA2/AN2
27 RA3/AN3
4096 x 14 on-chip EPROM program memory RA0/AN0 2
26
RD3/REFB 3 RD4/AN4
192 x 8 general purpose registers (SRAM) RD2/CMPB 4 25 RD5/AN5
PIC14000
6 internal and 5 external interrupt sources RD1/SDAB 5 24 RD6/AN6
RD0/SCLB 6 23 RD7/AN7
38 special function hardware registers OSC2/CLKOUT 7 22 CDAC
Eight-level hardware stack OSC1/PBTN 8 21 SUM
VDD 9 20 VSS
Analog Peripherals Features: VREG 10 19 RC0/REFA
RC7/SDAA 11 18 RC1/CMPA
Slope Analog-to-Digital (A/D) converter RC6/SCLA 12 17 RC2
- Eight external input channels including two RC5 13 16 RC3/T0CKI
MCLR/VPP 14 15 RC4
channels with selectable level shift inputs
- Six internal input channels
- 16-bit programmable timer with capture
register Digital Peripherals Features:
- 16 ms maximum conversion time at maxi-
mum (16-bit) resolution and 4 MHz clock 22 I/O pins with individual direction control
- 4-bit programmable current source High current sink/source for direct LED drive
Internal bandgap voltage reference TMR0: 8-bit timer/counter with 8-bit
Factory calibrated with calibration constants programmable prescaler
stored in EPROM 16-bit A/D timer: can be used as a general
On-chip temperature sensor purpose timer
Voltage regulator control output I2C serial port compatible with System
Two comparators with programmable references Management Bus
On-chip low voltage detector
CMOS Technology:
Special Microcontroller Features: Low-power, high-speed CMOS EPROM technology
Power-on Reset (POR), Power-up Timer (PWRT) Fully static design
and Oscillator Start-up Timer (OST) Wide-operating voltage range (2.7V to 6.0V)
Watchdog Timer (WDT) with its own on-chip RC Commercial and Industrial Temperature Range
oscillator for reliable operation Low power dissipation (typical)
Multi-segment programmable code-protection - < 3 mA @5V, 4 MHz operating mode
Selectable oscillator options - < 300 A @3V (Sleep mode: clocks stopped
- Internal 4 MHz oscillator with analog circuits active)
- External crystal oscillator - < 5 A @3V (Hibernate mode: clocks
Serial in-system programming (via two pins) stopped, analog inactive, and WDT disabled)
Applications:
Battery Chargers
Battery Capacity Monitoring
Uninterruptable Power Supply Controllers
Power Management Controllers
HVAC Controllers
Sensing and Data Acquisition
1996 Microchip Technology Inc. Preliminary DS40122B-page 1
This document was created with FrameMaker 4 0 4

PIC14000
TABLE OF CONTENTS
1.0: General Description........................................................................................................................... 3
2.0: Device Varieties ................................................................................................................................ 5
3.0: Architectural Overview ...................................................................................................................... 7
4.0: Memory Organization ...................................................................................................................... 13
5.0: I/O Ports .......................................................................................................................................... 25
6.0: Timer Modules................................................................................................................................. 37
7.0: Inter-integrated Circuit Serial Port (I2C)........................................................................................ 41
8.0: Analog Modules for A/D Conversion ............................................................................................... 57
9.0: Other Analog Modules..................................................................................................................... 65
10.0: Special Features of the CPU........................................................................................................... 75
11.0: Instruction Set Summary ................................................................................................................. 91
12.0: Development Support.................................................................................................................... 103
13.0: Electrical Characteristics for PIC14000 ..........................................................................................107
14.0: Analog Specifications: PIC14000-04 (Commercial, Industrial)...................................................... 123
Appendix A:PIC16/17 Microcontrollers ....................................................................................................133
Index .........................................................................................................................................................143
PIC14000 Product Identification System ..................................................................................................149
To Our Valued Customers

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DS40122B-page 2 Preliminary 1996 Microchip Technology Inc.

PIC14000
1.0 GENERAL DESCRIPTION The internal band-gap reference is used for calibrating
the measurements of the analog peripherals. The
The PIC14000 features include medium to high reso- calibration factors are stored in EPROM and can be
lution A/D conversion (10 to 16 bits), temperature sens- used to achieve high measurement accuracy.
ing, closed loop charge control, serial communication,
and low power operation. Power savings modes are available for portable appli-
cations. The SLEEP and HIBERNATE modes offer dif-
The PIC14000 uses a RISC Harvard architecture CPU ferent levels of power savings. The PIC14000 can
with separate 14-bit instruction and 8-bit data buses. A wake up from these modes through interrupts or reset.
two-stage instruction pipeline allows all instructions to
execute in a single cycle, except for program branches, A UV erasable CERDIP packaged version is ideal for
which require two cycles. A total of 35 instructions are code development, while the cost-effective One-Time
available. Additionally, a large register set is included. Programmable (OTP) version is suitable for production
in any volume.
PIC16/17 microcontrollers typically achieve a 2:1 code
compression and a 4:1 speed improvement over other The PIC14000 fits perfectly in applications for battery
8-bit microcontrollers. charging, capacity monitoring, and data logging. The
EPROM technology makes customization of
Features: application programs (battery characteristics, feature
The PIC14000 is a 28-pin device with these features: sets, etc.) extremely fast and convenient. The small
footprint packages make this microcontroller based
4K of EPROM
mixed signal device perfect for all applications with
192 bytes of RAM space limitations. Low-cost, low-power, high perfor-
22 I/O pins mance, ease of use and I/O flexibility make the
The analog peripherals include: PIC14000 very versatile in other applications such as
temperature monitors/controllers.
8 external analog input channels, two with level
shift inputs 1.1 Family and Upward Compatibility
6 internal analog input channels
Code written for PIC16C6X/7X can be easily ported to
2 comparators with programmable references the PIC14000 (see Appendix A).
A bandgap reference
An internal temperature sensor 1.2 Development Support
A programmable current source The PIC14000 is supported by a full-featured macro
In addition, the I2C serial port through a multiplexer assembler, a software simulator, an in-circuit emulator,
supports two separate I2C channels. a low-cost development programmer and a
full-featured programmer. A C compiler and fuzzy
A special oscillator option allows either an internal logic support tools are also available.
4 MHz oscillator or an external crystal oscillator. Using
the internal 4 MHz oscillator requires no external com-
ponents.
The PIC14000 contains three timers, the Watchdog
Timer (WDT), Timer0 (TMR0), and A/D Timer
(ADTMR). The Watchdog Timer includes its own
on-chip RC oscillator providing protection against
software lock-up. TMR0 is a general purpose 8-bit
timer/counter with an 8-bit prescaler. It may be clocked
externally using the RC3/T0CKI pin. The ADTMR is
intended for use with the slope A/D converter, but can
also be used as a general purpose timer. It has an
associated capture register which can be used to mea-
sure the time between events.
An internal low-voltage detect circuit allows for tracking
of voltage levels. Upon detecting the low voltage con-
dition, the PIC14000 can be instructed to save its oper-
ating state then enter an idle state.

PIC14000
NOTES:

PIC14000
2.0 DEVICE VARIETIES 2.3 Quick-Turnaround-Production (QTP)
Devices
A variety of frequency ranges and packaging options
are available. The PIC14000 Product Selection System Microchip offers a QTP Programming Service for
section at the end of this data sheet provides the factory production orders. This service is made
devices options to be selected for your specific applica- available for users who choose not to program a
tion and production requirements. When placing medium to high quantity of units and whose code
orders, please use the PIC14000 Product Identifica- patterns have stabilized. The devices are identical to
tion System at the back of this data sheet to specify the the OTP devices but with all EPROM locations and
correct part number. fuse options already programmed by the factory.
Certain code and prototype verification procedures do
2.1 UV Erasable Devices
apply before production shipments are available.
The UV erasable version, offered in CERDIP package, Please contact your local Microchip Technology sales
is optimal for prototype development and pilot office for more details.
programs.
2.4 Serialized Quick-Turnaround
The UV erasable version can be erased and Production (SQTPSM) Devices
reprogrammed to any of the configuration modes.
Microchip offers a unique programming service where
Note: Please note that erasing the device will
a few user-defined locations in each device are
also erase the pre-programmed calibration
programmed with different serial numbers. The serial
factors. Please refer to AN621 for more
numbers may be random, pseudo-random or
information.
sequential.
Microchip's PICSTART, PICSTART-PLUS and
Serial programming allows each device to have a
PRO MATE programmers all support programming of
unique number which can serve as an entry-code,
the PIC14000. Third party programmers also are avail-
password or ID number.
able; refer to the Microchip Third Party Guide for a list
of sources.
2.2 One-Time-Programmable (OTP)

Devices
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates or small volume applications.
The OTP devices, packaged in plastic packages permit
the user to program them once. In addition to the
program memory, the configuration bits must also be
programmed.

PIC14000
NOTES:

PIC14000
3.0 ARCHITECTURAL OVERVIEW The ALU is capable of addition, subtraction, shift, and
logical operations. Unless otherwise mentioned,
The PIC14000 addresses 4K x 14 program memory. All arithmetic operations are two's complement. In
program memory is internal. The PIC14000 can directly two-operand instructions, typically one operand is the
or indirectly address its register files or data memory. All working register (W register). The other operand is a
special function registers including the program counter file register or an immediate constant. In single
are mapped in the data memory. The PIC14000 has an operand instructions, the operand is either the
orthogonal instruction set that makes it possible to W register or a file register.
carry out any operation on any register using any
addressing mode. This symmetrical nature and lack of Depending on the instruction executed, the ALU may
special optimal situations make programming with the affect the values of the Carry (C), Digit Carry (DC), and
PIC14000 simple yet efficient. In addition, the learning Zero (Z) bits in the STATUS register. The C and DC bits
curve is reduced significantly. operate as a borrow bit and a digit borrow out bit,
respectively, in subtraction. See the SUBLW and SUBWF
The PIC14000 contains an 8-bit ALU and working instructions for examples.
register. The ALU performs arithmetic and Boolean
functions between data in the working register and any A simplified block diagram for the PIC14000 is shown
register file. in Figure 3-1, its corresponding pin description is
shown in Table 3-1.

PIC14000
FIGURE 3-1: PIC14000 BLOCK DIAGRAM
13 Data Bus 8 PORTA

EPROM Program Counter
RA0/AN0
Program RA1/AN1
Memory RA2/AN2
RAM RA3/AN3
8 Level Stack
4K x 14 File
(13-bit) Registers
192 x 8
Program 14
Bus RAM Addr (1) 9
Addr MUX
Instruction reg
Direct Addr 7 Indirect
8 Addr
FSR reg PORTC

RC0/REFA
STATUS reg RC1/CMPA
8 RC2
RC3/T0CKI
RC4
3 MUX
Power-up RC5
Timer RC6/SCLA
Oscillator RC7/SDAA
Instruction
Decode & Start-up Timer ALU
Control
Power-on
Reset 8
Timing Watchdog
Generation Timer W reg
OSC1/PBTN Low Voltage
OSC2/CLKOUT Detector PORTD
RD0/SCLB
Internal RD1/SDAB
Oscillator RD2/CMPB
RD3/REFB
RD4/AN4
MCLR/VPP VDD, VSS RD5/AN5
RD6/AN6
RD7/AN7
Programmable
Reference A & B Timer0
with Comparators
Voltage Temp Bandgap I2C

Regulator Sensor Reference Slope A/D
Support Serial Port
VREG SUM CDAC
Note 1: Higher order bits are from the STATUS register.

PIC14000
TABLE 3-1: PIN DESCRIPTIONS
Pin Pin Type

Pin Name I/O Description
No. Input Output
CDAC 22 O AN A/D ramp current source output. Normally connected to
external capacitor to generate a linear voltage ramp.
RA0/AN0 2 I/O AN/ST CMOS Analog input channel 0. This pin can also serve as a
general-purpose I/O.
RA1/AN1 1 I/O AN/ST CMOS Analog input channel 1. This pin can connect to a level
shift network. If enabled, a +0.5V offset is added to the
input voltage. This pin can also serve as a general-
purpose I/O.
RA2/AN2 28 I/O AN/ST CMOS Analog input channel 2. This pin can also serve as a
general purpose digital I/O.
RA3/AN3 27 I/O AN/ST CMOS Analog input channel 3. This pin can also serve as a gen-
eral purpose digital I/O.
SUM 21 O AN AN1 summing junction output. This pin can be connected
to an external capacitor for averaging small duration
pulses.
RC0/REFA 19 I/O-PU ST CMOS LED direct-drive output or programmable reference A out-
put. This pin can also serve as a GPIO. If enabled, this
pin has a weak internal pull-up to VDD.
RC1/CMPA 18 I/O-PU ST CMOS LED direct-drive output or comparator A output. This pin
can also serve as a GPIO. If enabled, this pin has a weak
internal pull-up to VDD.
RC2 17 I/O-PU ST CMOS LED direct-drive output. This pin can also serve as a
GPIO. If enabled, this pin has a weak internal pull-up to
VDD
RC3/T0CKI 16 I/O-PU ST CMOS LED direct-drive output. This pin can also serve as a
GPIO, or an external clock input for Timer0. If enabled,
this pin has a weak internal pull-up to VDD.
GPIO. If enabled, a change on this pin can cause a CPU
interrupt. If enabled, this pin has a weak internal pull-up
to VDD.
GPIO. If enabled, a change on this pin can cause a CPU
interrupt. If enabled, this pin has a weak internal pull-up
to VDD.
RC6/SCLA 12 I/O ST/SM NPU/OD General purpose I/O. If enabled, is multiplexed as
(No P-diode) synchronous serial clock for I2C interface. Also is the
serial programming clock. If enabled, a change on this pin
can cause a CPU interrupt. This pin has an N-channel
pull-up device which is disabled in I2C mode.
RC7/SDAA 11 I/O ST/SM NPU/OD General purpose I/O. If enabled, is multiplexed as
(No P-diode) synchronous serial data I/O for I2C interface. Also is the
serial programming data line. If enabled, a change on this
pin can cause a CPU interrupt. This pin has an N-channel
pull-up device which is disabled in I2C mode.
RD0/SCLB 6 I/O ST/SM NPU/OD General purpose I/O. If enabled, is multiplexed as
(No P-diode) synchronous serial clock for I2C interface. This pin has an
N-channel pull-up device which is disabled in I2C mode.
RD1/SDAB 5 I/O ST/SM NPU/OD General purpose I/O. If enabled, is multiplexed as
(No P-diode) synchronous serial data I/O for I2C interface. This pin has
an N-channel pull-up device which is disabled in I2C
mode.
RD2/CMPB 4 I/O-PU AN/ST CMOS General purpose I/O or comparator B output.

PIC14000
TABLE 3-1: PIN DESCRIPTIONS (CONTINUED)
Pin Pin Type

Pin Name I/O Description
No. Input Output
RD3/REFB 3 I/O-PU AN/ST CMOS General purpose I/O or programmable reference B
output.
RD4/AN4 26 I/O AN/ST CMOS Analog input channel 4. This pin can also serve as a
GPIO.
RD5/AN5 25 I/O AN/ST CMOS Analog input channel 5. This pin can connect to a level
shift network. If enabled, a +0.5V offset is added to the
input voltage. This pin can also serve as a GPIO.
GPIO.
GPIO.
VREG 10 O AN This pin is an output to control the gate of an external
N-FET for voltage regulation.
OSC1/PBTN 8 I-PU ST IN Mode: Input with weak pull-up resistor, can be used to
generate an interrupt.
HS Mode: External oscillator input.
OSC2/ 7 O CMOS IN Mode: General purpose output.
CLKOUT HS Mode: External oscillator/clock output.
MCLR/VPP 14 I/PWR ST Master clear (reset) input / programming voltage input.
This pin is an active low reset to the device.
VDD 9 PWR Positive supply connection
VSS 20 GND Return supply connection
Legend:
Type: Definition:
TTL TTL-compatible input
CMOS CMOS-compatible input or output
ST Schmitt Trigger input, with CMOS levels
SM SMBus compatible input
OD Open-drain output. An external pull-up resistor is required if this pin is used as an output.
NPU N-channel pull-up. This pin will pull-up to approximately VDD - 1.0V when outputting a logical 1.
PU Weak internal pull-up (10K-50K ohms)
No-P diode No P-diode to VDD. This pin may be pulled above the supply rail (to 6.0V maximum).
AN Analog input or output

PIC14000
3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining
The clock input (from OSC1 or the internal oscillator) is An Instruction Cycle consists of four Q cycles (Q1,
internally divided by four to generate four Q2, Q3 and Q4). The instruction fetch and execute are
non-overlapping quadrature clocks, namely Q1, Q2, pipelined such that fetch takes one instruction cycle
Q3 and Q4. The program counter (PC) is incremented while decode and execute takes another instruction
every Q1, the instruction is fetched from the program cycle. However, due to the pipelining, each instruction
memory and latched into the instruction register in Q4. effectively executes in one cycle. If an instruction
The instruction is decoded and executed during the causes the program counter to change (e.g., GOTO)
following Q1 through Q4. The clocks and instruction then two cycles are required to complete the instruction
execution flow are shown in Figure 3-2. (Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-2: CLOCK/INSTRUCTION CYCLE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2 Internal
Phase
Q3 Clock
Q4
PC PC PC+1 PC+2
CLKOUT
(IN mode)
Fetch INST (PC)
Execute INST (PC-1) Fetch INST (PC+1)
Execute INST (PC) Fetch INST (PC+2)
Execute INST (PC+1)
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
1. MOVLW 55h Fetch 1 Execute 1

2. MOVWF PORTB Fetch 2 Execute 2
3. CALL SUB_1 Fetch 3 Execute 3
4. BSF PORTA, BIT3 FetchFetch
SUB_14 Flush
Flush
Fetch SUB_1
All instructions are single cycle, except for program branches. These take two cycles
since the fetched instruction is flushed from the pipeline while the new instruction is
being fetched and then executed.

PIC14000
NOTES:

PIC14000
4.0 MEMORY ORGANIZATION 4.1.1 CALIBRATION SPACE
4.1 Program Memory Organization The calibration space is not used for instructions. This
section stores constants and factors for the arithmetic
The PIC14000 has a 13-bit program counter capable of calculations to calibrate the analog measurements.
addressing an 8K x 14 program memory space. Only
TABLE 4-1: CALIBRATION DATA
the first 4K x 14 (0000-0FFFh) are physically imple-
mented. Accessing a location above the physically OVERVIEW*
implemented address will cause a wraparound. The Address Parameter Symbol Units Format
reset vector is at 0000h and the interrupt vector is at
Slope 32-bit
0004h (Figure 4-1).
0FC0h-0FC3h reference KREF N/A floating
The 4096 words of Program Memory space are divided ratio point**
into: Bandgap 32-bit
Address Vectors (addr 0000h-0004h) 0FC4h-0FC7h reference KBG Volts floating
voltage point
Program Memory Page 0 (addr 0005h-07FFH)
Program Memory Page 1 (addr 0800h-0FBFh) Tempera- 32-bit
0FC8h-0FCBh ture sensor VTHERM Volts floating
Calibration Space (64 words, addr 0FC0h-0FFFh) voltage point
Program code may reside in Page 0 and Page 1. Tempera- Volts/ 32-bit
0FCCh-0FCFh ture sensor KTC degree floating
FIGURE 4-1: PIC14000 PROGRAM coefficient Celsius point
MEMORY MAP AND STACK
Internal
oscillator
PC<12:0> 0FD0h FOSC N/A byte
frequency
13 multiplier
CALL, RETURN,
RETFIE, RETLW WDT
0FD2h TWDT ms byte
time-out
Stack Level 1 * Refer to AN621 for details.
** Microchip modified IEEE754 32-bit floating point format.
Refer to application note AN575 for details.
Stack Level 8
Program Memory & Calibration Space
Reset Vector 0000h

Interrupt Vector
0004h
(4096 words)
On-chip Program 0005h

Memory (Page 0) 07FFh
0800h
On-chip Program
Memory (Page 1)
0FBFh
Calibration Space 0FC0h
(64 words) 0FFFh
1000h
20FFh

PIC14000
TABLE 4-2: CALIBRATION CONSTANT 4.2.1 GENERAL PURPOSE REGISTER FILE
ADDRESSES
The register file is accessed either directly, or indirectly
through the file select register FSR (Section 4.4).
Address Data
FIGURE 4-2: REGISTER FILE MAP
0FC0h KREF , exponent
File Address
0FC1h KREF , mantissa high byte 00h Indirect add.(*) Indirect addr.(*) 80h
0FC2h KREF , mantissa middle byte 01h TMR0 OPTION 81h
02h PCL PCL 82h
0FC3h KREF , mantissa low byte
03h STATUS STATUS 83h
0FC4h KBG , exponent 04h FSR FSR 84h
0FC5h KBG , mantissa high byte 05h PORTA TRISA 85h
06h RESERVED RESERVED 86h
0FC6h KBG , mantissa middle byte
07h PORTC TRISC 87h
0FC7h KBG , mantissa low byte 08h PORTD TRISD 88h
0FC8h VTHERM , exponent 09h 89h
0Ah PCLATH PCLATH 8Ah
0FC9h VTHERM , mantissa high byte
0Bh INTCON INTCON 8Bh
0FCAh VTHERM , mantissa middle byte
0Ch PIR1 PIE1 8Ch
0FCBh VTHERM , mantissa low byte 0Dh 8Dh
0Eh ADTMRL PCON 8Eh
0FCCh KTC , exponent
0Fh ADTMRH SLPCON 8Fh
0FCDh KTC , mantissa high byte
10h 90h
0FCEh KTC , mantissa middle byte 11h 91h
12h 92h
0FCFh KTC , mantissa low byte
13h 2CBUF
I I2CADD 93h
0FD0h FOSC, unsigned byte
14h I2CCON I2CSTAT 94h
0FD1h reserved
15h ADCAPL 95h
0FD2h TWDT, unsigned byte 16h ADCAPH 96h
0FD3h - 17h 97h
reserved
0FF8h 18h 98h
0FF9h-Fh calibration space checksums 19h 99h
1Ah 9Ah
4.2 Data Memory Organization 1Bh PREFA 9Bh
1Ch PREFB 9Ch
The data memory (Figure 4-2) is partitioned into two
1Dh CMCON 9Dh
banks which contain the general purpose registers and
the special function registers. Bank 0 is selected when 1Eh MISC 9Eh
the RP0 bit in the STATUS register is cleared. Bank 1 1Fh ADCON0 ADCON1 9Fh
is selected when the RP0 bit in the STATUS register is 20h A0h
set. Each bank extends up to 7Fh (128 bytes). The first
32 locations of each bank are reserved for the Special
Function Registers. Several Special Function General General
Registers are mapped in both Bank 0 and Bank 1. The Purpose Purpose
general purpose registers, implemented as static RAM, Register Register
are located from address 20h through 7Fh, and A0 (96 Bytes) (96 Bytes)
through FF. 7F FF
* Not a physical register.

Shaded areas are unimplemented memory locations,
read as 0s.

PIC14000
4.2.2 SPECIAL FUNCTION REGISTERS The special registers are classified into two sets.
Special registers associated with the core functions
The special function registers are registers used by the are described in this section. Those registers related to
CPU and peripheral functions for controlling the the operation of the peripheral features are described
desired operation of the device (Table 4-3). These reg- in the section specific to that peripheral.
isters are static RAM.
TABLE 4-3: SPECIAL FUNCTION REGISTERS FOR THE PIC14000

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bank0
INDF
Addressing this location uses contents of the FSR to address data memory (not a physical
00h* (Indirect
register).
Address)
01h TMR0 Timer0 data
02h* PCL Program Counters (PCs) least significant byte
03h* STATUS IRP RP1 RP0 TO PD Z DC C
04h* FSR Indirect data memory address pointer
05h PORTA PORTA data latch.
06h Reserved Reserved for emulation.
07h PORTC PORTC data latch
08h PORTD PORTD data latch
09h Reserved
0Ah* PCLATH Buffered register for the upper 5 bits of the Program Counter (PC)
0Bh* INTCON GIE PEIE T0IE r r T0IF r r
0Ch PIR1 CMIF PBIF 2
I CIF RCIF ADCIF OVFIF
0Dh Reserved
0Eh ADTMRL A/D capture timer data least significant byte
0Fh ADTMRH A/D capture timer data most significant byte
10h Reserved
11h Reserved
12h Reserved
13h I2CBUF I2C Serial Port Receive Buffer/Transmit Register
14h I2CCON WCOL I2COV I2CEN CKP I2CM3 I2CM2 I2CM1 I2CM0
15h ADCAPL A/D capture latch least significant byte
16h ADCAPH A/D capture latch most significant byte
17h Reserved
18h Reserved
19h Reserved
1Ah Reserved
1Bh Reserved
1Ch Reserved
1Dh Reserved
1Eh Reserved
1Fh ADCON0 ADCS3 ADCS2 ADCS1 ADCS0 AMUXOE ADRST ADZERO
Legend
= unimplemented bits, read as 0 but cannot be overwritten
r = reserved bits, default is POR value and should not be overwritten with any value
Reserved indicates reserved register and should not be overwritten with any value
* indicates registers that can be addressed from either bank

PIC14000
TABLE 4-3: SPECIAL FUNCTION REGISTERS FOR THE PIC14000 (CONTINUED)
Bank1
INDF
Addressing this location uses contents of FSR to address data memory (not a physical regis-
80h* (Indirect Ad-
ter).
dress)
81h OPTION RCPU r TOCS TOSE PSA PS2 PS1 PS0
82h* PCL Program Counters (PCs) least significant byte
83h* STATUS IRP RP1 RP0 TO PD Z DC C
84h* FSR Indirect data memory address pointer
85h TRISA PORTA Data Direction Register
86h Reserved Reserved for emulation
87h TRISC PORTC Data Direction Register
88h TRISD PORTD Data Direction Register
89h Reserved
8Ah* PCLATH Buffered register for the upper 5 bits of the Program Counter (PC)
8Bh* INTCON GIE PEIE T0IE r r T0IF r r
8Ch PIE1 CMIE PBIE I2CIE RCIE ADCIE OVFIE
8Dh Reserved
8Eh PCON r POR LVD
8Fh SLPCON HIBEN REFOFF LSOFF OSCOFF CMOFF TEMPOFF ADOFF
90h Reserved
91h Reserved
92h Reserved
93h I2CADD I2C Synchronous Serial Port Address Register
2
94h I CSTAT D/A P S R/W UA BF
95h Reserved
96h Reserved
97h Reserved
98h Reserved
99h Reserved
9Ah Reserved
9Bh PREFA PRA7 PRA6 PRA5 PRA4 PRA3 PRA2 PRA1 PRA0
9Ch PREFB PRB7 PRB6 PRB5 PRB4 PRB3 PRB2 PRB1 PRB0
9Dh CMCON CMBOUT CMBOE CPOLB CMAOUT CMAOE CPOLA
9Eh MISC SMHOG SPGNDB SPGNDA I2CSEL SMBUS INCLKEN OSC2 OSC1
9Fh ADCON1 ADDAC3 ADDAC2 ADDAC1 ADDAC0 PCFG3 PCFG2 PCFG1 PCFG0
Legend
= unimplemented bits, read as 0 but cannot be overwritten
r = reserved bits, default is POR value and should not be overwritten with any value
Reserved indicates reserved register and should not be overwritten with any value
* indicates registers that can be addressed from either bank

PIC14000
4.2.2.1 STATUS REGISTER It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
The STATUS register, shown in Figure 4-3, contains STATUS register because these instructions do not
the arithmetic status of the ALU, the RESET status and affect the Z, C or DC bits from the STATUS register. For
the bank select bits for data memory. other instructions, not affecting any status bits, see the
The STATUS register can be the destination for any Instruction Set Summary.
instruction, as with any other register. If the STATUS
Note 1: The IRP and RP1 bits (STATUS<7:6>) are
register is the destination for an instruction that affects
not used by the PIC14000 and should be
the Z, DC or C bits, then the write to these three bits is
programmed as cleared. Use of these bits
disabled. These bits are set or cleared according to the
as general purpose R/W bits is NOT
device logic. Furthermore, the TO and PD bits are not
recommended, since this may affect
writable. Therefore, the result of an instruction with the
upward compatibility with future products.
STATUS register as destination may be different than
intended. Note 2: The C and DC bits operate as a borrow
and digit borrow out bit, respectively, in
For example, CLRF STATUS will clear the upper-three
subtraction. See the SUBLW and SUBWF
bits and set the Z bit. This leaves the STATUS register
instructions for examples.
as 000u u1uu (where u = unchanged).
FIGURE 4-3: STATUS REGISTER

83h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
STATUS IRP RP1 RP0 TO PD Z DC C
Read/Write R/W R/W R/W R R R/W R/W R/W
POR value FFh 0 0 0 1 1 X X X
Bit Name Function

Not used. This bit should be programmed as 0.
B7 IRP Use of this bit as a general purpose read/write bit is not recommended, since this may
affect upward compatibility with future products.
Not used. This bit should be programmed as 0.
B6 RP1 Use of this bit as a general purpose read/write bit is not recommended, since this may
affect upward compatibility with future products.
Register page select for direct addressing.
1 = Bank1 (80h - FFh)
B5 RP0
0 = Bank0 (00h - 7Fh)
Each page is 128 bytes. Only the RP0 bit is used.
Time-out bit.
B4 TO 1 = After power-up and by the CLRWDT and SLEEP instruction.
0 = A watchdog timer time-out has occurred.
Power down bit.
B3 PD 1 = After power-up or by a CLRWDT instruction.
0 = By execution of the SLEEP instruction.
Zero bit.
B2 Z 1 = The result of an arithmetic or logic operation is zero.
0 = The result of an arithmetic or logical operation is not zero.
Digit carry / borrow bit.
For ADDWF and ADDLW instructions.
B1 DC 1 = A carry-out from the 4th low order bit of the result.
0 = No carry-out from the 4th low order bit of the result.
Note: For Borrow, the polarity is reversed.
Carry / borrow bit.
For ADDWF and ADDLW instructions.
1 = A carry-out from the most significant bit of the result occurred. Note that a
subtraction is executed by adding the twos complement of the second operand. For
B0 C
rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.
0 = No carry-out from the most significant bit of the result.
Note: For Borrow the polarity is reversed.

PIC14000
4.2.2.2 OPTION REGISTER Note: To achieve a 1:1 prescaler assignment,
The OPTION register (Address 81h) is a readable and assign the prescaler to the WDT (PSA=1)
writable register which contains various control bits to
configure the TMR0/WDT prescaler, TMR0, and the
weak pull-ups on PORTC<5:0>. Bit 6 is reserved.
FIGURE 4-4: OPTION REGISTER
R/W R/W R/W R/W R/W R/W R/W R/W

Register: OPTION W: Writable
RCPU r T0CS T0SE PSA PS2 PS1 PS0 Address: 81h R: Readable
POR value: FFh U: Unimplemented.
bit7 bit0
Read as '0'
PRESCALER VALUE
PS2:PS0 TMR0 RATE WDT RATE
PS2 PS1 PS0
0 0 0 1 : 2 1 : 1
0 0 1 1 : 4 1 : 2
0 1 0 1 : 8 1 : 4
0 1 1 1 : 16 1 : 8
1 0 0 1 : 32 1 : 16
1 0 1 1 : 64 1 : 32
1 1 0 1 : 128 1 : 64
1 1 1 1 : 256 1 : 128
PSA: Prescaler assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to TMR0
T0SE: TMR0 source edge

1 = Increment on high-to-low transition on RC3/T0CKI pin
0 = Increment on low-to-high transition on RC3/T0CKI pin
T0CS: TMR0 clock source

1 = Transition on RC3/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
Reserved. This bit should be programmed as a 1. Use of this bit as

general purpose read/write is not recommended since this may affect
upward compatibility with future products.
RCPU: PORTC pull-up enable

1 = PORTC pull-ups are disabled overriding any port latch value (RC<5:0> only)
0 = PORTC pull-ups are enabled by individual port-latch values (RC<5:0>)

PIC14000
4.2.2.3 INTCON REGISTER Note: The T0IF will be set by the specified
condition even if the corresponding Inter-
The INTCON Register is a readable and writable
rupt Enable Bit is cleared (interrupt
register which contains the various enable and flag bits
disabled) or the GIE bit is cleared (all
for the Timer0 overflow and peripheral interrupts.
interrupts disabled). Before enabling
Figure 4-5 shows the bits for the INTCON register.
interrupt, clear the interrupt flag, to ensure
that the program does not immediately
branch to the peripheral interrupt service
routine
FIGURE 4-5: INTCON REGISTER
R/W R/W R/W R/W R/W R/W R/W R/W Register: INTCON W: Writable
r Address: 0Bh or 8Bh R: Readable
GIE PEIE T0IE r T0IF r r POR value: 0000 000xb U: Unimplemented,
bit7 bit0 read as '0'
Reserved. This bit should be programmed as 0. Use of this bit

as a general purpose read/write bit is not recommended, since
this may affect upward compatibility with future products.

T0IF: TMR0 overflow interrupt flag

1 = The TMR0 has overflowed
Must be cleared by software
0 = TMR0 did not overflow
T0IE: TMR0 interrupt enable bit
1 = Enables T0IF interrupt
0 = Disables T0IF interrupt
PEIE: Peripheral interrupt enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
GIE: Global interrupt enable
1 = Enables all un-masked interrupts
0 = Disables all interrupts

PIC14000
4.2.2.4 PIE1 REGISTER
Note: INTCON<6> must be enabled to enable
This register contains the individual enable bits for the any interrupt in PIE1.
Peripheral interrupts including A/D capture event, I2C
serial port, PORTC change and A/D capture timer
overflow, and external push button.
FIGURE 4-6: PIE1 REGISTER
R/W R R R/W R/W R/W R/W R/W
2CIE Register: PIE1 W: Writable

CMIE PBIE I RCIE ADCIE OVFIE
Address: 8Ch R: Readable
bit7 bit0 POR value: 00h U: Unimplemented,
read as '0'
OVFIE: A/D Counter Overflow Interrupt Enable

1 = Enables A/D counter overflow interrupt
0 = Disables A/D counter overflow interrupt
ADCIE: A/D Capture Interrupt Enable

1 = A/D capture interrupt is enabled
0 = A/D capture interrupt is disabled
RCIE: PORTC Interrupt on change Enable

1 = Enables RCIF interrupt on pins, RC<7:4>
0 = Disables RCIF interrupt
I2CIE: I2C Port Interrupt Enable

1 = Enables I2CIF interrupt
0 = Disables I2CIF interrupt
PBIE: External Pushbutton Interrupt Enable

1 = Enable PBTN (pushbutton) interrupt on OSC1/PBTN.
(Note this interrupt not available in HS mode).
0 = Disable PBTN interrupt on OSC1/PBTN
Unimplemented. Read as 0
CMIE: Programmable Reference Comparator Interrupt Enable

1 = Enable programmable reference comparator trip
0 = Disable programmable reference comparator trip

PIC14000
4.2.2.5 PIR1 REGISTER
Note: These bits will be set by the specified
This register contains the individual flag bits for the condition, even if the corresponding
Peripheral interrupts (Figure 4-7). Interrupt Enable bit is cleared (interrupt
disabled) or the GIE bit is cleared (all
interrupts disabled). Before enabling an
interrupt, the user may wish to clear the
corresponding interrupt flag, to ensure that
the program does not immediately branch
to the Peripheral Interrupt service routine.
FIGURE 4-7: PIR1 REGISTER
R/W R R R/W R/W R/W R/W R/W

Register: PIR1 W: Writable
CMIF PBIF I2CIF RCIF ADCIF OVFIF Address: 0Ch R: Readable
POR value: 00h U: Unimplemented,
bit7 bit0
read as 0
OVFIF: A/D counter Overflow Interrupt Flag

1 = An A/D counter overflow has occurred.
Must be cleared in software.
0 = An A/D counter overflow has not occurred
ADCIF: A/D Capture Interrupt Flag

1 = An A/D capture has occurred.
0 = An A/D capture has not occurred
RCIF: PORTC Interrupt on Change Flag

1 = At least one RC<7:4> input changed.
0 =None of the RC<7:4> inputs have changed
I2CIF: I2C Port Interrupt Flag

1 = A transmission/reception is completed.
0 =Waiting to transmit/receive
PBIF: External Pushbutton Interrupt Flag

1 = The external pushbutton interrupt has occurred
on OSC1/PBTN. Note: This interrupt is not available
in HS mode.
0 =The external pushbutton interrupt did not occur
CMIF: Programmable Reference Comparator Interrupt Flag

1 = The comparator output has tripped. This is a
level-sensitive interrupt.
0 = The interrupt did not occur

PIC14000
4.2.2.6 PCON REGISTER These bits are cleared on POR. The user must set
these bits following POR. On a subsequent reset if
The Power Control (PCON) register status contains POR is cleared, this is an indication that the reset was
2 flag bits to allow differentiation between a Power-on due to a power-on reset condition.
Reset, an external MCLR reset, WDT reset, or low-volt-
age condition (Figure 4-8). Note: LVD is unknown on Power-on Reset. It
must then be set by the user and checked
on subsequent resets to see if LVD is
cleared, indicating a low voltage condition
has occurred.
FIGURE 4-8: PCON REGISTER

R/W U U U U U R/W R/W
Register: PCON W: Writable
r POR LVD
Address: 8Eh R: Readable
bit7 bit0 POR value: U: Unimplemented,
0000_000xb read as 0
LVD: Low Voltage Detect Flag

1 = A low-voltage detect condition has not occurred.
0 = A low-voltage detect condition has occurred.
Software must set this bit after a
power-on-reset condition has occurred.
POR: Power on Reset Flag

1 = A power on reset condition has not occurred.
Reset must be due to some other source
(WDT, MCLR).
0 = A power on reset condition has occurred.
Software must set this bit after a
power-on-reset condition has occurred.
Reserved. Bit 7 is reserved. This bit should be

programmed as 0 .

PIC14000
4.3 PCL and PCLATH
Note 1: There are no STATUS bits to indicate
The program counter (PC) is 13-bits wide. The low stack overflow or stack underflow
byte, PCL, is a readable and writable register. The high conditions.
byte of the PC (PCH) is not directly readable or
Note 2: There are no instruction mnemonics
writable. PCLATH is a holding register for PC<12:8>
called PUSH nor POP. These are actions
where contents are transferred to the upper byte of the
that occur from the execution of the CALL,
program counter. When PC is loaded with a new value
RETURN, RETLW, or RETFIE instructions,
during a CALL, GOTO or a write to PCL, the high bits of
or the vectoring to an interrupt address
PC are loaded from PCLATH as shown in Figure 4-9.
4.3.3 PROGRAM MEMORY PAGING
FIGURE 4-9: LOADING OF PC IN
DIFFERENT SITUATIONS The PIC14000 has 4K of program memory, but the
CALL and GOTO instructions only have a 11-bit address
PCH PCL range. This 11-bit address range allows a branch within
12 8 7 0 a 2K program memory page size. To allow CALL and
PC INST with PCL GOTO instructions to address the entire 4K program
as dest memory address range, there must be another bit to
PCLATH<4:0> 8
5 ALU result specify the program memory page. This paging bit
comes from the PCLATH<3> bit (Figure 4-9). When
doing a CALL or GOTO instruction, the user must ensure
PCLATH
that this page bit (PCLATH<3>) is programmed to the
PCH PCL
desired program memory page. If a CALL instruction (or
12 11 10 8 7 0
interrupt) is executed, the entire 13-bit PC is pushed
onto the stack. Therefore, manipulation of the
PC GOTO, CALL
PCLATH<3> is not required for the return instructions
PCLATH<4:3> 11 (which pops the PC from the stack).
2 Opcode <10:0>
Note: The PIC14000 ignores the PCLATH<4>

PCLATH bit, which is used for program memory
pages 2 and 3 (1000h-1FFFh). The use of
PCLATH<4> as a general purpose
Note: On POR, the contents of the PCLATH read/write bit is not recommended since
register are unknown. The PCLATH should this may affect upward compatibility with
be initialized before a CALL, GOTO, or any future products.
instruction that modifies the PCL register is Example 4-1 shows the calling of a subroutine in
executed. page 1 of the program memory. This example assumes
that the PCLATH is saved and restored by the interrupt
4.3.1 COMPUTED GOTO
service routine (if interrupts are used).
When doing a table read using a computed GOTO
method, care should be exercised if the table location EXAMPLE 4-1: CALL OF A SUBROUTINE IN
crosses a PCL memory boundary (each 256 byte PAGE 1 FROM PAGE 0
block). Refer to the application note Table Read Using ORG 0X500
the PIC16CXX(AN556). BSF PCLATH, 3 ; Select page 1 (800h-FFFh)
CALL SUB1_P1 ; Call subroutine in
4.3.2 STACK : ; page 1 (800h-FFFh)
:
The PIC14000 has an 8 deep x 13-bit wide hardware :
stack (Figure 4-1). The stack space is not part of either ORG 0X900
program or data space and the stack pointer is not SUB1 P1 : ; called subroutine
readable or writable. The PC is PUSHed in the stack : ; page 1 (800h-FFFh)
when a CALL instruction is executed or an interrupt is :
RETURN ; return to page 0
acknowledged. The stack is POPed in the event of a
; (000h-7FFh)
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not affected by a PUSH or a POP
operation.
The stack operates as a circular buffer. This means
that after the stack has been PUSHed eight times, the
ninth push overwrites the value that was stored from
the first push. The tenth push overwrites the second
push (and so on).

PIC14000
4.4 Indirect Addressing, INDF and FSR EXAMPLE 4-2: INDIRECT ADDRESSING
Registers movlw 0x20 ;initialize pointer
movf FSR ;to RAM
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing. NEXT clrf INDF ;clear INDF register
incf FSR ;inc pointer
Indirect addressing is possible by using the INDF
btfss FSR,4 ;all done?
register. Any instruction using the INDF register
actually accesses data pointed to by the file select goto NEXT ;no clear next
register (FSR). Reading INDF itself indirectly will ;yes continue
produce 00h. Writing to the INDF register indirectly CONTINUE:
results in a no-operation (although status bits may be
affected). An effective 9-bit address is obtained by
concatenating the 8-bit FSR register and the IRP bit
(STATUS<7>), as shown in Figure 4-10. However, IRP
is not used in the PIC14000.
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 4-2.
FIGURE 4-10: INDIRECT/INDIRECT ADDRESSING
Direct Addressing Indirect Addressing

RP1 RP0 6 from opcode 0 IRP 7 FSR 00
bank select location select bank select location select

00 01 10 11
00 00
Data
not used
Memory
7F 7F
Bank 0 Bank 1 Bank 2 Bank 3
Note: For memory map detail see Figure 4-1.

PIC14000
5.0 I/O PORTS Note: On Reset, PORTA is configured as analog
The PIC14000 has three ports, PORTA, PORTC and inputs
PORTD, described in the following paragraphs. The TRISA register controls the direction of the PORTA
Generally, PORTA is used as the analog input port. pins, even when they are being used as analog inputs.
PORTC is used for general purpose I/O and for host The user must make sure to keep the pins configured
communication. PORTD provides additional I/O lines. as inputs when using them as analog inputs. A 1 in
Four lines of PORTD may function as analog inputs. each location configures the corresponding port pin as
an input. This register resets to all 1s, meaning all
5.1 PORTA and TRISA PORTA pins are initially inputs. The data register
should be initialized prior to configuring the port as out-
PORTA is a 4-bit wide port with data register located at
puts. See Figure 5-2 and Figure 5-3.
location 05h and corresponding data direction register
(TRISA) at 85h. PORTA can operate as either PORTA inputs go through a Schmitt Trigger AND gate
analog inputs for the internal A/D converter or as that is disabled when the input is in analog mode. Refer
general purpose digital I/O ports. These inputs are to Figure 5-1.
Schmitt Triggers when used as digital inputs, and have Note that bits RA<7:4> are unimplemented and always
CMOS drivers as outputs. read as 0. Unused inputs should not be left floating to
PORTA pins are multiplexed with analog inputs. avoid leakage currents. All pins have input protection
ADCON1<1:0> bits control whether these pins are diodes to VDD and VSS.
analog or digital as shown in Section 8.7. When config-
ured to the digital mode, reading the PORTA register EXAMPLE 5-1: INITIALIZING PORTA
reads the status of the pins whereas writing to it will CLRF PORTA ;Initialize PORTA by setting
write to the port latch. When selected as an analog ;output data latches
input, these pins will read as 0s. BSF STATUS, RP0 ;Select Bank1
MOVLW 0x0F ;Value used to initialize
;data direction
MOVWF TRISA ;Set RA<3:0> as inputs
FIGURE 5-1: PORTA BLOCK DIAGRAM

VDD
Data
Bus D Q
P I/O
Write CK Q Pin
PORTA
D Q N
Write VSS
TRISA CK Q Analog Input Mode
Read
TRISA
Schmitt Trigger
Input Buffer
Q D
EN
Read
PORTA
To A/D Converter
Note: I/O pins have protection diodes to VDD and VSS.

PIC14000
FIGURE 5-2: PORTA DATA REGISTER
PORTA RA3/AN3 RA2/AN2 RA1/AN1 RA0/AN0
Read/Write U U U U R/W R/W R/W R/W
POR value 0xh 0 0 0 0 X X X X
Bit Name Function
B7-B4 Unimplemented. Reads as0.
B3 RA3/AN3 GPIO or analog input. Returns value on pin RA3/AN3 when used as a digital
input. When configured as an analog input, reads as 0.
B1 RA1/AN1 GPIO or analog input. Returns value on RA1/AN1 when used as a digital input.
This pin can connect to a level shift network. If enabled, a +0.5V offset is added
to the input voltage. When configured as an analog input, reads as 0.
5.2 PORTC and TRISC When using PORTC<0> as an analog output

(CMCON<1> bit is set), the TRISC<0> bit should be
PORTC is a 8-bit wide bidirectional port, with Schmitt cleared to disable the weak pull-up on this pin. Refer to
Trigger inputs, that serves the following functions Table 5-1.
depending on programming:
Four of the PORTC pins, RC<7:4> have an interrupt on
Direct LED drive (PORTC<7:0>). change feature. Only pins configured as inputs can
I2C communication lines (PORTC<7:6>), refer to cause this interrupt to occur. In other words, any pin
Section 7.0 I2C Serial Port. RC<7:4> configured as an output is excluded from the
Interrupt on change function (PORTC<7:4>), interrupt on change comparison. The input pins of
discussed below and in Section 10.3 Interrupts. RC<7:4> are compared with the old value latched on
Programmable reference and comparator the last read of PORTC. The mismatch outputs of
outputs. RC<7:4> are ORed together to assert the RCIF flag
(PIR1 register<2>) and cause a CPU interrupt, if
Timer0 clock source on RC3
enabled.
The PORTC data register is located at location 07h and
its data direction register (TRISC) is at 87h. Note: If the I2C function is enabled,
(I2CCON<5>, address 14h), RC<7:6> are
PORTC<5:0> have weak internal pull-ups (~100 uA automatically excluded from the
typical). A single control bit can turn on all the pull-ups. interrupt-on-change comparison.
This is done by clearing bit RCPU (OPTION<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on power-on reset and in hibernate mode.

PIC14000
This interrupt can wake the device up from SLEEP. The The TRISC register controls the direction of the
user, in the interrupt service routine, can clear the PORTC pin. A 1 in each location configures the
interrupt in one of two ways: corresponding port pin as an input. Upon reset, this
Disable the interrupt by clearing the RCIE register sets to FFh, meaning all PORTC pins are ini-
(PIE1<2>) bit tially inputs. The data register should be initialized prior
to configuring the port as outputs.
Read PORTC. This will end mismatch condition.
Then, clear the RCIF (PIR1<2>) bit. Unused inputs should not be left floating to avoid
leakage currents. All pins have input protection diodes
A mismatch condition will continue to set the RCIF bit.
to VDD and VSS.
Reading PORTC will end the mismatch condition, and
allow the RCIF bit to be cleared.
EXAMPLE 5-2: INITIALIZING PORTC
If bit CMAOE (CMCON<1>) is set, the RC0/REFA pin CLRF PORTC ; Initialize PORTC data
becomes the programmable reference A and analog ; latches before setting
output. Pin RC1/CMPA becomes the comparator A out- ; the data direction
put. ; register
Note: Setting CMAOE changes the definition of BSF STATUS, RPO ; Select Bank1
RC0/REFA and RC1/CMPA, bypassing MOVLW 0xCF ; Value used to initialize
the PORTC data and TRISC register set- ; data direction
tings. MOVWF TRISC ; Set RC<3:0> as inputs
; RC<5:4> as outputs
PORTC<7:6> also serves multiple functions. These ; RC<7:6> as inputs
pins act as the I2C data and clock lines when the I2C
module is enabled. They also serve as the serial pro-
gramming interface data and clock line for in-circuit
programming of the EPROM.
FIGURE 5-3: BLOCK DIAGRAM OF PORTC<7:6> PINS
I2CCON<5> VDD
Data
Bus D Q N
I/O
Write Pin
CK Q
PORTC
N
D Q
VSS
Write CK Q
TRISC
Schmitt Trigger
Read Input Buffer
TRISC
Q D
Read
PORTC EN
Set Q D
RCIF From other
PORTC pins Read PORTC
EN
Note: I/O pins have protection diodes to VDD and VSS. These pins do not have a P-channel pull-up.

PIC14000
TABLE 5-1: PORT RC0 PIN CONFIGURATION SUMMARY
RC0 Pin RCPU CMAOE
TRISC<0> Comment
Configuration OPTION<7> CMCON<1>
Digital Input (weak pull-up) 1 0 0
Digital Input (no pull-up) 1 1 0
Digital Output 0 X 0
Analog Output 0 X 1 Must clear TRISC<0> to disable pull-up when
used as an analog output.

RCPU
HIBERNATE VDD
Data
Bus D Q
P
I/O
Write CK Q Pin
PORTC
D Q
Write Schmitt Trigger

CK Q Input Buffer
TRISC
Read
TRISC
Q D
Read
PORTC EN
Set Q D
RCIF From other
PORTC pins Read PORTC
EN
1. I/O pins have protection diodes to VDD and VSS.

2. Port Latch = 1 and TRISC = 1 enables weak pull-up if RCPU = 0 in OPTION register.

PIC14000
RCPU
VDD
Data
Bus D Q
P
I/O
Write CK Q Pin
PORTC
D Q
Write CK Q HIBERNATE
TRISC Schmitt Trigger
Read Input Buffer
TRISC
Q D
Read
PORTC EN
Read PORTC

2. Port Latch =1 and TRISC =1 enables weak pull-up if RCPU =0 in OPTION register.
3. If the CMAOE bit (CMCON<1>) is set to1, RC0 becomes REFA, RC1 becomes CMPA,
ignoring the PORTC<1:0> data and TRISC<1:0> register settings.

PIC14000
FIGURE 5-6: PORTC DATA REGISTER
PORTC RC7/SDAA RC6/SCLA RC5 RC4 RC3/T0CKI RC2 RC1/CMPA RC0/REFA
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
POR value xxh x x x x x x x x
Bit Name Function
Synchronous serial data I/O for I2C interface. Also is the serial programming data line.
This pin can also serve as a general purpose I/O. If enabled, a change on this pin can
B7 RC7/SDAA
cause a CPU interrupt. This pin has an N-channel pull-up to VDD which is disabled in
I2C mode.
Synchronous serial clock for I2C interface. Also is the serial programming clock. This pin
B6 RC6/SCLA can also serve as a general purpose I/O. If enabled, a change on this pin can cause a
CPU interrupt. This pin has an N-channel pull-up to VDD which is disabled in I2C mode.
B5 RC5 LED direct-drive output. This pin can also serve as a GPIO. If enabled, a change on this
pin can cause a CPU interrupt. If enabled, this pin has a weak internal pull-up to VDD.
B4 RC4 LED direct-drive output. This pin can also serve as a GPIO. If enabled, a change on this
pin can cause a CPU interrupt. If enabled, this pin has a weak internal pull-up to VDD.
B3 RC3/T0CKI LED direct-drive output. This pin can also serve as a GPIO. If enabled, this pin has a
weak internal pull-up to VDD. T0CKI is enabled as TMR0 clock via the OPTION register.
B2 RC2 LED direct-drive output. This pin can also serve as a GPIO. If enabled, this pin has a
weak internal pull-up to VDD.
B1 RC1/CMPA LED direct-drive output. This pin can also serve as a GPIO, or comparator A output. If
enabled, this pin has a weak internal pull-up to VDD.
B0 RC0/REFA LED direct-drive output. This pin can also serve as a GPIO, or programmable reference
A output. If enabled, this pin has a weak internal pull-up to VDD.
U= unimplemented, X = unknown.

PIC14000
5.2.1 TRISC PORTC DATA DIRECTION
REGISTER
This register defines each pin of PORTC as either an

input or output under software control. A 1 in each
location configures the corresponding port pin as an
input. This register resets to all 1s, meaning all
PORTC pins are initially inputs. The data register
should be initialized prior to configuring the port as
outputs.
FIGURE 5-7: TRISC REGISTER

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
POR value FFh 1 1 1 1 1 1 1 1
Bit Name Function

B7 TRISC7 Control direction on pin RC7/SDAA (has no effect if I2C is enabled):
0 = pin is an output
1 = pin is an input
B6 TRISC6 Control direction on pin RC6/SCLA (has no effect if I2C is enabled):
1 = pin is an input
B5 TRISC5 Control direction on pin RC5:
1 = pin is an input
1 = pin is an input
1 = pin is an input
1 = pin is an input
B1 TRISC1 Control direction on pin RC1/CMPA (has no effect if the CMAOE bit is set):
1 = pin is an input
B0 TRISC0 Control direction on pin RC0/REFA (has no effect if the CMAOE bit is set):
1 = pin is an input
U= unimplemented, X = unknown.

PIC14000
5.3 PORTD and TRISD
PORTD is an 8-bit port that may be used for general
purpose I/O. Four pins can be configured as analog
inputs.
FIGURE 5-8: BLOCK DIAGRAM OF PORTD<7:4> PINS

VDD
Data
Bus D Q
Write P I/O
PORTD CK Q Pin
D Q N
Write VSS
TRISD CK Q
Analog Input Mode
Read
TRISD
Schmitt Trigger
Input Buffer
Q D
EN
Read
PortD
To A/D Converter
Note: I/O pins have protection diodes to VDD and VSS.
Data
Bus D Q
Write I/O
CK Q Pin
PORTD
D Q
Write Schmitt Trigger
TRISD CK Q Input Buffer
Read
TRISD
Q D
Read
PORTD EN
Read PORTD
2. If CMBOE (CMCON<5>) is set to 1, RD2 becomes CMPB,
RD3 becomes REFB, ignoring the PORTD<3:2> data and
TRISD<3:2> register settings.

PIC14000
I2CCON<5> VDD
Data
Bus D Q
Write N I/O
CK Q Pin
PORTD
D Q N
Write VSS
TRISD CK Q
Read
TRISD
Schmitt Trigger
Input Buffer
Q D
EN
Read
PortD
Note: I/O pins have protection diodes to VDD and VSS. These pins do not have a P-channel pull-up.
FIGURE 5-11: PORTD DATA REGISTER

PORTD RD7/AN7 RD6/AN6 RD5/AN5 RD4/AN4 RD3/REFB RD2/CMPB RD1/SDAB RD0/SCLB
POR value xxh X X X X X X X X
Bit Name Function
GPIO or analog input. Returns value on pin RD7/AN7 when used as a digital
B7 RD7/AN7
RD6/AN6 GPIO or analog input. Returns value on pin RD6/AN6 when used as a digital
B6
GPIO or analog input. This pin can connect to a level shift network. If
B5 RD5/AN5 enabled, a +0.5V offset is added to the input voltage. When configured as
an analog input, reads as 0.
RD4/AN4 GPIO or analog input. Returns value on pin RD4/AN4 when used as a digital
B4
B3 RD3/REFB This pin can serve as a GPIO, or programmable reference B output.
B2 RD2/CMPB This pin can serve as a GPIO, or comparator B output.
Alternate synchronous serial data I/O for I2C interface enabled by setting
the I2CSEL bit in the MISC register. This pin can also serve as a general
B1 RD1/SDAB
purpose I/O. This pin has an N-channel pull-up to VDD which is disabled in
I2C mode.
Alternate synchronous serial clock for I2C interface, enabled by setting the
I2CSEL bit in the MISC register. This pin can also serve as a general pur-
B0 RD0/SCLB
pose I/O. This pin has an N-Channel pull-up to VDD which is disabled in I2C
mode.
Legend: U = unimplemented, read as 0, x = unknown.

PIC14000
FIGURE 5-12: TRISD REGISTER
TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0
POR value FFh 1 1 1 1 1 1 1 1
Bit Name Function

Control direction on pin RD7/AN7:
B7 TRISD7 0 = pin is an output
1 = pin is an input
1 = pin is an input
1 = pin is an input
1 = pin is an input
Control direction on pin RD3/REFB (has no effect if the CMBOE bit is set):
1 = pin is an input
Control direction on pin RD2/CMPB (has no effect if the CMBOE bit is set):
1 = pin is an input
Control direction on pin RD1/SDAB:
1 = pin is an input
Control direction on pin RD0/SCLB:
1 = pin is an input

PIC14000
If the CMBOE bit (CMCON<5>) is set, the RD3/REFB 5.4 I/O Programming Considerations
pin becomes the programmable reference B output
and pin RD2/CMPB becomes the comparator B output. 5.4.1 BI-DIRECTIONAL I/O PORTS
Reading the port register reads the values of the port

Note: Setting CMBOE changes the definition of pins. Writing to the port register writes the value to the
RD3/REFB and RD2/CMPB, bypassing port latch. Some instructions operate internally as
the PORTD data and TRISD register set- read-modify-write. The BCF and BSF instructions, for
tings. example, read the register into the CPU, execute the bit
PORTD<1:0> also serve multiple functions. These pins operation, and write the result back to the register.
act as the I2C data and clock lines when the I2C module Caution must be used when these instructions are
is enabled. applied to a port with both inputs and outputs defined.
For example, a BSF operation on bit5 of PORTC will
The TRISD register controls the direction of the Port D cause all eight bits of PORTC to be read into the CPU.
pins. A 1 in each location configures the Then the BSF operation takes place on bit5 and
corresponding port pin as an input. Upon reset, this PORTC is written to the output latches. If another bit of
register sets to FFh, meaning all PORTD pins are ini- PORTC is used as a bi-directional I/O pin (say bit0) and
tially inputs. The data register should be initialized prior it is defined as an input at this time, the input signal
to configuring the port as outputs. present on the pin itself would be read into the CPU
Unused inputs should not be left floating to avoid and re-written to the data latch of this particular pin,
leakage currents. All pins have input protection diodes overwriting the previous content. As long as the pin
to VDD and VSS. stays in the input mode, no problem occurs. However,
if bit0 is switched into output mode later on, the content
EXAMPLE 5-3: INITIALIZING PORTD of the data latch may now be unknown.
CLRF PORTD ; Initialize PORTD data A pin actively outputting a LOW or HIGH should not be
; latches before setting driven from external devices at the same time in order
; the data direction to change the level on this pin (wire-or, wire-and).
; register The resulting high output currents may damage the
BSF STATUS, RP0 ; Select Bank1 chip.
MOVLW 0xFF ; Value used to initialize
Example 5-4 shows the effect of two sequential read
; data direction
modify write instructions (ex. BCF, BSF, etc.) on an I/O
MOVWF TRISD ; Set RD<7:0> as inputs
Port.
EXAMPLE 5-4: READ MODIFY WRITE

INSTRUCTIONS ON AN
I/O PORT
; Initial PORT settings: PORTC<7:4> Inputs
;
; PORTC<3:0> Outputs
; PORTC<7:6> have external pull-up and are not
; connected to other circuitry
;
; PORT latch PORT pins
; ---------- ----------
BCF PORTC, 7 ; 01pp pppp 11pp pppp

BCF PORTC, 6 ; 10pp pppp 11pp pppp
BSF STATUS,RP0 ;
BCF TRISC, 7 ; 10pp pppp 11pp pppp
BCF TRISC, 6 ; 10pp pppp 10pp pppp
;
; Note that the user may have expected the pin
; values to be 00pp pppp. The 2nd BCF caused
; RC7 to be latched as the pin value (High).

PIC14000
5.4.2 SUCCESSIVE OPERATIONS ON I/O The sequence of instructions should be such to allow
PORTS the pin voltage to stabilize before the next instruction
which causes that port to be read into the CPU is
The actual write to an I/O port happens at the end of an executed. Otherwise, the previous state of that pin may
instruction cycle, whereas for reading, the data must be be read into the CPU rather than the new state. When
valid at the beginning of the instruction cycle. in doubt, it is better to separate these instructions with
Therefore, care must be exercised if a write operation a NOP or another instruction not accessing this I/O
is followed by a read operation on the same I/O port. port.
FIGURE 5-13: SUCCESSIVE I/O OPERATION

Example showing write to PORTC followed by immediate read. Some delays in settling may cause old
Port data to be read, especially at higher clock frequencies. Data setup time = (0.25 Tcyc- Tpd), where
Tcyc = instruction cycle time.
Q1 | Q2 | Q3 | Q4 Q1 | Q2 | Q3 | Q4 Q1 | Q2 | Q3 | Q4 Q1 | Q2 | Q3 | Q4
PC PC + 1 PC + 2 PC + 3
MOVWF PORTC MOVF PORTC, W NOP NOP

Write to PORTC Read PORTC
RC<x> Pin values
Port pin sampled

here
Execute MOVWF Execute MOVF Execute NOP

PORTC PORTC, W

PIC14000
6.0 TIMER MODULES 8-bit timer
Readable and writable (file address 01h)
The PIC14000 contains two general purpose timer
modules, Timer0 (TMR0) and the Watchdog Timer 8-bit software programmable prescaler
(WDT). The ADTMR is described in the A/D section. Interrupt on overflow from FFh to 00h
The Timer0 module is identical to the Timer0 module of Figure 6-1 is a simplified block diagram of the Timer0
the PIC16C7X enhanced core products. It is an 8-bit module.
overflow counter. The Timer0 module will increment every instruction
The Timer0 module has a programmable prescaler cycle (without prescaler). If TMR0 is written, increment
option. This prescaler can be assigned to either the is inhibited for the following two cycles (Figure 6-2 and
Timer0 module or the Watchdog Timer (WDT). PSA Figure 6-3). The user can compensate by writing an
(OPTION<3>) assigns the prescaler, and PS2:PS0 adjusted value to TMR0.
(OPTION<2:0>) determines the prescaler value.
Timer0 can increment at the following rates: 1:1 (when
prescaler assigned to Watchdog Timer), 1:2, 1:4, 1:8,
1:16, 1:32, 1:64, 1:128, 1:256.
The Timer0 module has the following features:
FIGURE 6-1: TIMER0 AND WATCHDOG TIMER BLOCK DIAGRAM
Timer0
Data bus
FOSC/4 0
PSout 8
1
Sync with
1 Internal TMR0
clocks
RC3/T0CKI 0 PSout
pin Set T0IF
T0SE (2 cycle delay)
Interrupt on
Overflow
PSA
T0CS
Prescaler/
Postscaler
Local
Oscillator 0 8-bit Counter
18 mS 8
Timer 1
3
8-to-1 MUX PS2:PS0
PSA
Enable 1 0 PSA
WDT
Watchdog Timer Time-out
WDT Note: T0CS, T0SE, PSA, PS2:PS0 correspond to (OPTION<5:0>).

HIBERNATE Enable Bit

PIC14000
6.1 Timer0 Interrupt vice routine before re-enabling this interrupt. The
Timer0 module interrupt cannot wake the processor
The TMR0 interrupt is generated when the Timer0 from SLEEP since the timer is shut off during SLEEP.
overflows from FFh to 00h. This overflow sets the T0IF The timing of the Timer0 interrupt is shown in
bit. The interrupt can be masked by clearing bit T0IE Figure 6-4.
(INTCON<5>). Flag bit T0IF (INTCON<2>) must be
cleared in software by the TMR0 module interrupt ser-
FIGURE 6-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
PC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
(Program
Counter) PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6
Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Fetch
TMR0 T0 T0+1 T0+2 NT0 NT0 NT0 NT0+1 NT0+2
Instruction
Executed
Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0
executed reads NT0 reads NT0 reads NT0 reads NT0 + 1 reads NT0 + 2
FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
PC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
(Program
Counter) PC-1 PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6
Instruction MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Fetch
TMR0 T0 T0+1 NT0 NT0+1
Instruction
Execute Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0
executed reads NT0 reads NT0 reads NT0 reads NT0 reads NT0 + 1
FIGURE 6-4: TIMER0 INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(3)
TMR0 timer FEh FFh 00h 01h 02h

1 1
T0IF bit
(INTCON<2>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC PC PC +1 PC +1 0004h 0005h
Instruction
fetched Inst (PC) Inst (PC+1) Inst (0004h) Inst (0005h)
Instruction Inst (PC-1) Inst (PC) Dummy cycle Dummy cycle Inst (0004h)
executed
Note 1: T0IF interrupt flag is sampled here (every Q1).

2: Interrupt latency = 4Tcy where Tcy = instruction cycle time.
3: CLKOUT is available only in HS oscillator mode.

PIC14000
6.2 Using Timer0 with External Clock 6.2.2 TIMER0 INCREMENT DELAY
When the external clock input (pin RC3/T0CKI) is used Since the prescaler output is synchronized with the
for Timer0, it must meet certain requirements. The internal clocks, there is a small delay from the time the
external clock requirement is due to internal phase external clock edge occurs to the time the Timer0
clock (TOSC) synchronization. Also, there is a delay in module is actually incremented. Figure 6-5 shows the
the actual incrementing of TMR0 after synchronization. delay from the external clock edge to the timer
incrementing.
6.2.1 EXTERNAL CLOCK SYNCHRONIZATION
6.3 Prescaler
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization An 8-bit counter is available as a prescaler for the
of T0CKI with the internal phase clocks is Timer0 module, or as a post-scaler for the Watchdog
accomplished by sampling the prescaler output on the Timer (Figure 6-1). For simplicity, this counter is being
Q2 and Q4 cycles of the internal phase clocks referred to as prescaler throughout this data sheet.
(Figure 6-5). Therefore, it is necessary for T0CKI to be Note that there is only one prescaler available which is
high for at least 2Tosc (and a small RC delay of 20 ns) mutually exclusive between the Timer0 module and the
and low for at least 2Tosc (and a small RC delay of Watchdog Timer. Thus, a prescaler assignment for the
20 ns). Timer0 module means that there is no prescaler for the
When a prescaler is used, the external clock input is Watchdog Timer, and vice-versa.
divided by the asynchronous ripple counter-type Bit PSA and PS2:PS0 (OPTION<3:0>) determine the
prescaler so that the prescaler output is symmetrical. prescaler assignment and prescale ratio.
For the external clock to meet the sampling When assigned to the Timer0 module, all instructions
requirement, the ripple counter must be taken into writing to the Timer0 module (e.g., CLRF 1, MOVWF 1,
account. Therefore, it is necessary for T0CKI to have a BSF 1,x) will clear the prescaler. When assigned to
period of at least 4Tosc (and a small RC delay of 40 ns) WDT, a CLRWDT instruction will clear the prescaler
divided by the prescaler value. The only requirement along with the Watchdog Timer. The prescaler is not
on T0CKI high and low time is that they do not violate readable or writable.
the minimum pulse width requirement of 10 ns.
FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
EXT CLOCK INPUT OR Small pulse
PRESCALER OUT (NOTE 2) misses sampling
EXT CLOCK/PRESCALER (note 3)

OUTPUT AFTER SAMPLING
INCREMENT TMR0 (Q4)
TMR0 T0 T0 + 1 T0 + 2
Notes:
1. Delay from clock input change to TMR0 increment is 3 TOSC to 7 TOSC. (Duration of Q = TOSC).
Therefore, the error in measuring the interval between two edges on TMR0 input = 4 tosc max.
2. External clock if no prescaler selected, Prescaler output otherwise.
3. The arrows indicate the points in time where sampling occurs.

PIC14000
6.3.1 SWITCHING PRESCALER ASSIGNMENT To change prescaler from the WDT to the Timer0
module use the sequence shown in Example 6-2. This
The prescaler assignment is fully under software precaution must be taken even if the WDT is disabled.
control, i.e., it can be changed on the fly during
program execution. To avoid an unintended device
EXAMPLE 6-2: CHANGING PRESCALER
RESET, the following instruction sequence
(WDTTIMER0)
(Example 6-1) must be executed when changing the
CLRWDT ;Clear WDT and
prescaler assignment from Timer0 to WDT. ;prescaler
BSF STATUS, RP0
EXAMPLE 6-1: CHANGING PRESCALER MOVLW B'xxxx0xxx' ;Select TMR0, new
(TIMER0WDT) ;prescale value and
;clock source
1.BCF STATUS,RP0 ;Skip if already in MOVWF OPTION
; Bank 0 BCF STATUS, RP0
2.CLRWDT ;Clear WDT
3.CLRF TMR0 ;Clear TMR0 & Prescaler
4.BSF STATUS, RP0 ;Bank 1
5.MOVLW '00101111'b;These 3 lines (5, 6, 7)
6.MOVWF OPTION ; are required only
; if desired PS<2:0>
7.CLRWDT ; are 000 or 001
8.MOVLW '00101xxx'b ;Set Postscaler to
9.MOVWF OPTION ; desired WDT rate
10.BCF STATUS, RP0 ;Return to Bank 0
TABLE 6-1: SUMMARY OF TIMER0 REGISTERS
Register Name Function Address Power-on Reset Value

TMR0 Timer/counter register 01h xxxx xxxx
OPTION Configuration and prescaler assign- 81h 1111 1111
ment bits for TMR0.
INTCON TMR0 overflow interrupt flag and 0Bh 0000 000x
mask bits.
Legend: x = unknown,
Note 1: For reset values of registers in other reset situations refer to Table 10-4.
TABLE 6-2: REGISTERS ASSOCIATED WITH TIMER0
01h TMR0 TIMER0 TIMER/COUNTER
0Bh/8Bh INTCON GIE PEIE T0IE r r T0IF r r
81h OPTION RCPU r T0CS T0SE PSA PS2 PS1 PS0
87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
Legend: r = Reserved locations
Shaded boxes are not used by Timer0 module

PIC14000
7.0 INTER-INTEGRATED CIRCUIT In the I2C interface protocol each device has an
SERIAL PORT (I2C) address. When a master wishes to initiate a data
transfer, it first transmits the address of the device that
The I2C module is a serial interface useful for it wishes to talk to. All devices listen to see if this is
communicating with other peripheral or microcontroller their address. Within this address, a bit specifies if the
devices. These peripheral devices may be serial master wishes to read from or write to the slave device.
EEPROMs, shift registers, display drivers, A/D The master and slave are always in opposite modes
converters, etc. The I2C module is compatible with the (transmitter/receiver) of operation during a data
following interface specifications: transfer. They may operate in either of these two
Inter-Integrated Circuit (I2C) states:
System Management Bus (SMBus) Master-transmitter and Slave-receiver
Note: 2
The I C module on PIC14000 only Slave-transmitter and Master-receiver
supports I2C mode. This is different from In both cases the master generates the clock signal.
the standard module used on the
The output stages of the clock (SCL) and data (SDA)
PIC16C7X family, which supports both
lines must have an open-drain or open-collector in
I2C and SPI modes. Caution should be
order to perform the wired-AND function of the bus.
exercised to avoid enabling SPI mode on
External pull-up resistors are used to ensure a high
the PIC14000.
level when no device is pulling the line down. The
This section provides an overview of the Inter-IC(I2C) number of devices that may be attached to the I2C bus
bus. The I2C bus is a two-wire serial interface is limited only by the maximum bus loading specifica-
developed by the Philips Corporation. The original tion of 400 pF.
specification, or standard mode, was for data transfers
of up to 100 Kbps. An enhanced specification, or fast 7.1 Initiating and Terminating Data
mode, supports data transmission up to 400 Kbps. Transfer
Both standard mode and fast mode devices will
inter-operate if attached to the same bus. During times of no data transfer (idle time), both the
clock line (SCL) and the data line (SDA) are pulled high
The I2C interface employs a comprehensive protocol to through the external pull-up resistors. The START and
ensure reliable transmission and reception of data. STOP determine the start and stop of data
When transmitting data, one device is the master transmission. The START is defined as a high to low
(generates the clock) while the other device(s) acts as transition of SDA when SCL is high. The STOP is
the slave. All portions of the slave protocol are defined as a low to high transition of SDA when SCL is
implemented in the I2C modules hardware, except high. Figure 7-1 shows the START and STOP. The
general call support, while portions of the master proto- master generates these conditions for starting and ter-
col will need to be addressed in the PIC14000 soft- minating data transfer. Due to the definition of the
ware. Table 7-1 defines some of the I2C bus START and STOP, when data is being transmitted the
terminology. For additional information on the I2C inter- SDA line can only change state when the SCL line is
face specification, please refer to the Philips Corpora- low.
tion document The I 2C-bus and How to Use It.
FIGURE 7-1: I2C START AND STOP CONDITIONS
SDA
SCL S P
Start Change Change Stop

Condition of Data of Data Condition
Allowed Allowed

PIC14000
FIGURE 7-2: I2CSTAT: I2C PORT STATUS REGISTER
U U R R R R R R
_ _ D/A P S R/W UA BF Register: I2CSTAT W: Writable bit
Address: 94h R: Readable bit
POR value: 00h U: Unimplemented, read as 0
bit7 bit0
BF: Buffer full

Receive
1 = Receive complete, I2CBUF is full
0 = Receive not complete, I2CBUF is empty
Transmit
1 = Transmit in progress, I2CBUF is full
0 = Transmit complete, I2CBUF is empty
UA: Update Address (10-bit I2C slave mode only)
1 = Indicate that the user needs to update the address in the I2CADD
register.
0 = Address does not need to be updated
R/W: Read/write bit information
This bit holds the R/W bit information received following the last address
match. This bit is only valid during the transmission.
The user may use this bit in software to determine whether transmission
or reception is in progress.
1 = Read
0 = Write
S: Start bit
This bit is cleared when the I2C module is disabled (I2CEN is cleared)
1 = Indicates that a start bit has been detected last. This bit is 0 on
reset.
0 = Start bit was not detected last
P: Stop bit
This bit is cleared when the I2C module is disabled (I2CEN is cleared)
1 = Indicates that a stop bit has been detected last.
0 = Stop bit was not detected last
D/A: Data/Address bit
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was address
Unimplemented: read as 0

PIC14000
FIGURE 7-3: I2CCON: I2C PORT CONTROL REGISTER
R/W R/W R/W R/W R/W R/W R/W R/W
WCOL I2COV I2CEN CKP I2CM3 I2CM2 I2CM1 I2CM0 Register: I2CCON W: Writable bit
Address: 14h R: Readable bit
bit7 bit0 POR value: 00h U: Unimplemented, read as 0
I2CM<3:0>: I2C mode select

0110 = I2C slave mode, 7-bit address
0111 = I2C slave mode, 10-bit address
1011 = I2C firmware controlled master mode (slave idle)
1110 = I2C slave mode, 7-bit address with start and stop bit interrupts
enabled
1111 = I2C slave mode, 10-bit address with start and stop bit interrupts
enabled
Any other combinations of I2CM<3:0>
are illegal and should NEVER be used.
CKP: Clock polarity select

SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch)
Note: Used to ensure data setup time
I2CEN: I2C enable

1 = Enables the serial port and configures SDA and SCL pins as serial
port pins. When enabled, these pins must be configured as input
or output.
0 = Disables serial port and configures these pins as I/O port pins
I2COV: Receive overflow flag

1 = A byte is received while the I2CBUF is still holding the previous
byte. I2COV is a don't care in transmit mode.
I2COV must be cleared in software.
0 = No overflow
WCOL: Write collision detect

1 = the I2CBUF register is written while it is still transmitting the previ-
ous word.
0 = No collision

PIC14000
TABLE 7-1: I2C BUS TERMINOLOGY
Term Description
Transmitter The device that sends the data to the bus.
Receiver The device that receives the data from the bus.
Master The device which initiates the transfer, generates the clock, and terminates the transfer.
Slave The device addressed by a master.
Multi-master More than one master device in a system. These masters can attempt to control the bus
at the same time without corrupting the message.
Arbitration Procedure that ensures that only one of the master devices will control the bus. This
ensures that the transfer data does not get corrupted.
Synchronization Procedure where the clock signals of two or more devices are synchronized.
FIGURE 7-4: I2C 7-BIT ADDRESS FORMAT 7.2 Addressing I2C Devices
MSb LSb There are two address formats. The simplest is the
S R/W ACK 7-bit address format with a R/W bit (Figure 7-4). The
address is the most significant seven bits of the byte.
slave address Sent by For example when loading the I2CADD register, the
S Start Condition Slave least significant bit is a dont care. The more complex
R/W Read/Write pulse is the 10-bit address with a R/W bit (Figure 7-5). For
ACK Acknowledge
10-bit address format, two bytes must be transmitted
with the first five bits specifying this to be a 10-bit
FIGURE 7-5: I2C 10-BIT ADDRESS address.
FORMAT
S 1 1 1 1 0 A9 A8 RW ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK
sent by slave
= 0 for write
S - Start Condition
R/W - Read/Write Pulse
ACK - Acknowledge

PIC14000
7.3 Transfer Acknowledge accomplished by setting SMHOG (MISC<7>) high.
Clearing MISC<7> will resume the data transfer.
All data must be transmitted per byte, with no limit to Figure 7-7 shows a data transfer waveform.
the number of bytes transmitted per data transfer. After
Figure 7-8 and Figure 7-9 show master-transmitter and
each byte, the slave-receiver generates an
master-receiver data transfer sequences.
acknowledge bit (ACK). This is shown in Figure 7-6.
When a slave-receiver doesnt acknowledge the slave FIGURE 7-6: I2C SLAVE-RECEIVER
address or received data, the master must abort the ACKNOWLEDGE
transfer. The slave must leave SDA high so that the
master can generate the STOP (Figure 7-1). Data
Output by
If the master is receiving the data (master-receiver), it Transmitter
not acknowledge
generates an acknowledge signal for each received Data
Output by
byte of data, except for the last byte. To signal the end Receiver
acknowledge
of data to the slave-transmitter, the master does not SCL from
1 2 8 9
generate an acknowledge. The slave then releases the Master
SDA line so the master can generate the STOP. The S

master can also generate the STOP during the Start Clock pulse for
Condition acknowledgement
acknowledge pulse for valid termination of data
transfer.
If the slave needs to delay the transmission of the next
byte, holding the SCL line low will force the master into
a wait state. Data transfer continues when the slave
releases the SCL line. This allows the slave to move
the received data or fetch the data it needs to transfer
before allowing the clock to start. This wait state can be
FIGURE 7-7: SAMPLE I2C DATA TRANSFER
SDA
MSB acknowledgement byte complete. acknowledgement
signal from receiver interrupt with receiver signal from receiver
clock line held low while

interrupts are serviced
SCL S 1 2 7 8 9 1 2 38 9 P
Start Stop
Condition Address R/W ACK Wait Data ACK Condition
State

PIC14000
When a master does not wish to relinquish the bus (by bus-free state). This allows a master to send
generating a STOP condition), a repeated START (Sr) commands to the slave and then receive the
must be generated. This condition is identical to the requested information or to address a different slave
START (SDA goes high-to-low while SCL is high), but device. This sequence is shown in Figure 7-10.
occurs after a data transfer acknowledge pulse (not the
FIGURE 7-8: MASTER - TRANSMITTER SEQUENCE
For 7-bit address: For 10-bit address:

S Slave Address R/W A DATA A DATA A/A P S Slave Address R/W A1 Slave Address A2
first 7 bits second byte
"0" (write) data transferred
(write)
(n bytes - acknowledge)
A master transmitter addresses a slave receiver with a
7-bit address. The transfer direction is not changed. Data A Data A/A P
A = acknowledge (SDA low)
From master to slave A = not acknowledge (SDA high)
S = START condition A master transmitter addresses a slave receiver with a
From slave to master P = STOP condition 10-bit address.
FIGURE 7-9: MASTER - RECEIVER SEQUENCE
For 7-bit address: For 10-bit address:

S Slave Address R/W A DATA A DATA A P S Slave Address R/W A1 Slave Address A2
first 7 bits second byte
(read) data transferred
(write)
(n bytes - acknowledge)
A master reads a slave immediately after the first byte.
Sr Slave Address R/W A3 Data A Data A P
first 7 bits
A = acknowledge (SDA low) (read)
S = START condition A master transmitter addresses a slave receiver with a
From slave to master P = STOP condition 10-bit address.
FIGURE 7-10: COMBINED FORMAT
(read or write)
(n bytes + acknowledge)
S Slave Address R/W A DATA A/A Sr Slave Address R/W A DATA A/A P
(read) Sr = repeated (write) Direction of transfer

START condition may change at this point
Transfer direction of data and acknowledgement bits depends on R/W bits.
Combined Format:
S Slave Address R/W A Slave Address A Data A Data A/A Sr Slave Address R/W A Data A Data A P
first 7 bits second byte first 7 bits
(write) (read)
Combined format - A master addresses a slave with a 10-bit address, then transmits
data to this slave and reads data from this slave.
A = acknowledge (SDA low)
S = START condition
From slave to master P = STOP condition

PIC14000
7.4 Multi-Master Operation FIGURE 7-11: MULTI-MASTER
ARBITRATION (2 MASTERS)
The I2C protocol allows a system to have more than
one master. This is called multi-master. When two or transmitter 1 loses arbitration
more masters try to transfer data at the same time, DATA 1 SDA
arbitration and synchronization occur. DATA 1
7.4.1 ARBITRATION DATA 2
Arbitration takes place on the SDA line, while the SCL

SDA
line is high. The master which transmits a high when
the other master transmits a low loses arbitration
SCL
(Figure 7-11) and turns off its data output stage. A
master which lost arbitrating can generate clock pulses
until the end of the data byte where it lost arbitration.
When the master devices are addressing the same FIGURE 7-12: I2C CLOCK
device, arbitration continues into the data. SYNCHRONIZATION
Masters that also incorporate the slave function, and
have lost arbitration must immediately switch over to wait start counting
slave-receiver mode. This is because the winning state HIGH period
master-transmitter may be addressing it.
CLK
Arbitration is not allowed between:
1
A repeated START counter
A STOP and a data bit CLK reset
2
A repeated START and a STOP
Care needs to be taken to ensure that these conditions
SCL
do not occur.
7.4.2 CLOCK SYNCHRONIZATION
Clock synchronization occurs after the devices have

started arbitration. This is performed using a
wired-AND connection to the SCL line. A high to low
transition on the SCL line causes the concerned
devices to start counting off their low period. Once a
device clock has gone low, it will hold the SCL line low
until its SCL high state is reached. The low to high
transition of this clock may not change the state of the
SCL line, if another device clock is still within its low
period. The SCL line is held low by the device with the
longest low period. Devices with shorter low periods
enter a high wait-state, until the SCL line comes high.
When the SCL line comes high, all devices start
counting off their high periods. The first device to
complete its high period will pull the SCL line low. The
SCA line high time is determined by the device with the
shortest high period. This is shown in the Figure 7-12.

PIC14000
FIGURE 7-13: I2C BLOCK DIAGRAM
Internal
data bus
MISC<4>
Read Write
RC6/SCLA
I2CBUF
RC7/SDAA SCK
4:2 Shift
clock
MUX SDA
RD0/SCLB I2CSR
MSB
RD1/SDAB
Match Detect Addr_Match
I2CADD
Set, Reset
Start and S, P bits
Stop bit detect (I2CSTAT Reg)
7.5 I2C Operation I2C Slave mode (7-bit address), with start and
stop bit interrupts enabled
The I2C module in I2C mode fully implements all slave I2C Slave mode (10-bit address), with start and
functions, and provides support in hardware to facilitate stop bit interrupts enabled
software implementations of the master functions. The
I2C Firmware Controlled Master mode, slave is
I2C module implements the standard and fast mode
idle
specifications as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the Selection of any I2C mode with the I2CEN bit set, forces
RC6/SCLA pin, which is the I2C clock, and the the SCL and SDA pins to be open collector, provided
RC7/SDAA pin which acts as the I2C data. The I2C these pins are set to inputs through the TRISC bits.
module can also be accessed via the RD0/SCLB and The I2CSTAT register gives the status of the data
RD1/SDAB pins by setting I2CSEL (MISC<4>).The transfer. This information includes detection of a
user must configure these pins as inputs or outputs START or STOP bit, specifies if the received byte was
through the TRISC<7:6> or TRISD<1:0> bits. A block data or address, if the next byte is the completion of
diagram of the I2C module in I2C mode is shown in 10-bit address, and if this will be a read or write data
Figure 7-13. The I2C module functions are enabled by transfer. The I2CSTAT register is read only.
setting the I2CCON<5> bit.
The I2CBUF is the register to which transfer data is
The I2C module has five registers for I2C operation. written to or read from. The I2CSR register shifts the
These are the: data in or out of the device. In receive operations, the
I2C Control Register (I2CCON) I2CBUF and I2CSR create a double buffered receiver.
I2C Status Register (I2CSTAT) This allows reception of the next byte before reading
the last byte of received data. When the complete byte
Serial Receive/Transmit Buffer (I2CBUF)
is received, it is transferred to the I2CBUF and PIR1<3>
I2C Shift Register (I2CSR) - Not directly is set. If another complete byte is received before the
accessible I2CBUF is read, a receiver overflow has occurred and
Address Register (I2CADD) the I2CCON<6> is set.
The I2CCON register (14h) allows control of the I2C The I2CADD register holds the slave address. In 10-bit
operation. Four mode selection bits (I2CCON<3:0>) mode, the user needs to write the high byte of the
allow one of the following I2C modes to be selected: address (1 1 1 1 0 A9 A8 0). Following the high byte
I2C Slave mode (7-bit address) address match, the low byte of the address needs to be
I2C Slave mode (10-bit address) loaded (A7-A0).

PIC14000
7.5.1 SLAVE MODE In this case, the I2CSR value is not loaded into the
I2CBUF, but the I2CIF bit is set. Table 7-2 shows what
In slave mode, the SCLx and SDAx pins must be happens when a data transfer byte is received, given
configured as inputs (TRISC<7:6> or TRISD<1:0> are the status of the BF and I2COV bits. The shaded boxes
set). The I2C module will override the input state with show the conditions where user software did not
the output data when required (slave-transmitter). properly clear the overflow condition. The BF flag is
When an address is matched or the data transfer from cleared by reading the I2CBUF register while the
an address match is received, the hardware I2COV bit is cleared through software.
automatically will generate the acknowledge (ACK) The SCL clock input must have a minimum high and
pulse, and then load the I2CBUF with the received low for proper operation. The high and low times of the
value in the I2CSR. I2C specification as well as the requirement of the I2C
There are two conditions that will cause the I2C module module is shown in the AC timing specifications.
not to give this ACK pulse. These are if either (or both)
occur:
the Buffer Full (BF), I2CSTAT<0>, bit was set
before the transfer was received, or
the Overflow (I2COV), I2CCON<6> bit was set
before the transfer was received.
TABLE 7-2: DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data Transfer

is Received Set I2CIF bit
BF I2COV I2CSR-> I2CBUF Generate ACK Pulse (I2C interrupt if enabled)
0 0 Yes Yes Yes
1 0 No No Yes
1 1 No No Yes
0 1 No No Yes

PIC14000
7.5.1.1 ADDRESSING 4. Receive second (low) byte of address (I2CIF, BF
and UA are set).
Once the I2C module has been enabled, the I2C waits
5. Update I2CADD with first (high) byte of address
for a START to occur. Following the START, the 8-bits
(clears UA, if match releases SCL line).
are shifted into the I2CSR. All incoming bits are
sampled with the rising edge of the clock (SCL) line. 6. Read I2CBUF (clears BF) and clear I2CIF
The I2CSR<7:1> is compared to the I2CADD register. 7. Receive Repeated START.
The address is compared on the falling edge of the 8. Receive first (high) byte of address (I2CIF and
eighth clock (SCL) pulse. If the addresses match, and BF are set).
the BF and I2COV bits are clear, the following things 9. Read I2CBUF (clears BF) and clear I2CIF.
happen:
7.5.1.2 RECEPTION
I2CSR loaded into I2CBUF
Buffer Full (BF) bit is set When the R/W bit of the address byte is clear and an
ACK pulse is generated address match occurs, the R/W bit of the I2CSTAT
I2C Interrupt Flag (I2CIF) is set (interrupt is register is cleared. The received address is loaded into
generated if enabled (I2CIE set) on falling edge of the I2CBUF.
ninth SCL pulse. When the address byte overflow condition exists then
In 10-bit address mode, two address bytes need to be no acknowledge (ACK) pulse is given. An overflow
received by the slave (Figure 7-5). The five most condition is defined as either the BF bit (I2CSTAT<0>)
significant bits (MSbs) of the first address byte specify is set or the I2COV bit (I2CCON<6>) is set
if this is a 10-bit address. The R/W bit (bit 0) must (Figure 7-14).
specify a write, so the slave device will received the An I2CIF interrupt is generated for each data transfer
second address byte. For a 10-bit address the first byte byte. The I2CIF bit must be cleared in software, and the
would equal 1 1 1 1 0 A9 A8 0, where A9 and A8 are I2CSTAT register is used to determine the status of the
the two MSbs of the address. The sequence of events byte. In master mode with slave enabled, three inter-
for 10-bit address are as follows, with steps 7-9 for rupt sources are possible. Reading BF, P and S will
slave-transmitter: indicate the source of the interrupt.
1. Receive first (high) byte of address (I2CIF, BF Caution: BF is set after receipt of eight bits and auto-
and UA are set). matically cleared after the I2CBUF is read.
2. Update I2CADD with second (low) byte of However, the flag is not actually cleared
address (clears UA and releases SCL line). until receipt of the acknowledge pulse. Oth-
3. Read I2CBUF (clears BF) and clear I2CIF. erwise extra reads appear to be valid.
FIGURE 7-14: I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)

Receiving Address R/W=0
Receiving Data ACK Receiving Data ACK
A7 A6 A5 A4 A3 A2 A1 ACK
SDA D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
I2CIF (PIR1<3>) Bus Master

terminates
transfer
BF (I2CSTAT<0>)
Cleared in software
I2CBUF is read
I2COV (I2CCON<6>)
I2COV is set
because I2CBUF is
still full. ACK is not sent.

PIC14000
7.5.1.3 TRANSMISSION A I2CIF interrupt is generated for each data transfer
byte. The I2CIF bit must be cleared in software, and the
When the R/W bit of the address byte is set and an I2CSTAT register is used to determine the status of the
address match occurs, the R/W bit of the I2CSTAT byte. The I2CIF bit is set on the falling edge of the ninth
register is set. The received address is loaded into the clock pulse.
I2CBUF The ACK pulse will be sent on the ninth bit, and
the SCL pin is held low. The transmit data must be As a slave-transmitter, the ACK pulse from the
loaded into the I2CBUF register, which also loads the master-receiver is latched on the rising edge of the
I2CSR register. Then the SCL pin should be enabled by ninth SCL input pulse. If the SDA line was high (not
setting the CKP bit (I2CCON<4>). The eight data bits ACK), then the data transfer is complete. The slave
are shifted out on the falling edge of the SCL input. This then monitors for another occurrence of the START bit.
ensures that the SDA signal is valid during the SCL If the SDA line was low (ACK), the transmit data must
high time (Figure 7-15). be loaded into the I2CBUF register, which also loads
the I2CSR register. Then the SCL pin should be
enabled by setting the CKP bit (I2CCON<4>).
FIGURE 7-15: I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)

Receiving Address R/W = 1 Transmitting Data ACK
SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
Data in SCL held low
sampled while CPU
responds to I2CIF
I2CIF (PIR1<3>)
BF (I2CSTAT<0>)
cleared in software From I2CIF interrupt
I2CBUF is written in software service routine
CKP (I2CCON<4>)
Set bit after writing to I2CBUF

PIC14000
7.5.2 MASTER MODE 7.5.3 MULTI-MASTER MODE
Master mode operation is supported by interrupt In multi-master mode, the interrupt generation on the
generation on the detection of the START and STOP. detection of the START and STOP allows the
The STOP(P) and START(S) bits are cleared from a determination of when the bus is free. The STOP (P)
reset or when the I2C module is disabled. Control of the and START (S) bits are cleared from a reset or when
I2C bus may be taken when the P bit is set, or the bus the I2C module is disabled. Control of the I2C bus may
is idle and both the S and P bits are cleared. be taken when the P bit is set, or the bus is idle and
In master mode, the SCL and SDA lines are both the S and P bits are cleared. When the bus is
manipulated by changing the corresponding busy, enabling the I2C interrupt will generate the
TRISC<7:6> or TRISD<1:0> bits to an output (cleared). interrupt when the STOP occurs.
The output level is always low, regardless of the In multi-master operation, the SDA line must be
value(s) in PORTC<7:6> or PORTD<1:0>. So when monitored to see if the signal level is the expected
transmitting data, a 1 data bit must have the output level. This check only needs to be done when a
TRISC<7> or TRISD<1> bit set (input) and a 0 data high level is output. If a high level is expected and low
bit must have the TRISC<7> or TRISD<1> bit cleared level is present, the device needs to release the SDA
(output). The same scenario is true for the SCL line and SCL lines (set TRISC<7:6>). There are two stages
with the TRISC<6> or TRISD<0> bit. where this arbitration can be lost, these are:
The following events will cause the I2C interrupt Flag Address Transfer
(I2CIF) to be set (I2C interrupt if enabled): Data Transfer
START When the slave logic is enabled, the slave continues to
STOP receive. If arbitration was lost during the address
Data transfer byte transmitted/received transfer stage, the device may being addressed. If
addressed an ACK pulse will be generated. If
Master mode of operation can be done with either the
arbitration was lost during the data transfer stage, the
slave mode idle (I2CM3...I2CM0 = 1011b) or with the
device will need to re-transfer the data at a later time.
slave active. When both master and slave modes are
enabled, the software needs to differentiate the
source(s) of the interrupt.
TABLE 7-3: REGISTERS ASSOCIATED WITH I2C OPERATION

0B/8Bh INTCON GIE PEIE T0IE r r T0IF r r
0Ch PIR1 CMIF PBIF I2CIF RCIF ADCIF OVFIF
8Ch PIE1 CMIE PBIE I2CIE RCIE ADCIE OVFIE
13h I2CBUF I2C Serial Port Receive Buffer/Transmit Register
93h I2CADD I2C mode Synchronous Serial Port (I2C mode) Address Register
14h I2CCON WCOL I2CON I2CEN CKP I2CM3 I2CM2 I2CM1 I2CM0
94h I2CSTAT D/A P S R/W UA BF
9Eh MISC SMHOG SPGNDB SPGNDA I2CSEL SMBUS INCLKEN OSC2 OSC1
87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
88h TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0
Legend: = Unimplemented location, read as 0
r = reserved locations, default is POR value and should not be overwritten with any value
Note: Shaded boxes are not used by the I2C module.

PIC14000
FIGURE 7-16: MISC REGISTER
9Eh Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MISC SMHOG SPGNDB SPGNDA I2CSEL SMBUS INCLKEN OSC2 OSC1
Read/Write R/W R/W R/W R/W R/W R/W R/W R
POR value 00h 0 0 0 0 0 0 0 X
Bit Name Function
SMHOG enable
1 = Stretch I2C CLK signal (hold low) when receive data buffer is full (refer to
B7 SMHOG Section 7.5.4). For pausing I2C transfers while preventing interruptions of A/D
conversions.
0 = Disable I2C CLK stretch.
Serial Port Ground Select
B6 SPGNDB 1 = PORTD<1:0> ground reference is the RD5/AN5 pin.
0 = PORTD<1:0> ground reference is VSS.
B5 SPGNDA 1 = PORTC<7:6> ground reference is the RA1/AN1 pin.
0 = PORTC<7:6> ground reference is VSS.
I2C Port select Bit.
B4 I2CSEL 1 = PORTD<1:0> are used as the I2C clock and data lines.
0 = PORTC<7:6> are used as the I2C clock and data lines.
SMBus-Compatibility Select
1 = SMBus compatibility mode is enabled. PORTC<7:6> and PORTD<1:0> have
B3 SMBus SMBus-compatible input thresholds.
0 = SMBus-compatibility is disabled. PORTC<7:6> and PORTD<1:0> have Schmitt Trig-
ger input thresholds.
Oscillator Output Select (available in IN mode only).
B2 INCLKEN 1 = Output IN oscillator signal divided by four on OSC2 pin.
0 = Disconnect IN oscillator signal from OSC2 pin.
OSC2 output port bit (available in IN mode only).
B1 OSC2 Writes to this location affect the OSC2 pin in IN mode. Reads return the value of the
output latch.
OSC1 input port bit (available in IN mode only).
B0 OSC1 Reads from this location return the status of the OSC1 pin in IN mode. Writes have no
effect.

PIC14000
FIGURE 7-17: OPERATION OF THE I2C IN IDLE_MODE, RCV_MODE OR XMIT_MODE

IDLE_MODE (7-bit):
if (Addr_match) { Set interrupt;
if (R/W = 1) { Send ACK = 0;
set XMIT_MODE;
}
else if (R/W = 0) set RCV_MODE;
}
RCV_MODE:
if ((I2CBUF=Full) OR (I2COV = 1))
{ Set I2COV;
Do not acknowledge;
}
else { transfer I2CSR I2CBUF;
send ACK = 0;
}
Receive 8-bits in I2CSR;
Set interrupt;
XMIT_MODE:
While ((I2CBUF = Empty) AND (CKP=0)) Hold SCL Low;
Send byte;
Set interrupt;
if (ACK Received = 1) { End of transmission;
Go back to IDLE_MODE;
}
else if (ACK Received = 0) Go back to XMIT_MODE;
IDLE_MODE (10-Bit):
If (High_byte_addr_match AND (R/W = 0))
{ PRIOR_ADDR_MATCH = FALSE;
Set interrupt;
if ((I2CBUF = Full) OR ((I2COV = 1))
{ Set I2COV;
Do not acknowledge;
}
else { Set UA = 1;
Send ACK = 0;
While (I2CADD not updated) Hold SCL low;
Clear UA = 0;
Receive Low_addr_byte;
Set interrupt;
Set UA = 1;
If (Low_byte_addr_match)
{ PRIOR_ADDR_MATCH = TRUE;
Send ACK = 0;
while (I2CADD not updated) Hold SCL low;
Clear UA = 0;
Set RCV_MODE;
}
}
}
else if (High_byte_addr_match AND (R/W = 1)
{ if (PRIOR_ADDR_MATCH)
{ send ACK = 0;
set XMIT_MODE;
}
else PRIOR_ADDR_MATCH = FALSE;
}

PIC14000
7.5.4 SMBus AND ACCESS.bus A mechanism to stretch the I2C clock time has
CONSIDERATIONS been implemented to support SMBus slave
transactions. The SMHOG bit (MISC<7>) allows
PIC14000 is compliant with the SMBus specification hardware to automatically force and hold the I2C
published by Intel. Some key points to note regarding clock line low when a data byte has been
the bus specifications and how it pertains to the received. This prevents the SMBus master from
PIC14000 hardware are listed below: overflowing the receive buffer in instances where
SMBus has fixed input voltage thresholds. the microcontroller may be to busy servicing
PIC14000 I/O buffers have programmable levels higher priority tasks to respond to a I2C module
that can be selected to be compatible with both interrupt. Or, if the microcontroller is in SLEEP
SMBus threshold levels via the SMBus and mode and needs time to wake-up and respond to
SPGND bits in the MISC register. the I2C interrupt.
FIGURE 7-18: SMHOG STATE MACHINE

SMHOG = 0
A SM
=0 HO
G
OG =1
S MH SM
HO
G
I2CIF = 1 =0
I2CIF = 1
E/DRIVE
B
SCL
LOW I2
CI
F= SMHOG = 0
SMHOG = 0
I2CIF = 0
SCL = 0
I2CIF = 0
C
D
I2CIF = 1
I2CIF = 0
SCL = 1

PIC14000
NOTES:

PIC14000
8.0 ANALOG MODULES FOR A/D The maximum A/D timer count is 65,536. It can be
clocked by the on-chip or external oscillator. At a 4 MHz
CONVERSION oscillation frequency, the maximum conversion time is
8.1 Overview 16.38 ms for a full count. A typical conversion should
complete before full-count is reached. A timer overflow
The PIC14000 includes analog components to create a flag is set once the timer rolls over (FFFFh to 0000h),
slope A/D converter including: and an interrupt is sent to the CPU, if enabled.
Comparator End-user calibration is simplified or eliminated by mak-
4-bit programmable current source ing use of the on-chip EPROM. Internal component val-
16-channel analog mux ues are measured at factory final test and stored in the
16-bit timer with capture register memory for use by the application firmware.
Each channel is converted independently by means of Periodic conversion cycles should be performed on the
a slope conversion method using a single precision bandgap and slope references (described in
comparator. The programmable current source feeds Section 9.0) to compensate for A/D component drift.
an external 0.1 F (nominal) capacitor to generate the Measurements for the reference voltage count are
ramp voltage used in the conversion. equated to the voltage value stored into EPROM during
calibration. All other channel measurements are
8.2 Conversion Process compensated for by ratioing the actual count with the
bandgap count and multiplying by the bandgap voltage
These are the steps to perform data conversion:
value stored in EPROM. Since all measurements are
Clear REFOFF (SLPCON<5>) and ADOFF relative to the reference, offset voltages inherent in the
(SLPCON<0>) bits to enable the A/D module. comparator are cancelled out. See AN624, PIC14000
Initialize ADCON1<7:4> to initialize the program- A/D Theory and Implementation for further details of
mable current source. A/D operation.
Set ADRST (ADCON0<1>), for a minimum of 200 The analog components used in the conversion and
s to stop the timer and fully discharge the ramp the A/D timer can be disabled during idle periods for
capacitor to ground. maximum power savings. Power-saving can be
The A/D timer (ADTMR) increments from 0000h achieved via software and/or hardware control
to FFFFh and must be initialized before each con- (Section 10.8).
version.
To start a conversion, clear ADRST through soft- 8.3 A/D Timer (ADTMR) Module
ware, it will allow the timer to begin counting and
The A/D timer (ADTMR) is comprised of a 16-bit up
the ramp capacitor to begin charging.
timer, which is incremented every oscillator cycle.
When the ramp voltage exceeds the analog input, ADTMR is reset to 0000h by a power-up reset; other-
the comparator output changes from high to low. wise the software must initialize it after each conver-
This transition causes a capture event and copies sion. A separate 16-bit capture register (ADCAP) is
the current A/D timer value into the 16-bit capture used to capture the ADTMR count if an A/D capture
register. event occurs (see below). Both the A/D timer and cap-
An interrupt is generated to the CPU if enabled. ture register are readable and writable. The low byte of
the A/D timer (ADTMRL) is accessed at location 0Eh
Note: The A/D timer continues to run following a
while the high byte (ADTMRH) is accessed at location
capture event.
0Fh. Similarly, the low byte of the A/D capture register
(ADCAP) is accessed at location 15h, and the high byte
is located at 16h.

PIC14000
Caution: Reading or writing the ADTMR register A CPU interrupt will be generated if bit ADCIE
during an A/D conversion cycle can pro- (PIE1<1>) is set to 1 (interrupt enabled). In addition,
duce unpredictable results and is not the Global Interrupt Enable and Peripheral Interrupt
recommended. Enables (INTCON<7,6>) must also be set. Software is
responsible for clearing the ADCIF flag prior to the next
Note: The correct sequence for writing the
conversion cycle. Note that this interrupt can only occur
ADTMR register is HI byte followed by LO
once per conversion cycle.
byte. Reversing this order will prevent the
A/D timer from running. In a timer overflow condition, the timer rolls over from
FFFFh to 0000h, and a capture overflow flag (OVFIF)
During conversion one or both of the following events
is asserted (PIR1<0>). The timer continues to incre-
will occur:
ment following a timer overflow. A CPU interrupt can be
1. capture event generated if bit OVFIE (PIE1<0>) is set (interrupt
2. timer overflow enabled). In addition, the Global Interrupt Enable and
Peripheral Interrupt Enables (INTCON<7,6>) must also
In a capture event, the comparator trips when the slope
be set. Software is responsible for clearing the OVFIF
voltage on the CDAC output exceeds the input voltage,
flag prior to the next conversion cycle.
causing the comparator output to transition from high to
low. This causes a transfer of the current timer count to
the capture register and sets the ADCIF flag
(PIR1<1>).
FIGURE 8-1: A/D BLOCK DIAGRAM

OSC1
0
Internal ADOFF
Oscillator WRITE_TMR Clock
Stop
FOSC ADRST Logic
(Configuration Bit)
AMUXOE
(ADCON0<2>)
RA0/AN0
RESERVED 15
RESERVED 14
RD7/AN7 13
RD6/AN6 12 ADOFF
RD5/AN5 11
10 Note 2
RD4/AN4 ADTMRH ADTMRL
Prog. Ref. B 9 Analog Timer
Prog. Ref. A 8 Mux Overflow
Temp sensor 7 ~ 1 kohm A/D Capture (OVFIF, PIR1<0>)
SREFLO 6
SREFHI 5 ADCAPH ADCAPL
Bandgap Ref. 4
RA3/AN3 3 Internal
RA2/AN2 2 Data
RA1/AN1 1 Bus
RA0/AN0 A/D
0
Capture Interrupt
(ADCIF, PIR1<1>)
4
ADCON0<7:4>
~2.5uA~5uA~10uA~20uA
ADOFF
(SLPCON<0>)
CDAC
ADCON1<7:4>
0.1F ~100
(nominal)
ADRST (ADCON0<1>)
Note 1 Note 1: All current sources are disabled if ADRST = 1
4-Bit Current DAC Note 2: Approximately 3.5 microsecond time constant

PIC14000
FIGURE 8-2: EXAMPLE A/D CONVERSION CYCLE
CAPTURE
CLK
ADTMR INCREMENTS
ADRST
ADCON0<1>
ADTMR
COUNT XX XX+1 XX+2 XX+3 XX+8 XX+9
CDAC COMPARE
ADCIF,
PIR1<1> (must be cleared by software)
Capture
Register XX XX+8
FIGURE 8-3: A/D CAPTURE TIMER (LOW BYTE)

ADTMRL b7 b6 b5 b4 b3 b2 b1 b0
POR value 00h 0 0 0 0 0 0 0 0
FIGURE 8-4: A/D CAPTURE TIMER (HIGH BYTE)

0Fh Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ADTMRH b15 b14 b13 b12 b11 b10 b9 b8
POR value 00h 0 0 0 0 0 0 0 0
FIGURE 8-5: A/D CAPTURE REGISTER (LOW BYTE)

ADCAPL b7 b6 b5 b4 b3 b2 b1 b0
POR value 00h 0 0 0 0 0 0 0 0
FIGURE 8-6: A/D CAPTURE REGISTER (HIGH BYTE)

ADCAPH b15 b14 b13 b12 b11 b10 b9 b8
POR value 00h 0 0 0 0 0 0 0 0
Legend: U= unimplemented, X = unknown.

PIC14000
8.4 A/D Comparator 8.5 Analog Mux
The PIC14000 includes a high gain comparator for A total of 16 channels are internally multiplexed to the
A/D conversions. The positive input terminal of the A/D single A/D comparator positive input. Four
comparator is connected to the output of an analog configuration bits (ADCON0<7:4>) select the channel
mux through an RC low-pass filter. The nominal to be converted. Refer to Table 8-1 for channel assign-
time-constant for the RC filter is 3.5 s. The negative ments.
input terminal is connected to the external 0.1 F (nom-
inal) ramp capacitor.
TABLE 8-1: A/D CHANNEL ASSIGNMENT
ADCON0(7:4) A/D Channel

0 0 0 0 RA0/AN0 pin
0 0 0 1 RA1/AN1 pin
0 0 1 0 RA2/AN2 pin
0 0 1 1 RA3/AN3 pin
0 1 0 0 Bandgap reference voltage
0 1 0 1 Slope reference SREFHI
0 1 1 0 Slope reference SREFLO
0 1 1 1 Internal temperature sensor
1 0 0 0 Programmable reference A output
1 0 0 1 Programmable reference B output
1 0 1 0 RD4/AN4 pin
1 0 1 1 RD5/AN5 pin
1 1 0 0 RD6/AN6 pin
1 1 0 1 RD7/AN7 pin
1 1 1 0 Reserved
1 1 1 1 Reserved

PIC14000
8.6 Programmable Current Source The programmable current source output is tied to the
CDAC pin and is used to charge an external capacitor
Four configuration bits (ADCON1<7:4>) are used to to generate the ramp voltage for the A/D comparator.
control a programmable current source for generating (Refer to Figure 8-1.) This capacitor should have a low
the ramp voltage to the A/D comparator. It allows com- voltage-coefficient as found in teflon, polypropylene, or
pensation for full-scale input voltage, clock frequency polystyrene capacitors, for optimum results. The
and CDAC capacitor tolerance variations. The current capacitor must be discharged at the beginning of each
values range from 0 to 33.75 A (nominal) in 2.25 A conversion cycle by asserting ADRST (ADCON0<1>)
increments. The intermediate values of the current for at least 200 s to allow a complete discharge.
source are as follows: Asserting ADRST disables the current sources inter-
nally. Current flow begins when ADRST is cleared.
TABLE 8-2: PROGRAMMABLE CURRENT
SOURCE SELECTION
Current Source
ADCON1<7:4>
Output
0 0 0 0 OFF - all current

sources disabled
0 0 0 1 2.25 A
0 0 1 0 4.5 A
0 0 1 1 6.75 A
0 1 0 0 9 A
0 1 0 1 11.25 A
0 1 1 0 13.5 A
0 1 1 1 15.75 A
1 0 0 0 18 A
1 0 0 1 20.25 A
1 0 1 0 22.5 A
1 0 1 1 24.75 A
1 1 0 0 27 A
1 1 0 1 29.25 A
1 1 1 0 31.5 A
1 1 1 1 33.75 A

PIC14000
8.7 A/D Control Registers
Two A/D control registers are provided on the
PIC14000 to control the conversion process. These are
ADCON0 (1Fh) and ADCON1 (9Fh). Both registers are
readable and writable.
TABLE 8-3: A/D CONTROL AND STATUS REGISTER 0

ADCON0 ADCS3 ADCS2 ADCS1 ADCS0 AMUXOE ADRST ADZERO
Read/Write R/W R/W R/W R/W U R/W R/W R/W
POR value 02h 0 0 0 0 0 0 1 0
Bit Name Function

ADCS3
ADCS2 A/D Channel Selects. Refer to Table 8-1.
B7-B4
ADCS1
ADCS0
B3 Unimplemented. Read as 0.
Analog Mux Output Enable
B2 AMUXOE 1 = Connect AMUX Output to RA0/AN0 pin (overrides TRISA<0> setting)
0 = RA0/AN0 pin normal
A/D Reset Control Bit
B1 ADRST 1 = Stop the A/D Timer, discharge CDAC capacitor
0 = Normal operation (A/D running)
A/D Zero Select Control. (Refer to Section 9.2)
B0 ADZERO 1 = Enable zeroing operation on RA1/AN1 and RD5/AN5
0 = Normal operation (sample RA1/AN1 and RD5/AN5 pins)

PIC14000
TABLE 8-4: A/D CONTROL AND STATUS REGISTER 1

ADCON1 ADDAC3 ADDAC2 ADDAC1 ADDAC0 PCFG3 PCFG2 PCFG1 PCFG0
POR value 00h 0 0 0 0 0 0 0 0
Bit Name Function

ADDAC3
ADDAC2
B7-B4 A/D Current Source Selects. Refer to Table 8-2.
ADDAC1
ADDAC0
PCFG3 PORTD Configuration Selects
B3-B2
PCFG2 (See Table 8-5)
PCFG1 PORTA Configuration Selects
B1-B0
PCFG0 (See Table 8-5)
TABLE 8-5: PORTA AND PORTD CONFIGURATION

ADCON1<1:0> RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3
ADCON1<3:2> RD4/AN4 RD5/AN5 RD6/AN6 RD7/AN7
00 A A A A
01 A A A D
10 A A D D
11 D D D D
Legend: A = Analog input, D = Digital I/O

PIC14000
8.8 A/D Speed, Resolution and Capacitor Choosing the correct ramp capacitor for the CDAC pin
Selection is required to achieve the desired resolution, conver-
sion time and full scale input voltage. The equation for
The conversion time for the A/D converter on the selecting the ramp capacitor value is:
PIC14000 can be calculated using the equation:
Capacitor = (conversion time in seconds) X
Conversion Time = (1/Fosc) x 2N (current source output in amps) / (full scale in volts)
Where Fosc is the oscillator frequency and N is the Table 8-6 provides example capacitor values for the
number of bits of resolution desired. desired A/D resolution, conversion time, and full scale
voltage measurement.
Therefore at 4MHz, the conversion time for 16 bits is
16.384 msec. Conversely, it is 256 sec for 10 bits.
TABLE 8-6: CDAC CAPACITOR SELECTION (EXAMPLES FOR FULL SCALE OF 3.5V AND 1.5V)
Calculated
A/D A/D Current CDAC CDAC Capacitor
Resolution Conversion Time Full Scale Source Output Capacitor Nearest Standard
(Bits) (Seconds) (Volts) (amps) (Farads) Value
16 0.016384 3.5 24.75 1.17E-07 .1uF

14 0.004096 3.5 24.75 2.93E-08 .022uF
12 0.001024 3.5 24.75 7.31E-09 6800pF
16 0.016384 1.5 24.75 2.73E-07 0.22F

14 0.004096 1.5 24.75 6.83E-08 68nF
12 0.001024 1.5 24.75 1.71E-08 15nF
Note: Assumes FOSC of 4 MHz.

PIC14000
9.0 OTHER ANALOG MODULES 9.2.1 ZEROING/FILTERING SWITCHES
The PIC14000 has additional analog modules for The RA1/AN1 and RA5/AN5 inputs also have a
mixed signal applications. These include: matched pair of pass gates useful for current-measure-
bandgap voltage reference ment applications. One gate is connected between the
pin and the level-shift network. The second pass gate
comparators with programmable references
is connected to ground as shown in Figure 9-1. By set-
internal temperature sensor ting the ADZERO bit (ADCON0<0>), a zero-current
voltage regulator control condition is simulated. Subsequent A/D readings are
calculated relative to this zero count from the A/D. This
9.1 Bandgap Voltage Reference zeroing of the current provides very high accuracies at
The bandgap reference circuit is used to generate a low current values where it is most needed.
1.2V nominal stable voltage reference for the A/D and For additional noise filtering or for capturing short dura-
the low-voltage detector. The bandgap reference is tion periodic pulses, an optional filter capacitor may be
channel 4 of the analog mux. The bandgap reference connected from the SUM pin to ground (this feature is
voltage is stored in the calibration space EPROM available for RA1/AN1 only). This forms an RC network
(See Table 4-2). To enable the bandgap reference with the internal 100 kohm (nominal) bias resistor to act
REFOFF (SLPCON<5>) must be cleared. as a low pass filter. The capacitor size can be adjusted
for the desired time constant.
9.2 Level-Shift Networks
A switch is included between the output from the
The RA1/AN1 and RA5/AN5 pins have an internal RA1/AN1 level-shift network and the SUM pin. This
level-shift network. A current source and resistor are switch is closed during A/D sampling periods and is
used to bias the pin voltage by about +0.5V into a range automatically opened during a zeroing operation (if
usable by the A/D converter. The nominal value of bias ADZERO = '1'). If not required in the system, this pin
current source is 5 A and the resistor is 100 kohms. should be left floating (not connected).
The level-shift function can be turned on by clearing the Setting the LSOFF bit (SLPCON<4>) disables the
LSOFF bit (SLPCON<4>) to '0'. level-shift networks, so the RA1/AN1 and RA5/AN5
pins can continue to be used as general-purpose ana-
Note: The minimum voltage permissible at the log inputs.
RA1/AN1 and RA5/AN5 pins is -0.3V. The
input protection diodes will begin to turn
on beyond -0.3V, introducing significant
errors in the A/D readings. Under no con-
ditions should the pin voltage fall below
-0.5V.

PIC14000
FIGURE 9-1: LEVEL-SHIFT NETWORKS
VDD
5 A (nominal) RA1/AN1 only
LSOFF SUM
(SLPCON<4>)
VDD
Input Protection
Diodes
External
Capacitor
(Optional)
RA1/AN1
*
RD5/AN5 100 k To A/D mux,

programmable
(nominal) reference
* comparators
ADZERO
(ADCON<0>)
LSOFF
(SLPCON<4>)
*These switches are a matched pair
9.3 Slope Reference Voltage Divider 9.4 Internal Temperature Sensor

The slope reference voltage divider circuit, consisting The internal temperature sensor is connected to the
of a buffer amplifier and resistor divider, is connected to channel 7 input of the A/D converter. The sensor volt-
the internal bandgap reference producing two other age is 1.05V nominal at 25C and its temperature coef-
voltage references called SREFHI and SREFLO (see ficient is approximately 3.7mV/C. The sensor voltage
Figure 9-2). SREFHI is nominally the same as the at 25C and the temperature coefficient values are
bandgap voltage, 1.2V, and SREFLO is nominally stored in the calibration space EPROM (See
0.13V. These reference voltages are available on two Table 4-2). To enable the temperature sensor, the
of the analog multiplexer channels. The A/D module TEMPOFF bit (SLPCON<1>) must be cleared.
and firmware can measure the SREFHI and SREFLO
voltages, and in conjunction with the KREF and KBG cal-
ibration data correct for the A/D's offset and slope
errors. See AN624 for further details.

PIC14000
FIGURE 9-2: SLOPE REFERENCE DIVIDER
ADOFF (SLPCON<0>)
VREF
+
Bandgap SREFHI
_
Reference
To A/D
MUX
REFOFF (SLPCON<5>) SREFLO
SREFLO ~ SREFHI
9
= SREFLO
KREF
SREFHI - SREFLO
9.5 Comparator and Programmable The comparator outputs are visible at either
Reference Modules RC1/CMPA or RD2/CMPB pins by setting the CMAOE
(CMCON<1>) or CMBOE (CMCON<5>) bits. Setting
9.5.1 COMPARATORS CMxOE does not affect the comparator operation. It
only enables the pin function regardless of the port
The PIC14000 includes two independent low-power TRIS register setting.
comparators for comparing the programmable refer-
Both the references and the comparators are enabled
ence outputs to either the RA1/AN1 or RA5/AN5 pins.
by clearing the CMOFF (SLPCON<2>) bit.
The negative input of each comparator is tied to one of
the reference outputs as shown in Figure 9-3. The 9.5.2 PROGRAMMABLE REFERENCES
comparator positive inputs are connected to the output
of the RA1/AN1 and RA5/AN5 level-shift networks. The PIC14000 includes two independent, programma-
At reset, the RA1/AN1 level-shift output is connected to ble voltage references. Each reference is built using
the positive inputs of both comparators. This allows a two resistor ladders, bandgap-referenced current
window comparison of the RA1/AN1 voltage using the source, and analog multiplexers. The first ladder con-
two programmable references and comparators. Set- tains 32 taps, and is divided into three ranges (upper,
ting CMBOE (CMCON<5>) changes the configuration middle, and lower) to provide a coarse voltage adjust-
so that RA1/AN1 and RA5/AN5 may be independently ment. The coarse ladder includes 1k and 10k resistors
monitored. yielding a step size of either 5 or 50 mV (nominal)
depending on the selected range. Figure 9-8 shows the
The comparator outputs can be read by the CMAOUT comparator and reference architecture.
(CMCON<2>) and CMBOUT (CMCON<6>) bits. These
are read-only bits and writes to these locations have no A second ladder contains eight taps, and is connected
effect. across the selected coarse ladder resistor to increase
resolution. This subdivides the coarse ladder step by
Either a rising or falling comparator output can gener- approximately 1/8. Thus, resolutions approaching 5/8
ate an interrupt to the CPU as controlled by the polarity mV are obtainable.
bits CPOLA (CMCON<0>) and CPOLB (CMCON<4>).
The CMIF bit (PIR1<7>) interrupt flag is set whenever
the exclusive-OR of the comparator output CMxOUT
and the CPOLx bits equal a logic one. As with other
peripheral interrupts, the corresponding enable bit
CMIE (PIE1<7>) must also be set to enable the com-
parator interrupt. In addition, the global interrupt enable
and peripheral interrupt enable bits INTCON<7:6>
must also be set. This comparator interrupt is level sen-
sitive.

PIC14000
Two registers PREFA (9Bh) and PREFB (9Ch) are The reference outputs are also connected to two inde-
used to select the reference output voltages. The pendent comparators, COMPA and COMPB. Thus, the
PREFx<7:3> bits select the output from the coarse lad- references can be used to set the comparator trip-
der, while PREFx<2:0> bits are for the fine-tune adjust- points. The A/D converter can also monitor the refer-
ment. Table 9-1 and Table 9-2 show the reference ence outputs via A/D channels 8 and 9. Refer to
decoding. Section 8 for the description of the A/D operation.
These voltages are visible at either RC0/REFA or The programmable reference output is designed to
RD3/REFB pins by setting the CMAOE (CMCON<1>) track the output from the level shift network. However,
or CMBOE (CMCON<5>) bits. Setting CMxOE does there will always be some mismatch due to component
not affect the reference voltages. It only enables the pin drift. For best accuracy, the A/D should be used to peri-
function regardless of the port TRIS register setting. odically calibrate the references to the desired
These outputs are not buffered, so they cannot directly set-point.
drive any DC loads.
FIGURE 9-3: COMPARATOR AND PROGRAMMABLE REFERENCE BLOCK DIAGRAM

(ONE OF TWO SHOWN)
CMOFF
~5 A
PREFx<7:3>
Coarse Adjust Fine Tune Adjust

~0.85V
Analog
Mux
(1 of 32) RC0/REFA or
Analog RD3/REFB
Mux
(1-of-8)
Analog
Mux PREFx<2:0>
(1 of 32)
CMxOE
~0.15V
PREFx<7:3> To A/D
Converter
Programmable
Reference
To CMxOUT bit,
_ CMCON register RC1/CMPA or
From AN1 Level RD2/CMPB
Shift Network
+
CMBOE
CPOLx
CMIF bit
From Other
From AN5 Level Comparator PIR1<7>
Shift Network
Channel B only

PIC14000
TABLE 9-1: PROGRAMMABLE REFERENCE COARSE RANGE SELECTION
Nominal
PREFx<7:3> Output Voltage
Range (V)
0 1 1 1 1 0.8000 - 0.8500
0 1 1 1 0 0.7500 - 0.8000
Upper 0 1 1 0 1 0.7000 - 0.7500

0 1 1 0 0 0.6500 - 0.7000
0 1 0 1 1 0.6000 - 0.6500
0 1 0 1 0 0.5500 - 0.6000
0 1 0 0 1 0.5450 - 0.5500
0 1 0 0 0 0.5400 - 0.5450
0 0 1 1 1 0.5350 - 0.5400
0 0 1 1 0 0.5300 - 0.5350
0 0 1 0 1 0.5250 - 0.5300
0 0 1 0 0 0.5200 - 0.5250
0 0 0 1 1 0.5150 - 0.5200
0 0 0 1 0 0.5100 - 0.5150
0 0 0 0 1 0.5050 - 0.5100
0 0 0 0 0 0.5000 - 0.5050
Middle
1 0 0 0 0 0.4950 - 0.5000
1 0 0 0 1 0.4900 - 0.4950
1 0 0 1 0 0.4850 - 0.4900
1 0 0 1 1 0.4800 - 0.4850
1 0 1 0 0 0.4750 - 0.4800
1 0 1 0 1 0.4700 - 0.4750
1 0 1 1 0 0.4650 - 0.4700
1 0 1 1 1 0.4600 - 0.4650
1 1 0 0 0 0.4550 - 0.4600
1 1 0 0 1 0.4500 - 0.4550
1 1 0 1 0 0.4000 - 0.4500
1 1 0 1 1 0.3500 - 0.4000
Lower 1 1 1 0 0 0.3000 - 0.3500
1 1 1 0 1 0.2500 - 0.3000
1 1 1 1 0 0.2000 - 0.2500
1 1 1 1 1 0.1500 - 0.2000

PIC14000
TABLE 9-2: PROGRAMMABLE
REFERENCE FINE RANGE
SELECTION
Fractional Value Of The

PREFx<2:0>
Coarse Range
0 0 0 1/8
0 0 1 1/4
0 1 0 3/8
0 1 1 1/2
1 0 0 5/8
1 0 1 3/4
1 1 0 7/8
1 1 1 1
FIGURE 9-4: PROGRAMMABLE REFERENCE TRANSFER FUNCTION
0.9 Upper Range Middle Range Lower Range
0.8
0.7
0.6
VOLTS
0.5
0.4
0.3
0.2
0.1
7F 50 4F 00 C8 D7 F8
PREFx Value (hex)

PIC14000
FIGURE 9-5: COMPARATOR CONTROL REGISTER
9Dh Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CMCON U CMBOUT CMBOE CPOLB U CMAOUT CMAOE CPOLA
Read/Write R R/W R/W R R/W R/W
POR value 00h 0 0 0 0 0 0 0 0
Bit Name Function

Comparator B Output
B6 CMBOUT Reading this bit returns the status of the comparator B output. Writes to this bit have no
effect.
Comparator B Output Enable
B5 CMBOE 1 = Comparator B output is available on RD2/CMPB pin and Reference B output is

available on RD3/REFB pin.
0 = RD2/CMPB and RD3/REFB assume normal PORTD function.
Comparator B Polarity Bit

B4 CPOLB 1 = Invert the output of comparator B.
0 = Do not invert the output of comparator B.
Comparator A Output
B2 CMAOUT Reading this bit returns the status of the comparator A output. Writes to this bit have no
effect.
Comparator A Output Enable
B1 CMAOE 1 = Comparator A output is available on RC1/CMPA pin and Reference A output is

available on RC0/REFA pin.
0 = RC0/REFA and RC1/CMPA assume normal PORTC function.
Comparator A Polarity Bit

B0 CPOLA 1 = Invert the output of comparator A.
0 = Do not invert the output of comparator A.

PIC14000
FIGURE 9-6: PREFA REGISTER
9Bh Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PREFA PRA7 PRA6 PRA5 PRA4 PRA3 PRA2 PRA1 PRA0
POR value 00h 0 0 0 0 0 0 0 0
Bit Name Function
B7-B0 PRA7
PRA6
PRA5
Programmable Reference A Voltage Select Bits.
PRA4
See Table 9-1 and Table 9-2 for decoding.
PRA3
PRA2
PRA1
PRA0
FIGURE 9-7: PREFB REGISTER

9Ch Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PREFB PRB7 PRB6 PRB5 PRB4 PRB3 PRB2 PRB1 PRB0
POR value 00h 0 0 0 0 0 0 0 0
Bit Name Function
B7-B0 PRB7
PRB6
PRB5
Programmable Reference B Voltage Select Bits.
PRB4
See Table 9-1 and Table 9-2 for decoding.
PRB3
PRB2
PRB1
PRB0

PIC14000
9.6 Voltage Regulator Output
For systems with a main supply voltage above 6V, an
inexpensive, low quiescent current voltage regulator
can be formed by connecting the VREG pin to an exter-
nal resistor and FET as shown in Figure 9-8. This cir-
cuit will provide a VDD of about 5V, after the voltage
drop across the FET.
FIGURE 9-8: VOLTAGE REGULATOR CIRCUIT
PIC14000
Main
Supply
1-10 A recommended
VREG
N-FET
(enhancement)
6V
Typical
VDD
Optional External
Voltage Regulator
(Not required for supply voltages
below 6.0 V)

PIC14000
NOTES:

PIC14000
10.0 SPECIAL FEATURES OF THE Interrupts
CPU Watchdog Timer (WDT)
SLEEP and HIBERNATE modes
What sets apart a microcontroller from other
processors are special circuits to deal with the needs of Code protection
real time applications. The PIC14000 has a host of In-circuit serial programming
such features intended to maximize system reliability, These features will be described in the following
minimize cost through elimination of external sections.
components, provide power saving operating modes
and offer code protection. These are: 10.1 Configuration Bits
OSC (oscillator) selection The configuration bits can be programmed (read as '0')
- Crystal/resonator or left unprogrammed (read as '1') to select various
- Internal oscillator device configurations. These bits are mapped in pro-
gram memory location 2007h.
Reset options
- Power-on Reset (POR) The user will note that address 2007h is beyond the
user program memory space. In fact, it belongs to the
- Power-up Timer (PWRT)
special test/configuration memory space (2000h -
- Oscillator Start-up Timer (OST) 3FFFh), which can be accessed only during program-
ming.
FIGURE 10-1: CONFIGURATION WORD
2007h Bit 13-8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BITS r CPC r CPP1 CPP0 PWRTE WDTE r FOSC
Read/Write R/W R/W Reserved R/W R/W R/W R/W Reserved R/W
Erased value 1 1 1 1 1 1 1 1 1
Bit Name Function

B13-B8 r Reserved
Calibration Space Code Protection Bit
B7 CPC 1 = Calibration space is readable and programmable
0 = Calibration space is write protected
B6 r Reserved
Program Space Code Protection Bit
B5 CPP1 1 = Program space is readable and programmable
0 = Program space is read/write protected
Program Space Code Protection Bit
B4 CPP0 1 = Program space is readable and programmable
0 = Program space is read/write protected
Power-up Timer Enable Bit
B3 PWRTE 1 = Power-up timer is disabled
0 = Power-up timer is enabled
Watchdog Timer Enable Bit
B2 WDTE 1 = WDT is enabled
0 = WDT is disabled
B1 r Reserved
Oscillator Selection Bit
B0 FOSC 1 = IN oscillator (internal)
0 = HS oscillator (crystal/resonator)

PIC14000
10.2 Oscillator Configurations By selecting IN mode OSC1/PBTN becomes a digital
input (with weak internal pull-up resistor) and can be
The PIC14000 can be operated with two different oscil- read via bit MISC<0>. Writes to this location have no
lator options. The user can program a configuration effect. The OSC1/PBTN input is capable of generating
word (CONFIG<0>) to select one of these: an interrupt to the CPU if enabled (Section 10.6). Also,
HS High Speed Crystal/Ceramic Resonator the OSC2 pin becomes a digital output for general pur-
(CONFIG<0> =0) pose use and is accessed via MISC<1>. Writes to this bit
IN Internal oscillator (CONFIG<0> =1) directly affect the OSC2 pin. Reading this bit returns the
(Default) contents of the output latch. The MISC register format is
shown in Figure 10-2.
10.2.1 INTERNAL OSCILLATOR CIRCUIT The OSC2 pin can also output the IN oscillator fre-
quency, divided-by-four, by setting INCLKEN
The PIC14000 includes an internal oscillator option
(MISC<2>).
that offers additional cost and board-space savings. No
external components are required. The nominal Note: The OSC2 output buffer provides less drive
operating frequency is 4 MHz. The frequency is mea- than standard I/O.
sured and stored into the calibration space in EPROM.
FIGURE 10-2: MISC REGISTER

MISC SMHOG SPGNDB SPGNDA I2CSEL SMBUS INCLKEN OSC2 OSC1
Read/Write R/W R/W R/W R/W R/W R/W R/W R
POR value 00h 0 0 0 0 0 0 0 X
Bit Name Function
SMHOG enable
1 = Stretch I2C CLK signal (hold low) when receive data buffer is full (refer to
B7 SMHOG Section 7.5.4). For pausing I2C transfers while preventing interruptions of A/D
conversions.
0 = Disable I2C CLK stretch.
B6 SPGNDB 1 = PORTD<1:0> ground reference is the RD5/AN5 pin.
0 = PORTD<1:0> ground reference is VSS.
B5 SPGNDA 1 = PORTC<7:6> ground reference is the RA1/AN1 pin.
0 = PORTC<7:6> ground reference is VSS.
I2C Port select Bit.
B4 I2CSEL 1 = PORTD<1:0> are used as the I2C clock and data lines.
0 = PORTC<7:6> are used as the I2C clock and data lines.
SMBus-Compatibility Select
1 = SMBus compatibility mode is enabled. PORTC<7:6> and PORTD<1:0> have
B3 SMBus SMBus-compatible input thresholds.
0 = SMBus-compatibility is disabled. PORTC<7:6> and PORTD<1:0> have Schmitt Trig-
ger input thresholds.
Oscillator Output Select (available in IN mode only).
B2 INCLKEN 1 = Output IN oscillator signal divided by four on OSC2 pin.
0 = Disconnect IN oscillator signal from OSC2 pin.
OSC2 output port bit (available in IN mode only).
B1 OSC2 Writes to this location affect the OSC2 pin in IN mode. Reads return the value of the
output latch.
OSC1 input port bit (available in IN mode only).
B0 OSC1 Reads from this location return the status of the OSC1 pin in IN mode. Writes have no
effect.

PIC14000
10.2.2 CRYSTAL OSCILLATOR/CERAMIC TABLE 10-2: CAPACITOR SELECTION
RESONATOR FOR CRYSTAL OSCILLATOR
In HS mode, a crystal or ceramic resonator is con- Mode Freq C1 C2
nected to the OSC1 and OSC2 pins to establish oscil-
lation. A parallel cut crystal is required. Use of a series HS 4 MHz 15 - 33 pF 15 - 33 pF
cut crystal may give a frequency outside of the crystal 8 MHz 15 - 47 pF 15 - 47 pF
manufacturers specifications. When in HS mode, the 20 MHz 15 - 47 pF 15 - 47 pF
device can have an external clock source to drive the Note : Higher capacitance increases the stability of
OSC1 pin. oscillator but also increases the start-up time.
These values are for design guidance only. Rs may
FIGURE 10-3: CRYSTAL/CERAMIC be required in HS mode to avoid overdriving
RESONATOR OPERATION crystals with low drive level specification. Since
each crystal has its own characteristics, the user
(HS OSC CONFIGURATION)
should consult the crystal manufacturer for
OSC1 appropriate values of external components.
For VDD > 4.5V, C1 = C2 30pf is recommended.
C1 To internal
logic
10.2.3 EXTERNAL CRYSTAL OSCILLATOR
XTAL SLEEP
RF CIRCUIT
SLPCON<3>
OSC2
RS Either a prepackaged oscillator can be used or a simple
C2 Note1 PIC14000 oscillator circuit with TTL gates can be built.
Prepackaged oscillators provide a wide operating
See Table 10-1 and Table 10-2 for recommended range and better stability. A well-designed crystal
values of C1 and C2. oscillator will provide good performance with TTL
Note 1: A series resistor may be required for AT gates. Two types of crystal oscillator circuits can be
strip cut crystals. used; one with series resonance, or one with parallel
resonance.
FIGURE 10-4: EXTERNAL CLOCK INPUT Figure 10-5 shows implementation of a parallel
OPERATION (HS OSC resonant oscillator circuit. The circuit is designed to use
CONFIGURATION) the fundamental frequency of the crystal. The 74AS04
inverter performs the 180-degree phase shift that a
parallel oscillator requires. The 4.7 k resistor provides
Clock from OSC1 the negative feedback for stability. The 10 k
ext. system potentiometer biases the 74AS04 in the linear region.
PIC14000
Open OSC2 This could be used for external oscillator designs.
FIGURE 10-5: EXTERNAL PARALLEL
RESONANT CRYSTAL
TABLE 10-1: CERAMIC RESONATORS OSCILLATOR CIRCUIT
Mode Freq C1 C2 +5V
To Other
HS 4 MHz 15 - 68 pF 15 - 68 pF Devices
8 MHz 10 - 68 pF 10 - 68 pF 10k
4.7k 74AS04
16 MHz 10 - 22 pF 10 - 22 pF
Note : Recommended values of C1 and C2 are identical to 74AS04 OSC1
the ranges tested table.
Higher capacitance increases the stability of
oscillator but also increases the start-up time. 10k
These values are for design guidance only. Since XTAL
each resonator has its own characteristics, the user
should consult the resonator manufacturer for 10k
appropriate values of external components.
Resonators Used: 20pF 20pF
4 MHz Murata Erie CSA4.00MG +/-.5%

8 MHz Murata Erie CSA8.00MT +/-.5%
16 MHz Murata Erie CSA16.00MX +/-.5%
All resonators used did not have built-in capacitors.

PIC14000
Figure 10-6 shows a series resonant oscillator circuit. 10.3 Reset
This circuit is also designed to use the fundamental
The PIC14000 differentiates between various kinds of
frequency of the crystal. The inverter performs a
reset:
180-degree phase shift in a series resonant oscillator
circuit. The 330 k resistors provide the negative Power-on Reset (POR)
feedback to bias the inverters in their linear region. MCLR Reset during normal operation
MCLR Reset during SLEEP
FIGURE 10-6: EXTERNAL SERIES
RESONANT CRYSTAL WDT Reset (normal operation)
OSCILLATOR CIRCUIT Some registers are not affected in any reset condition;
their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a reset
To Other state on Power-on Reset (POR), on the MCLR and
330k 330k Devices
PIC14000 WDT Reset, and on MCLR Reset during SLEEP. They
74AS04 74AS04 74AS04 are not affected by a WDT Wake-up, which is viewed
OSC1 as the resumption of normal operation. The TO and PD
0.1F bits are set or cleared differently in different reset situ-
XTAL
ations as indicated in Table 10-3. These bits are used
in software to determine the nature of the reset. See
Table 10-5 for a full description of reset states of all reg-
isters.
A simplified block diagram of the on-chip reset circuit is
The devices all have a MCLR noise filter in the MCLR
reset path. The filter will detect and ignore small pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
FIGURE 10-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External
Reset
MCLR
SLEEP
WDT WDT
Module Time-out
VDD rise
detect
Power-on Reset
VDD
OST/PWRT
OST
Chip_Reset
10-bit Ripple counter R Q
OSC1
PWRT
On-chip(1)
RC OSC 10-bit Ripple counter
Note 1: This is a separate oscillator from the RC

oscillator of the CLKIN pin. Enable PWRT
Enable OST

PIC14000
TABLE 10-3: STATUS BITS AND THEIR SIGNIFICANCE
POR TO PD Meaning
0 1 1 Power-On Reset
0 0 X Illegal, TO is set on POR
0 X 0 Illegal, PD is set on POR
1 0 1 WDT reset during normal operation
1 0 0 WDT time-out wakeup from sleep
1 1 1 MCLR reset during normal operation
1 1 0 MCLR reset during SLEEP or HIBERNATE, or interrupt wake-up from
SLEEP or HIBERNATE.
10.4 Low-Voltage Detector 10.5.2 POWER-UP TIMER (PWRT)
The PIC14000 contains an integrated low-voltage The Power-up Timer provides a fixed 72 ms (nominal)
detector. The supply voltage is divided and compared time-out on power-up only, from POR. The power-up
to the bandgap reference output. If the supply voltage timer operates from a local internal oscillator. The chip
(VDD) falls below VTRIP-, then the low-voltage detector is kept in reset as long as PWRT is active. The PWRT
will cause LVD (PCON<0>) to be reset. This bit can be delay allows the VDD to rise to an acceptable level. A
read by software to determine if a low voltage condition configuration bit, PWRTE, can disable (if set, or unpro-
occurred. This bit must be set by software. grammed) or enable (if cleared, or programmed) the
power-up timer.
The nominal values of the low-voltage detector trip
points are as follows: The power-up timer delay will vary from chip to chip
and due to VDD and temperature.
VTRIP- = 2.55V
VTRIP+ = 2.60V 10.5.3 OSCILLATOR START-UP TIMER (OST)
Hysteresis (VTRIP+ VTRIP-) = 55 mV
The Oscillator Start-up Timer (OST) provides 1024
10.5 Power-on Reset (POR), Power-up oscillator cycles (from OSC1 input) delay after the
Timer (PWRT) and Oscillator Start-up PWRT delay is over. This guarantees that the crystal
Timer (OST) oscillator or resonator has started and stabilized.
10.5.1 POWER-ON RESET (POR) 10.5.4 IN OSCILLATOR START-UP
A Power-on Reset pulse is generated on-chip when There is an 8-cycle delay in IN mode to ensure stability
VDD rise is detected (in the range of 1.5V - 2.1V). To only after a Power-on Reset (POR) or wake-up from
take advantage of the POR, just tie the MCLR pin SLEEP.
directly (or through a resistor) to VDD. This will elimi-
nate external RC components usually needed to create
a Power-on Reset. A maximum rise time for VDD is
specified. See Electrical Specifications for details.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating conditions are
met.
For additional information, refer to Application Note
AN607, Power-up Trouble Shooting.

PIC14000
10.5.5 TIMEOUT SEQUENCE FIGURE 10-8: EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
On power-up the time-out sequence is as follows: First
VDD POWER-UP)
the PWRT time-out is invoked after POR has expired.
The OST is activated only in HS (crystal oscillator)
VDD VDD
mode. The total time-out will vary based on the oscilla-
tor configuration and PWRTE status. For example, in
IN mode, with PWRTE unprogrammed (PWRT dis- D R
abled), there will be no time-out delay at all.
R1
Figure 13-4 depicts the power-on reset time-out MCLR
sequences.
C
Table 10-4 shows the reset conditions for some special PIC14000
registers, while Table 10-5 shows the reset conditions
for all registers. 1. External power-on reset circuit is required
only if VDD power-up slope is too slow. The
diode D helps discharge the capacitor
quickly when VDD powers down.
2. R < 40 K is recommended to make sure
that voltage drop across R does not exceed
0.2V (max leakage current spec on MCLR
pin is 5 A). A larger voltage drop will
degrade VIH level on MCLR pin.
3. R1 = 100 to 1 K will limit any current
flowing into MCLR from external capacitor C
in the event of MCLR pin breakdown due to
ESD or EOS.
TABLE 10-4: RESET CONDITION FOR SPECIAL REGISTERS
Condition PCL STATUS PCON

Addr: 02h Addr: 03h Addr: 8Eh
Power-on Reset 000h 0001 1xxx 0--- --0x
MCLR reset during normal operation 000h 0001 1uuu u--- --ux
MCLR reset during SLEEP 000h 0001 0uuu u--- --ux
WDT reset during normal operation 000h 0000 1uuu u--- --ux
WDT during SLEEP PC + 1 uuu0 0uuu u--- --ux
Interrupt wake-up from SLEEP PC + 1(1) uuu1 0uuu u--- --ux
Legend: u = unchanged
x = unknown
- = unimplemented, read as 0
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).

PIC14000
TABLE 10-5: RESET CONDITIONS FOR REGISTERS
MCLR reset during

Wake-up from SLEEP
- normal operation
through interrupt
- SLEEP
Wake up from SLEEP
WDT time-out during
through WDT time-out
Register Address Power-on Reset normal operation
W - xxxx xxxx uuuu uuuu uuuu uuuu
INDF 00h/80h - - -
TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu
PCL 02h/82h 0000h 0000h PC + 1(2)
STATUS 03h/83h 0001 1xxx 000? ?uuu(3) uuu? ?uuu(3)
FSR 04h/84h xxxx xxxx uuuu uuuu uuuu uuuu
PORTA 05h ---- xxxx ---- uuuu ---- uuuu
PORTC 07h xxxx xxxx uuuu uuuu uuuu uuuu
PORTD 08h xxxx xxxx uuuu uuuu uuuu uuuu
PCLATH 0Ah/8Ah ---0 0000 ---0 0000 ---u uuuu
INTCON 0Bh/8Bh 0000 000x 0000 000u uuuu uuuu(1)
PIR1 0Ch 0000 0000 0000 0000 uuuu uuuu(1)
ADTMRL 0Eh 0000 0000 0000 0000 uuuu uuuu
ADTMRH 0Fh 0000 0000 0000 0000 uuuu uuuu
I2CBUF 13h xxxx xxxx uuuu uuuu uuuu uuuu
I2CCON 14h 0000 0000 0000 0000 uuuu uuuu
ADCAPL 15h 0000 0000 0000 0000 uuuu uuuu
ADCAPH 16h 0000 0000 0000 0000 uuuu uuuu
ADCON0 1Fh 0000 0010 0000 0010 uuuu uuuu
OPTION 81h 1111 1111 1111 1111 uuuu uuuu
TRISA 85h ---- 1111 ---- 1111 ---- uuuu
TRISC 87h 1111 1111 1111 1111 uuuu uuuu
TRISD 88h 1111 1111 1111 1111 uuuu uuuu
PIE1 8Ch 0000 0000 0000 0000 uuuu uuuu
PCON 8Eh ---- --0x ---- --uu ---- --uu
SLPCON 8Fh 0011 1111 0011 1111 uuuu uuuu
I2CADD 93h 0000 0000 0000 0000 uuuu uuuu
I2CSTAT 94h --00 0000 --00 0000 --uu uuuu
PREFA 9Bh 0000 0000 0000 0000 uuuu uuuu
PREFB 9Ch 0000 0000 0000 0000 uuuu uuuu
CMCON 9Dh 0x00 0x00 0x00 0x00 uuuu uuuu
MISC 9Eh 0000 000x 0000 000x uuuu uuuu
ADCON1 9Fh 0000 0000 0000 0000 uuuu uuuu
Legend: u=unchanged, x =unknown, - = unimplemented, reads as 0, ? = value depends on condition.
Note 1: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 10-4 for reset value for specific condition.

PIC14000
10.6 Interrupts The return from interrupt instruction, RETFIE, exits the
interrupt routine as well as sets the GIE bit to re-enable
The PIC14000 has several sources of interrupt: interrupts.
External interrupt from OSC1/PBTN pin Note 1: The individual interrupt flags will be set by
I2C port interrupt the specified condition even though the
PORTC interrupt on change (pins RC<7:4> only) corresponding interrupt enable bit is
Timer0 overflow cleared (interrupt disabled) or the GIE bit is
cleared (all interrupts disabled).
A/D timer overflow
A/D converter capture event Note 2: If an interrupt occurs while the Global
Interrupt Enable (GIE) bit is being cleared,
Programmable reference comparator interrupt
the GIE bit may unintentionally be
This section addresses the external and Timer0 re-enabled by the users Interrupt Service
interrupts only. Refer to the appropriate sections for Routine (the RETFIE instruction). The
description of the serial port, programmable reference events that would cause this to occur are:
and A/D interrupts.
1. An instruction clears the GIE bit while an
INTCON records individual interrupt requests in flag interrupt is acknowledged.
bits. It also has individual and global enable bits. The 2. The program branches to the interrupt vector
peripheral interrupt flags reside in the PIR1 register. and executes the Interrupt Service Routine.
Peripheral interrupt enable interrupts are contained in
3. The interrupt service routine completes with the
the PIE1 register.
execution of the RETFIE instruction. This causes
Global interrupt masking is controlled by GIE the GIE bit to be set (enables interrupts), and the
(INTCON<7>). Individual interrupts can be disabled program returns to the instruction after the one
through their corresponding mask bit in the INTCON which was meant to disable interrupts.
register. GIE is cleared on reset to mask interrupts.
The method to ensure that interrupts are globally
When an interrupt is serviced, the GIE is cleared to disabled is:
disable any further interrupt, the return address is
1. Ensure that the GIE bit was cleared by the
pushed onto the stack and the PC is loaded with
instruction, as shown in the following code:
0004h, the interrupt vector. For external interrupt
LOOP: BCF INTCON,GIE ; Disable Global Interrupts
events, such as the I2C interrupt, the interrupt latency BTFSC INTCON,GIE ; Global Interrupts Disabled?
will be 3 or 4 instruction cycles. The exact latency GOTO LOOP ; No, try again
depends when the interrupt event occurs. The latency : ; Yes, continue with program
; flow
is the same for 1 or 2 cycle instructions. Once in the
interrupt service routine the source(s) of the interrupt
can be determined by polling the interrupt flag bits. The
interrupt flag bit(s) must be cleared in software before
re-enabling interrupts to avoid infinite interrupt
requests. Individual interrupt flag bits are set
regardless of the status of their corresponding mask bit
or the GIE bit to allow polling.
FIGURE 10-9: INTERRUPT LOGIC SCHEMATIC
PBIF
PBIE
ADCIF
ADCIE
Wake-up (If in SLEEP mode)
T0IF or terminate long write
I2CIF
T0IE
I2CIE
PEIF
PEIE Interrupt to CPU
OVFIF
OVFIE GIE
CMIF
CMIE
RCIF
RCIE

PIC14000
10.6.1 EXTERNAL INTERRUPT ware in the interrupt service routine before re-enabling
the interrupt. This interrupt can wake up the processor
An external interrupt can be generated via the from SLEEP if PBIE bit is set (interrupt enabled) prior
OSC1/PBTN pin if IN (internal oscillator) mode is to going into SLEEP mode. The status of the GIE bit
enabled. This interrupt is falling edge triggered. When determines whether or not the processor branches to
a valid edge appears on OSC1/PBTN pin, PBIF the interrupt vector following wake-up. The timing of the
(PIR1<4>) is set. This interrupt can be disabled by external interrupt is shown in Figure 10-10.
clearing PBIE (PIE1<4>). PBIF must be cleared in soft-
FIGURE 10-10: EXTERNAL (OSC1/PBTN) INTERRUPT TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
INTERNAL
OSC
CLKOUT(3)
4
PBTN pin
1
1
PBIF flag 5 Interrupt Latency
(PIR<4>)
(Note 2)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC PC PC+1 PC+1 0004h 0005h
Instruction
fetched Inst (PC) Inst (PC+1) Inst (0004h) Inst (0005h)
Instruction Inst (PC-1) Inst (PC) Dummy Cycle Dummy Cycle Inst (0004h)
executed
Notes:
1. PBIF flag is sampled here (every Q1)
2. Interrupt latency = 3-4Tcy where Tcy = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3. Available only in IN oscillator mode on OSC2.
4. For minimum width spec of PBTN pulse, refer to AC specs.
5. PBIF is enabled to be set anytime during the Q4-Q1 cycles.

PIC14000
10.6.2 TIMER0 INTERRUPT 10.6.4 CONTEXT SWITCHING DURING
INTERRUPTS
An overflow (FFh 00h) in Timer0 will set the T0IF
(INTCON<2>) flag. Setting T0IE (INTCON<5>) During an interrupt, only the return PC value is saved
enables the interrupt. on the stack. Typically, users may wish to save key
registers during an interrupt, for example, W register
10.6.3 PORTC INTERRUPT ON CHANGE and Status register. Example 10-1 is an example that
shows saving registers in RAM.
An input change on PORTC<7:4> sets RCIF
(PIR1<2>). Setting RCIE (PIE1<2>) enables the inter-
rupt. For operation of PORTC, refer to Section 5.2.
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RCIF
interrupt flag may not be set.
EXAMPLE 10-1: SAVING STATUS AND W REGISTERS IN RAM

MOVWF W_TEMP ;Copy W to TEMP register, could be any bank
SWAPF STATUS,W ;Swap status to be saved into W
BCF STATUS,RP1 ;Change to bank zero, regardless of current bank
BCF STATUS,RP0 ;
MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register
:
:(ISR)
:
SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W
;(sets bank to original state)
MOVWF STATUS ;Move W into STATUS register
SWAPF W_TEMP,F ;Swap W_TEMP
SWAPF W_TEMP,W ;Swap W_TEMP into W

PIC14000
10.7 Watchdog Timer (WDT) The WDT can be permanently disabled by
programming the configuration bit WDTE as a 0. Its
The watchdog timer is realized as a free running oscillator can be shut down to conserve battery power
on-chip RC oscillator which does not require any by entering HIBERNATE Mode. Refer to
external components. This RC oscillator is separate Section 10.8.3 for more information on HIBERNATE
from the IN oscillator used to generate the CPU and mode.
A/D clocks. That means that the WDT will run even if
the clock has been stopped, for example, by execution CAUTION: Beware of disabling WDT if software
of a SLEEP instruction. Refer to Section 10.8.1 for more routines require exiting based on WDT
information. reset. For example, the MCU will not
exit HIBERNATE mode based on WDT
During normal operation, a WDT time-out generates a reset.
device RESET. If the device is in SLEEP mode, a WDT
time-out causes the device to wake-up and continue A block diagram of the watchdog timer is shown in
with normal operation. Figure 10-11. It should be noted that a RESET
generated by the WDT time-out does not drive MCLR
low.
FIGURE 10-11: WATCHDOG TIMER BLOCK DIAGRAM (WITH TIMER0)
Timer0
Data bus
FOSC/4 0
PSout 8
1
Sync with
1 Internal TMR0
clocks
RC3/T0CKI 0 PSout
pin Set T0IF
T0SE (2 cycle delay)
Interrupt on
Overflow
PSA
T0CS
Prescaler/
Postscaler
Local
Oscillator 0 8-bit Counter
18 mS 8
Timer 1
3
8-to-1 MUX PS2:PS0
PSA
Enable 1 0 PSA
WDT
Watchdog Timer Time-out
WDT Note: T0CS, T0SE, PSA, PS2:PS0 correspond to (OPTION<5:0>).

HIBERNATE Enable Bit

PIC14000
10.7.1 WDT PERIOD 10.7.2 WDT PROGRAMMING CONSIDERATIONS
The WDT has a nominal time-out period of 18 ms (with It should also be taken into account that under
no prescaler). The time-out periods vary with worst-case conditions (minimum VDD, maximum
temperature, VDD and process variations (see DC temperature, maximum WDT prescaler) it may take
specs). If longer time-out periods are desired, a pres- several seconds before a WDT time-out occurs. Refer
caler with a division ratio of up to 1:128 can be to Section 6.3 for prescaler switching considerations.
assigned to the WDT under software control by writing
to the OPTION registers. Thus, time-out periods up to 10.8 Power Management Options
2.3 seconds can be realized. The CLRWDT and SLEEP
The PIC14000 has several power management
instructions clear the WDT and the prescaler, if
options to prolong battery lifetime. The SLEEP instruc-
assigned to the WDT, and prevent it from timing out and
tion halts the CPU and can turn off the on-chip oscilla-
generating a device RESET.
tors. The CPU can be in SLEEP mode, yet the A/D
The TO bit in the status register will be cleared upon a converter can continue to run. Several bits are included
watchdog timer time-out. The WDT time-out period (no in the SLPCON register (8Fh) to control power to ana-
prescaler) is measured and stored in calibration space log modules.
at location 0FD2h.
TABLE 10-6: SUMMARY OF POWER MANAGEMENT OPTIONS
Function Summary
CPU Clock OFF during SLEEP/HIBERNATE mode, ON otherwise

Main Oscillator ON if NOT in SLEEP mode. In SLEEP mode, controlled by OSCOFF
bit, SLPCON<3>.
Watchdog Timer Controlled by WDTE, 2007h<2> and HIBEN, SLPCON<7>
Temperature Sensor Controlled by TEMPOFF, SLPCON<1>
Low-voltage Detector Controlled by REFOFF, SLPCON<5>
Comparator and Controlled by CMOFF, SLPCON<2>
Programmable References
A/D Comparator Controlled by ADOFF, SLPCON<0>
Programmable Current Source Controlled by ADOFF, SLPCON<0> and ADCON1<7:4>
Slope Reference Voltage Divider Controlled by ADOFF, SLPCON<0>
Level Shift Networks Controlled by LSOFF, SLPCON<4>
Bandgap Reference Controlled by REFOFF, SLPCON<5>
Voltage Regulator Control Always ON. Does not consume power if unconnected.
Power On Reset Always ON, except in SLEEP/HIBERNATE mode
Note: Refer to analog specs for individual peripheral operating currents.

PIC14000
10.8.1 SLEEP MODE An external reset on MCLR pin causes a device reset.
The other wake-up events are considered a
The SLEEP mode is entered by executing a SLEEP continuation of program execution. The TO and PD bits
instruction. in the STATUS register can be used to determine the
If SLEEP mode is enabled, the WDT will be cleared but cause of device reset. The PD bit, which is set on
keep running. The PD bit in the STATUS register is power-up is cleared when SLEEP is invoked. The TO
cleared, the TO bit is set, and on-chip oscillators are bit is cleared if a WDT time-out occurred (and caused
shut off, except the WDT RC oscillator, which continues a wake-up).
to run. The I/O ports maintain the status they had When the SLEEP instruction is being executed, the next
before the SLEEP command was executed (driving instruction (PC + 1) is pre-fetched. For the device to
high, low, or high-impedance). wake-up through an interrupt event, the corresponding
It is an option while in SLEEP mode to leave the interrupt enable bit must be set. Wake-up occurs
on-chip oscillator running. This option allows an A/D regardless of the state of bit GIE. If bit GIE is clear, the
conversion to continue while the CPU is in SLEEP device continues execution at the instruction after the
mode. The CPU clocks are stopped in this condition to SLEEP instruction. If bit GIE is set, the device executes
preserve power. The operation of the on-chip oscillator the instruction after the SLEEP instruction and then
during SLEEP is controlled by OSCOFF branches to the interrupt address (0004h). In cases
(SLPCON<3>). Clearing this bit to 0 allows the oscil- where the execution of the instruction following SLEEP
lator to continue to run. This bit is only active in SLEEP is not desirable, the user should have a NOP after the
mode. SLEEP instruction.
For lowest power consumption in this mode, all I/O pins The WDT is cleared when the device wakes-up from
should be either at VDD or VSS with no external circuitry sleep, regardless of the source of wake-up.
drawing current from the I/O pin. I/O pins that are Note: If the global interrupts are disabled (GIE is
high-impedance inputs should be pulled high or low cleared), but any interrupt source has both
externally to avoid leakage currents caused by floating its interrupt enable bit and the
inputs. The MCLR pin must be at a logic high level corresponding interrupt flag bits set, the
(VIH). The contribution from any on-chip pull-up device will immediately wake from SLEEP.
resistors should be considered.
10.8.3 HIBERNATE MODE
10.8.2 WAKE-UP FROM SLEEP
HIBERNATE mode is an extension of SLEEP mode
The PIC14000 can wake up from SLEEP through one with the following additions.
of the following events:
WDT is forced off
1. External reset input on MCLR pin
Weak pull-ups on RC<5:0> are disabled
2. Watchdog Timer time-out (if WDT is enabled)
Some input buffers are gated-off (refer to
3. Interrupt from OSC1/PBTN pin Section 5.0)
4. RC<7:4> port change
The HIBERNATE mode is entered by executing a
5. I2C (serial port) start/stop bit detect interrupt. SLEEP instruction with HIBEN (SLPCON<7>) bit set.
6. Wake-up on programmable reference compara-
The PIC14000 wakes up from HIBERNATE mode via
tor interrupt.
all the same mechanisms as SLEEP mode, except for
7. A/D conversion complete (comparator trip) inter- WDT time-out. HIBERNATE mode allows power con-
rupt. sumption to be reduced to a minimum.
8. A/D timer overflow interrupt.

PIC14000
FIGURE 10-12: SLPCON REGISTER

SLPCON HIBEN REFOFF LSOFF OSCOFF CMOFF TEMPOFF ADOFF
Read/Write R/W U R/W R/W R/W R/W R/W R/W
POR value 3Fh 0 0 1 1 1 1 1 1
Bit Name Function

Hibernate Mode Select
B7 HIBEN 1 = Hibernate mode enable
0 = Normal operating mode
B6 Unimplemented. Read as 0
References Power Control (bandgap reference, low voltage detector,
bias generator)
B5 REFOFF
1 = The references are off
0 = The references are on
Level Shift Network Power Control
1 = The level shift network is off. The RA1/AN1, RD5/AN5 inputs can continue to
B4 LSOFF function as either analog or digital.
0 = The level shift network is on. The signals at the RA1/AN1, RD5/AN5 inputs are
level shifted by approximately 0.5V.
Main Oscillator Power Control
1 = The main oscillator is disabled during SLEEP mode
B3 OSCOFF
0 = The main oscillator is running during SLEEP mode for A/D conversions to
continue
Programmable Reference and Comparator Power Control
B2 CMOFF 1 = The programmable reference and comparator circuits are off
0 = The programmable reference and comparator circuits are on
On-chip Temperature Sensor Power Control
B1 TEMPOFF 1 = The temperature sensor is off
0 = The temperature sensor is on
A/D Module Power Control (comparator, programmable current source,
slope reference voltage divider)
B0 ADOFF
1 = The A/D module power is off
0 = The A/D module power is on

PIC14000
FIGURE 10-13: WAKE-UP FROM SLEEP AND HIBERNATE THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4) TOST(2)
INTERRUPT
Interrupt Latency
Flag (5)
(Note 2)
GIE bit Processor in
(INTCON<7>)
SLEEP
INSTRUCTION FLOW
PC PC PC+1 PC+2 PC + 2 0004h 0005h
Instruction Inst(0004h)
fetched Inst(PC) = SLEEP Inst(PC + 1) Inst(PC + 2) Inst(0005h)
Instruction SLEEP Inst(PC + 1) Dummy cycle Dummy cycle
executed Inst(PC - 1) Inst(0004h)
Note 1: HS oscillator mode assumed.

2: TOST = 1024 TOSC (drawing not to scale). This delay will be 8 TOSC for IN osc mode.
3: GIE = 1 assumed. In this case after wake up processor jumps to interrupt routine. If GIE = 0, execution will continue in line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
5: Refer to Section 10.8 for sources.
10.9 Code Protection After reset, to place the device into programming/verify
mode, the program counter (PC) is at location 00h. A
The code in the program memory can be protected by 6-bit command is then supplied to the device.
programming the code protect bits. When code Depending on the command, 14-bits of program data
protected, the contents of the program memory cannot are then supplied to or from the device. For complete
be read out. In code-protected mode, the configuration details about serial programming, please refer to the
word (2007h) will not be scrambled, allowing reading of PIC16C6X/7X Programming Specifications (Literature
all configuration bits. #DS30228).
10.10 In-Circuit Serial Programming A typical in-system serial programming connection is
PIC14000 can be serially programmed while in the end
application circuit. This is simply done with two lines for FIGURE 10-14: TYPICAL IN-SYSTEM SERIAL
clock and data, and three other lines for power, ground PROGRAMMING
and the programming voltage. This allows customers to CONNECTION
manufacture boards with unprogrammed devices, and
then program the microcontroller just before shipping
the product. This allows the most recent firmware or a To Normal
Connections
custom firmware to be programmed. External
Connector PIC14000
The device is placed into a program/verify mode by Signals
holding the RC6/SCL and RC7/SDA pins low while
+5V VDD
raising the MCLR (VPP) pin from VIL to VIH. RC6 then
becomes the programming clock and RC7 becomes 0V VSS
the programmed data. Both RC6 and RC7 are Schmitt Vpp MCLR/VPP
trigger inputs in this mode.
CLK RC6
Data I/O RC7
VDD
To Normal
Connections

PIC14000
NOTES:

PIC14000
11.0 INSTRUCTION SET SUMMARY The instruction set is highly orthogonal and is grouped
into three basic categories:
The PIC14000s instruction set is the same as
PIC16CXX. Each instruction is a 14-bit word divided Byte-oriented operations
into an OPCODE which specifies the instruction type Bit-oriented operations
and one or more operands which further specify the Literal and control operations
operation of the instruction. The instruction set sum-
All instructions are executed within one single instruc-
mary in Table 11-2 lists byte-oriented, bit-oriented, and
tion cycle, unless a conditional test is true or the pro-
literal and control operations. Table 11-1 shows the
gram counter is changed as a result of an instruction.
opcode field descriptions.
In this case, the execution takes two instruction cycles
For byte-oriented instructions, 'f' represents a file reg- with the second cycle executed as a NOP. One instruc-
ister designator and 'd' represents a destination desig- tion cycle consists of four oscillator periods. Thus, for
nator. The file register designator specifies which file an oscillator frequency of 4 MHz, the normal instruction
register is to be used by the instruction. execution time is 1 s. If a conditional test is true or the
The destination designator specifies where the result of program counter is changed as a result of an instruc-
the operation is to be placed. If 'd' is zero, the result is tion, the instruction execution time is 2 s.
placed in the W register. If 'd' is one, the result is placed Table 11-2 lists the instructions recognized by the
in the file register specified in the instruction. MPASM assembler.
For bit-oriented instructions, 'b' represents a bit field Figure 11-1 shows the three general formats that the
designator which selects the number of the bit affected instructions can have.
by the operation, while 'f' represents the number of the
file in which the bit is located. Note: To maintain upward compatibility with
future PIC16CXX products, do not use the
For literal and control operations, 'k' represents an OPTION and TRIS instructions.
eight or eleven bit constant or literal value.
All examples use the following format to represent a
TABLE 11-1: OPCODE FIELD hexadecimal number:
DESCRIPTIONS 0xhh
Field Description where h signifies a hexadecimal digit.
f Register file address (0x00 to 0x7F) FIGURE 11-1: GENERAL FORMAT FOR
W Working register (accumulator) INSTRUCTIONS
b Bit address within an 8-bit file register
Byte-oriented file register operations
k Literal field, constant data or label
13 8 7 6 0
x Don't care location (= 0 or 1)
OPCODE d f (FILE #)
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all d = 0 for destination W
Microchip software tools. d = 1 for destination f
d Destination select; d = 0: store result in W, f = 7-bit file register address
d = 1: store result in file register f.
Default is d = 1 Bit-oriented file register operations
label Label name 13 10 9 7 6 0
TOS Top of Stack OPCODE b (BIT #) f (FILE #)
PC Program Counter
b = 3-bit bit address
PCLATH Program Counter High Latch
f = 7-bit file register address
GIE Global Interrupt Enable bit
WDT Watchdog Timer/Counter Literal and control operations
TO Time-out bit
PD Power-down bit General
dest Destination either the W register or the specified 13 8 7 0
register file location OPCODE k (literal)
[ ] Options
k = 8-bit immediate value
( ) Contents
Assigned to
CALL and GOTO instructions only
<> Register bit field
13 11 10 0
In the set of
OPCODE k (literal)
italics User defined term (font is courier)
k = 11-bit immediate value

PIC14000
TABLE 11-2: PIC14000 INSTRUCTION SET
Mnemonic, Description Cycles 14-Bit Opcode Status Notes
Operands Affected
MSb LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF f, d Add W and f 1 00 0111 dfff ffff C,DC,Z 1,2
ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1,2
CLRF f Clear f 1 00 0001 lfff ffff Z 2
CLRW - Clear W 1 00 0001 0xxx xxxx Z
COMF f, d Complement f 1 00 1001 dfff ffff Z 1,2
DECF f, d Decrement f 1 00 0011 dfff ffff Z 1,2
DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1,2,3
INCF f, d Increment f 1 00 1010 dfff ffff Z 1,2
INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1,2,3
IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1,2
MOVF f, d Move f 1 00 1000 dfff ffff Z 1,2
MOVWF f Move W to f 1 00 0000 lfff ffff
NOP - No Operation 1 00 0000 0xx0 0000
RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1,2
RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1,2
SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C,DC,Z 1,2
SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1,2
XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF f, b Bit Clear f 1 01 00bb bfff ffff 1,2
BSF f, b Bit Set f 1 01 01bb bfff ffff 1,2
BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3
BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3
LITERAL AND CONTROL OPERATIONS
ADDLW k Add literal and W 1 11 111x kkkk kkkk C,DC,Z
ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z
CALL k Call subroutine 2 10 0kkk kkkk kkkk
CLRWDT - Clear Watchdog Timer 1 00 0000 0110 0100 TO,PD
GOTO k Go to address 2 10 1kkk kkkk kkkk
IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z
MOVLW k Move literal to W 1 11 00xx kkkk kkkk
RETFIE - Return from interrupt 2 00 0000 0000 1001
RETLW k Return with literal in W 2 11 01xx kkkk kkkk
RETURN - Return from Subroutine 2 00 0000 0000 1000
SLEEP - Go into standby mode 1 00 0000 0110 0011 TO,PD
SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C,DC,Z
XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external
device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.

PIC14000
11.1 Instruction Descriptions
ADDLW Add Literal and W ANDLW And Literal with W

Syntax: [ label ] ADDLW k Syntax: [ label ] ANDLW k
Operands: 0 k 255 Operands: 0 k 255
Operation: (W) + k (W) Operation: (W) .AND. (k) (W)
Status Affected: C, DC, Z Status Affected: Z
Encoding: 11 111x kkkk kkkk Encoding: 11 1001 kkkk kkkk
Description: The contents of the W register are Description: The contents of W register are
added to the eight bit literal 'k' and the ANDed with the eight bit literal 'k'. The
result is placed in the W register. result is placed in the W register.
Words: 1 Words: 1
Cycles: 1 Cycles: 1
Example ADDLW 0x15 Example ANDLW 0x5F
Before Instruction Before Instruction

W = 0x10 W = 0xA3
After Instruction After Instruction
W = 0x25 W = 0x03
ADDWF Add W and f ANDWF AND W with f

Syntax: [ label ] ADDWF f,d Syntax: [ label ] ANDWF f,d
Operands: 0 f 127 Operands: 0 f 127
d [0,1] d [0,1]
Operation: (W) + (f) (dest) Operation: (W) .AND. (f) (dest)
Status Affected: C, DC, Z Status Affected: Z
Encoding: 00 0111 dfff ffff Encoding: 00 0101 dfff ffff
Description: Add the contents of the W register Description: AND the W register with register 'f'. If
with register 'f'. If 'd' is 0 the result is 'd' is 0 the result is stored in the W
stored in the W register. If 'd' is 1 the register. If 'd' is 1 the result is stored
result is stored back in register 'f'. back in register 'f'.
Words: 1 Words: 1
Cycles: 1 Cycles: 1
Example ADDWF FSR, 0 Example ANDWF FSR, 1
Before Instruction Before Instruction
W = 0x17 W = 0x17
FSR = 0xC2 FSR = 0xC2
W = 0xD9 W = 0x17
FSR = 0xC2 FSR = 0x02

PIC14000
BCF Bit Clear f BTFSC Bit Test, Skip if Clear

Syntax: [ label ] BCF f,b Syntax: [ label ] BTFSC f,b
0b7 0b7
Operation: 0 (f<b>) Operation: skip if (f<b>) = 0
Status Affected: None Status Affected: None
Encoding: 01 00bb bfff ffff Encoding: 01 10bb bfff ffff
Description: Bit 'b' in register 'f' is cleared. Description: If bit 'b' in register 'f' is '0' then the next
instruction is skipped.
Words: 1 If bit 'b' is '0' then the next instruction
Cycles: 1 fetched during the current instruction
execution is discarded, and a NOP is
Example BCF FLAG_REG, 7
executed instead, making this a 2 cycle
Before Instruction instruction.
FLAG_REG = 0xC7
Words: 1
After Instruction
FLAG_REG = 0x47 Cycles: 1(2)
Example HERE BTFSC FLAG,1
FALSE GOTO PROCESS_CODE
TRUE

Before Instruction
PC = address HERE
After Instruction
if FLAG<1> = 0,
PC = address TRUE
if FLAG<1>=1,
PC = address FALSE
BSF Bit Set f
Syntax: [ label ] BSF f,b
Operands: 0 f 127
0b7
Operation: 1 (f<b>)
Status Affected: None
Encoding: 01 01bb bfff ffff
Description: Bit 'b' in register 'f' is set.
Words: 1
Cycles: 1
Example BSF FLAG_REG, 7
Before Instruction
FLAG_REG = 0x0A
After Instruction
FLAG_REG = 0x8A

PIC14000
BTFSS Bit Test f, Skip if Set CLRF Clear f

Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRF f
0b<7 Operation: 00h (f)
Operation: skip if (f<b>) = 1 1Z
Status Affected: None Status Affected: Z
Encoding: 01 11bb bfff ffff Encoding: 00 0001 1fff ffff
Description: If bit 'b' in register 'f' is '1' then the next Description: The contents of register 'f' are cleared
instruction is skipped. and the Z bit is set.
If bit 'b' is '1', then the next instruction
fetched during the current instruction Words: 1
execution, is discarded and a NOP is
executed instead, making this a 2 cycle Cycles: 1
instruction.
Example CLRF FLAG_REG
Words: 1
Before Instruction
Cycles: 1(2) FLAG_REG = 0x5A
Example HERE BTFSC FLAG,1 After Instruction
FALSE GOTO PROCESS_CODE FLAG_REG = 0x00
TRUE Z = 1

Before Instruction
PC = address HERE
After Instruction
if FLAG<1> = 0,
PC = address FALSE
if FLAG<1> = 1,
PC = address TRUE
CALL Call Subroutine CLRW Clear W

Syntax: [ label ] CALL k Syntax: [ label ] CLRW
Operands: 0 k 2047 Operands: None
Operation: (PC)+ 1 TOS, Operation: 00h (W)
k PC<10:0>, 1Z
(PCLATH<4:3>) PC<12:11> Status Affected: Z
Status Affected: None Encoding: 00 0001 0xxx xxxx
Encoding: 10 0kkk kkkk kkkk
Description: W register is cleared. Zero bit (Z) is
Description: Call Subroutine. First, return address set.
(PC+1) is pushed onto the stack. The
eleven bit immediate address is loaded Words: 1
into PC bits <10:0>. The upper bits of
the PC are loaded from PCLATH. Cycles: 1
CALL is a two cycle instruction. Example CLRW
Words: 1 Before Instruction
Cycles: 2 W = 0x5A
After Instruction
Example HERE CALL THERE
W = 0x00
Before Instruction Z = 1
PC = Address HERE
After Instruction
PC = Address THERE
TOS = Address HERE+1

PIC14000
CLRWDT Clear Watchdog Timer DECF Decrement f

Syntax: [ label ] CLRWDT Syntax: [ label ] DECF f,d
Operands: None Operands: 0 f 127
Operation: 00h WDT d [0,1]
0 WDT prescaler, Operation: (f) - 1 (dest)
1 TO Status Affected: Z
1 PD
Encoding: 00 0011 dfff ffff
Status Affected: TO, PD
Description: Decrement register 'f'. If 'd' is 0 the
Encoding: 00 0000 0110 0100 result is stored in the W register. If 'd'
is 1 the result is stored back in register
Description: CLRWDT instruction resets the Watch- 'f'.
dog Timer. It also resets the prescaler
of the WDT. Status bits TO and PD Words: 1
are set.
Cycles: 1
Words: 1
Example DECF CNT, 1
Cycles: 1
Before Instruction
Example CLRWDT CNT = 0x01
Before Instruction Z = 0
WDT counter = ? After Instruction
After Instruction CNT = 0x00
Z = 1
WDT counter = 0x00
WDT prescaler = 0
TO = 1
PD = 1
COMF Complement f DECFSZ Decrement f, Skip if 0

Syntax: [ label ] COMF f,d Syntax: [ label ] DECFSZ f,d
d [0,1] d [0,1]
Operation: (f) (dest) Operation: (f) - 1 (dest); skip if result = 0
Status Affected: Z Status Affected: None
Description: The contents of register 'f' are comple- Description: The contents of register 'f' are decre-
mented. If 'd' is 0 the result is stored in mented. If 'd' is 0 the result is placed in
W. If 'd' is 1 the result is stored back in the W register. If 'd' is 1 the result is
register 'f'. placed back in register 'f'.
If the result is 0, the next instruction,
Words: 1 which is already fetched, is discarded. A
NOP is executed instead making it a two
Cycles: 1 cycle instruction.
Example COMF REG1,0 Words: 1
Before Instruction Cycles: 1(2)
REG1 = 0x13
After Instruction Example HERE DECFSZ CNT, 1
GOTO LOOP
REG1 = 0x13
CONTINUE
W = 0xEC

Before Instruction
PC = address HERE
After Instruction
CNT = CNT - 1
if CNT = 0,
PC = address CONTINUE
if CNT 0,
PC = address HERE+1

PIC14000
GOTO Unconditional Branch INCFSZ Increment f, Skip if 0

Syntax: [ label ] GOTO k Syntax: [ label ] INCFSZ f,d
Operands: 0 k 2047 Operands: 0 f 127
Operation: k PC<10:0> d [0,1]
PCLATH<4:3> PC<12:11> Operation: (f) + 1 (dest), skip if result = 0
Encoding: 10 1kkk kkkk kkkk Encoding: 00 1111 dfff ffff
Description: GOTO is an unconditional branch. The Description: The contents of register 'f' are incre-
eleven bit immediate value is loaded mented. If 'd' is 0 the result is placed
into PC bits <10:0>. The upper bits of in the W register. If 'd' is 1 the result is
PC are loaded from PCLATH<4:3>. placed back in register 'f'.
GOTO is a two cycle instruction. If the result is 0, the next instruction,
which is already fetched, is discarded.
Words: 1 A NOP is executed instead making it a
two cycle instruction.
Cycles: 2
Words: 1
Example GOTO THERE
Cycles: 1(2)
After Instruction
PC = Address THERE Example HERE INCFSZ CNT, 1
GOTO LOOP
CONTINUE

Before Instruction
PC = address HERE
After Instruction
CNT = CNT + 1
if CNT= 0,
PC = address CONTINUE
if CNT 0,
PC = address HERE +1
INCF Increment f IORLW Inclusive OR Literal with W

Syntax: [ label ] INCF f,d Syntax: [ label ] IORLW k
Operands: 0 f 127 Operands: 0 k 255
d [0,1]
Operation: (W) .OR. k (W)
Operation: (f) + 1 (dest)
Status Affected: Z
Status Affected: Z
Encoding: 11 1000 kkkk kkkk
Encoding: 00 1010 dfff ffff
Description: The contents of the W register is
Description: The contents of register 'f' are incre- ORed with the eight bit literal 'k'. The
mented. If 'd' is 0 the result is placed result is placed in the W register.
in the W register. If 'd' is 1 the result is
placed back in register 'f'.
Words: 1
Words: 1 Cycles: 1
Cycles: 1 Example IORLW 0x35
Example INCF CNT, 1 Before Instruction

W = 0x9A
Before Instruction After Instruction
CNT = 0xFF W = 0xBF
Z = 0 Z = 1
After Instruction
CNT = 0x00
Z = 1

PIC14000
IORWF Inclusive OR W with f MOVF Move f

Syntax: [ label ] IORWF f,d Syntax: [ label ] MOVF f,d
d [0,1] d [0,1]
Operation: (W) .OR. (f) (dest) Operation: (f) (dest)
Status Affected: Z Status Affected: Z
Description: Inclusive OR the W register with regis- Description: The contents of register f is moved to
ter 'f'. If 'd' is 0 the result is placed in a destination dependant upon the sta-
the W register. If 'd' is 1 the result is tus of d. If d = 0, destination is W reg-
placed back in register 'f'. ister. If d = 1, the destination is file
Words: 1 register f itself. d = 1 is useful to test a
file register since status flag Z is
Cycles: 1 affected.
Example IORWF RESULT, 0 Words: 1
Before Instruction Cycles: 1
RESULT = 0x13
W = 0x91 Example MOVF FSR, 0
RESULT = 0x13 W = value in FSR register
W = 0x93 Z =1
Z = 1
MOVLW Move Literal to W MOVWF Move W to f

Syntax: [ label ] MOVLW k Syntax: [ label ] MOVWF f
Operation: k (W) Operation: (W) (f)
Encoding: 11 00xx kkkk kkkk Encoding: 00 0000 1fff ffff
Description: The eight bit literal 'k' is loaded into W Description: Move data from W register to register
register. The dont cares will assemble 'f'.
as 0s.
Words: 1
Words: 1
Cycles: 1
Cycles: 1
Example MOVWF OPTION
Example MOVLW 0x5A
Before Instruction
After Instruction OPTION = 0xFF
W = 0x5A W = 0x4F
After Instruction
OPTION = 0x4F
W = 0x4F

PIC14000
NOP No Operation RETFIE Return from Interrupt

Syntax: [ label ] NOP Syntax: [ label ] RETFIE
Operands: None Operands: None
Operation: No operation Operation: TOS PC,
Status Affected: None 1 GIE
Encoding: 00 0000 0xx0 0000 Status Affected: None
Description: No operation. Encoding: 00 0000 0000 1001
Words: 1 Description: Return from Interrupt. Stack is POPed

and Top of Stack (TOS) is loaded in
Cycles: 1 the PC. Interrupts are enabled by set-
ting Global Interrupt Enable bit, GIE
Example NOP
(INTCON<7>). This is a two cycle
instruction.
Words: 1
Cycles: 2
Example RETFIE
After Interrupt
PC = TOS
GIE = 1
OPTION Load Option Register RETLW Return with Literal in W

Syntax: [ label ] OPTION Syntax: [ label ] RETLW k
Operands: None Operands: 0 k 255
Operation: (W) OPTION Operation: k (W);
Status Affected: None TOS PC
Encoding: 00 0000 0110 0010 Status Affected: None
Description: The contents of the W register are Encoding: 11 01xx kkkk kkkk
loaded in the OPTION register. This
instruction is supported for code com- Description: The W register is loaded with the eight
bit literal 'k'. The program counter is
patibility with PIC16C5X products.
loaded from the top of the stack (the
Since OPTION is a readable/writable
return address). This is a two cycle
register, the user can directly address
instruction.
it.
Words: 1 Words: 1
Cycles: 1 Cycles: 2
Example Example CALL TABLE ;W contains table
;offset value
To maintain upward compatibility ;W now has table value
with future PIC16CXX products, do

not use this instruction. TABLE ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2 ;

RETLW kn ; End of table
Before Instruction
W = 0x07
After Instruction
W = value of k8

PIC14000
RETURN Return from Subroutine RRF Rotate Right f through Carry

Syntax: [ label ] RETURN Syntax: [ label ] RRF f,d
Operands: None Operands: 0 f 127
Operation: TOS PC d [0,1]
Status Affected: None Operation: See description below
Encoding: 00 0000 0000 1000 Status Affected: C
Description: Return from subroutine. The stack is Encoding: 00 1100 dfff ffff
POPed and the top of the stack (TOS) Description: The contents of register 'f' are rotated
is loaded into the program counter. one bit to the right through the Carry
This is a two cycle instruction. Flag. If 'd' is 0 the result is placed in
Words: 1 the W register. If 'd' is 1 the result is
placed back in register 'f'.
Cycles: 2
C Register f
Example RETURN
After Interrupt Words: 1
PC = TOS
Cycles: 1
Example RRF REG1,0
Before Instruction
REG1 = 1110 0110
C = 0
After Instruction
REG1 = 1110 0110
W = 0111 0011
C = 0
RLF Rotate Left f through Carry SLEEP

Syntax: [ label ] RLF f,d Syntax: [ label ] SLEEP
Operands: 0 f 127 Operands: None
d [0,1]
Operation: 00h WDT,
Operation: See description below 0 WDT prescaler,
Status Affected: C 1 TO,
Encoding: 00 1101 dfff ffff 0 PD
Description: The contents of register 'f' are rotated Status Affected: TO, PD
one bit to the left through the Carry Encoding: 00 0000 0110 0011
Flag. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is Description: The power-down status bit, PD is
cleared. Time-out status bit, TO is
stored back in register 'f'.
set. Watchdog Timer and its pres-
C Register f caler are cleared.
The processor is put into SLEEP
Words: 1 mode with the oscillator stopped.
See Section 10.8 for more details.
Cycles: 1
Words: 1
Example RLF REG1,0
Cycles: 1
Before Instruction
REG1 = 1110 0110 Example: SLEEP
C = 0
After Instruction
REG1 = 1110 0110
W = 1100 1100
C = 1

PIC14000
SUBLW Subtract W from Literal SUBWF Subtract W from f

Syntax: [ label ] SUBLW k Syntax: [ label ] SUBWF f,d
Operation: k - (W) (W) d [0,1]
Status C, DC, Z Operation: (f) - (W) (dest)

Affected: Status C, DC, Z
Encoding: 11 110x kkkk kkkk Affected:
Description: The W register is subtracted (2s com- Encoding: 00 0010 dfff ffff
plement method) from the eight bit literal Description: Subtract (2s complement method) W reg-
'k'. The result is placed in the W register. ister from register 'f'. If 'd' is 0 the result is
Words: 1 stored in the W register. If 'd' is 1 the
result is stored back in register 'f'.
Cycles: 1
Words: 1
Example 1: SUBLW 0x02
Cycles: 1
Before Instruction
Example 1: SUBWF REG1,1
W = 1
C = ? Before Instruction
After Instruction REG1 = 3
W = 2
W = 1 C = ?
C = 1; result is positive
After Instruction
Example 2: Before Instruction
REG1 = 1
W = 2 W = 2
C = ? C = 1; result is positive
After Instruction Example 2: Before Instruction
W = 0 REG1 = 2
C = 1; result is zero W = 2
Example 3: Before Instruction C = ?
W = 3 After Instruction
C = ? REG1 = 0
After Instruction W = 2
C = 1; result is zero
W = 0xFF
C = 0; result is nega- Example 3: Before Instruction
tive REG1 = 1
W = 2
C = ?
After Instruction
REG1 = 0xFF
W = 2
C = 0; result is negative

PIC14000
SWAPF Swap Nibbles in f XORLW Exclusive OR Literal with W

Syntax: [ label ] SWAPF f,d Syntax: [ label ] XORLW k
Operands: 0 f 127 Operands: 0 k 255
d [0,1]
Operation: (W) .XOR. k (W)
Operation: (f<3:0>) (dest<7:4>),
(f<7:4>) (dest<3:0>) Status Affected: Z
Status Affected: None Encoding: 11 1010 kkkk kkkk
Encoding: 00 1110 dfff ffff Description: The contents of the W register are
XORed with the eight bit literal 'k'.
Description: The upper and lower nibbles of regis- The result is placed in the W regis-
ter 'f' are exchanged. If 'd' is 0 the ter.
result is placed in W register. If 'd' is 1
the result is placed in register 'f'.
Words: 1
Words: 1 Cycles: 1
Cycles: 1 Example: XORLW 0xAF
Example SWAPF REG, 0 Before Instruction

W = 0xB5
Before Instruction
REG1 = 0xA5 After Instruction
W = 0x1A
After Instruction
REG1 = 0xA5
W = 0x5A
TRIS Load TRIS Register XORWF Exclusive OR W with f

Syntax: [ label ] TRIS f Syntax: [ label ] XORWF f,d
Operands: 5f7 Operands: 0 f 127
Operation: (W) TRIS register f; d [0,1]
Status Affected: None Operation: (W) .XOR. (f) (dest)
Encoding: 00 0000 0110 0fff Status Affected: Z
Description: The instruction is supported for code Encoding: 00 0110 dfff ffff
compatibility with the PIC16C5X prod-
ucts. Since TRIS registers are read- Description: Exclusive OR the contents of the W
able and writable, the user can directly register with register 'f'. If 'd' is 0 the
address them. result is stored in the W register. If 'd'
is 1 the result is stored back in register
Words: 1 'f'.
Cycles: 1 Words: 1
Example
Cycles: 1
To maintain upward compatibility
with future PIC16CXX products, do Example XORWF REG 1
not use this instruction. Before Instruction
REG = 0xAF
W = 0xB5
After Instruction
REG = 0x1A
W = 0xB5

PIC14000
12.0 DEVELOPMENT SUPPORT 12.3 ICEPIC: Low-cost PIC16CXX In-Circuit
Emulator
12.1 Development Tools
ICEPIC is a low-cost in-circuit emulator solution for the
The PIC16/17 microcontrollers are supported with a full Microchip PIC16C5X and PIC16CXX families of 8-bit
range of hardware and software development tools: OTP microcontrollers.
PICMASTER/PICMASTER CE Real-Time ICEPIC is designed to operate on PC-compatible
In-Circuit Emulator machines ranging from 286-AT through Pentium
ICEPIC Low-Cost PIC16C5X and PIC16CXX based machines under Windows 3.x environment.
In-Circuit Emulator ICEPIC features real time, non-intrusive emulation.
PRO MATE II Universal Programmer
12.4 PRO MATE II: Universal Programmer
PICSTART Plus Entry-Level Prototype
Programmer The PRO MATE II Universal Programmer is a full-fea-
PICDEM-1 Low-Cost Demonstration Board tured programmer capable of operating in stand-alone
PICDEM-2 Low-Cost Demonstration Board mode as well as PC-hosted mode.
PICDEM-3 Low-Cost Demonstration Board The PRO MATE II has programmable VDD and VPP
MPASM Assembler supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
MPLAB-SIM Software Simulator
an LCD display for displaying error messages, keys to
MPLAB-C (C Compiler) enter commands and a modular detachable socket
Fuzzy logic development system (fuzzyTECHMP) assembly to support various package types. In stand-
alone mode the PRO MATE II can read, verify or pro-
12.2 PICMASTER: High Performance gram PIC16C5X, PIC16CXX, PIC17CXX and
Universal In-Circuit Emulator with PIC14000 devices. It can also set configuration and
MPLAB IDE code-protect bits in this mode.
The PICMASTER Universal In-Circuit Emulator is 12.5 PICSTART Plus Entry Level
intended to provide the product development engineer Development System
with a complete microcontroller design tool set for all
microcontrollers in the PIC12C5XX, PIC14000, The PICSTART programmer is an easy-to-use, low-
PIC16C5X, PIC16CXX and PIC17CXX families. cost prototype programmer. It connects to the PC via
PICMASTER is supplied with the MPLAB Integrated one of the COM (RS-232) ports. MPLAB Integrated
Development Environment (IDE), which allows editing, Development Environment software makes using the
make and download, and source debugging from a programmer simple and efficient. PICSTART Plus is
single environment. not recommended for production programming.
Interchangeable target probes allow the system to be PICSTART Plus supports all PIC12C5XX, PIC14000,
easily reconfigured for emulation of different proces- PIC16C5X, PIC16CXX and PIC17CXX devices with up
sors. The universal architecture of the PICMASTER to 40 pins. Larger pin count devices such as the
allows expansion to support all new Microchip micro- PIC16C923 and PIC16C924 may be supported with an
controllers. adapter socket.
The PICMASTER Emulator System has been
designed as a real-time emulation system with
advanced features that are generally found on more
expensive development tools. The PC compatible 386
(and higher) machine platform and Microsoft Windows
3.x environment were chosen to best make these fea-
tures available to you, the end user.
A CE compliant version of PICMASTER is available for
European Union (EU) countries.

PIC14000
12.6 PICDEM-1 Low-Cost PIC16/17 include an RS-232 interface, push-button switches, a
Demonstration Board potentiometer for simulated analog input, a thermistor
and separate headers for connection to an external
The PICDEM-1 is a simple board which demonstrates LCD module and a keypad. Also provided on the PIC-
the capabilities of several of Microchips microcontrol- DEM-3 board is an LCD panel, with 4 commons and 12
lers. The microcontrollers supported are: PIC16C5X segments, that is capable of displaying time, tempera-
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, ture and day of the week. The PICDEM-3 provides an
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and additional RS-232 interface and Windows 3.1 software
PIC17C44. All necessary hardware and software is for showing the demultiplexed LCD signals on a PC. A
included to run basic demo programs. The users can simple serial interface allows the user to construct a
program the sample microcontrollers provided with hardware demultiplexer for the LCD signals. PICDEM-
the PICDEM-1 board, on a PRO MATE II or 3 will be available in the 3rd quarter of 1996.
PICSTART-16B programmer, and easily test firm-
ware. The user can also connect the PICDEM-1 12.9 MPLAB Integrated Development
board to the PICMASTER emulator and download Environment Software
the firmware to the emulator for testing. Additional pro-
totype area is available for the user to build some addi- The MPLAB IDE Software brings an ease of software
tional hardware and connect it to the microcontroller development previously unseen in the 8-bit microcon-
socket(s). Some of the features include an RS-232 troller market. MPLAB is a windows based application
interface, a potentiometer for simulated analog input, which contains:
push-button switches and eight LEDs connected to A full featured editor
PORTB. Three operating modes
- editor
12.7 PICDEM-2 Low-Cost PIC16CXX - emulator
Demonstration Board - simulator
A project manager
The PICDEM-2 is a simple demonstration board that
Customizable tool bar and key mapping
supports the PIC16C62, PIC16C64, PIC16C65,
A status bar with project information
PIC16C73 and PIC16C74 microcontrollers. All the
Extensive on-line help
necessary hardware and software is included to
run the basic demonstration programs. The user MPLAB allows you to:
can program the sample microcontrollers provided Edit your source files (either assembly or C)
with the PICDEM-2 board, on a PRO MATE II pro- One touch assemble (or compile) and download
grammer or PICSTART-16C, and easily test firmware. to PIC16/17 tools (automatically updates all
The PICMASTER emulator may also be used with the project information)
PICDEM-2 board to test firmware. Additional prototype Debug using:
area has been provided to the user for adding addi- - source files
tional hardware and connecting it to the microcontroller - absolute listing file
socket(s). Some of the features include a RS-232 inter- Transfer data dynamically via DDE (soon to be
face, push-button switches, a potentiometer for simu- replaced by OLE)
lated analog input, a Serial EEPROM to demonstrate Run up to four emulators on the same PC
usage of the I2C bus and separate headers for connec-
The ability to use MPLAB with Microchips simulator
tion to an LCD module and a keypad.
allows a consistent platform and the ability to easily
12.8 PICDEM-3 Low-Cost PIC16CXX switch from the low cost simulator to the full featured
Demonstration Board emulator with minimal retraining due to development
tools.
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC 12.10 Assembler (MPASM)
package. It will also support future 44-pin PLCC
The MPASM Universal Macro Assembler is a PC-
microcontrollers with a LCD Module. All the neces-
hosted symbolic assembler. It supports all microcon-
sary hardware and software is included to run the
troller series including the PIC12C5XX, PIC14000,
basic demonstration programs. The user can pro-
PIC16C5X, PIC16CXX, and PIC17CXX families.
gram the sample microcontrollers provided with
the PICDEM-3 board, on a PRO MATE II program- MPASM offers full featured Macro capabilities, condi-
mer or PICSTART Plus with an adapter socket, and tional assembly, and several source and listing formats.
easily test firmware. The PICMASTER emulator may It generates various object code formats to support
also be used with the PICDEM-3 board to test firm- Microchip's development tools as well as third party
ware. Additional prototype area has been provided to programmers.
the user for adding hardware and connecting it to the
microcontroller socket(s). Some of the features

PIC14000
MPASM allows full symbolic debugging from Both versions include Microchips fuzzyLAB demon-
the Microchip Universal Emulator System stration board for hands-on experience with fuzzy logic
(PICMASTER). systems implementation.
MPASM has the following features to assist in develop-
12.14 MP-DriveWay Application Code
ing software for specific use applications.
Generator
Provides translation of Assembler source code to
object code for all Microchip microcontrollers. MP-DriveWay is an easy-to-use Windows-based Appli-
Macro assembly capability. cation Code Generator. With MP-DriveWay you can
visually configure all the peripherals in a PIC16/17
Produces all the files (Object, Listing, Symbol,
device and, with a click of the mouse, generate all the
and special) required for symbolic debug with
initialization and many functional code modules in C
Microchips emulator systems.
language. The output is fully compatible with Micro-
Supports Hex (default), Decimal and Octal chips MPLAB-C C compiler. The code produced is
source and listing formats. highly modular and allows easy integration of your own
MPASM provides a rich directive language to support code. MP-DriveWay is intelligent enough to maintain
programming of the PIC16/17. Directives are helpful in your code through subsequent code generation.
making the development of your assemble source
code shorter and more maintainable. 12.15 SEEVAL Evaluation and
Programming System
12.11 Software Simulator (MPLAB-SIM)
The SEEVAL SEEPROM Designers Kit supports all
The MPLAB-SIM Software Simulator allows code Microchip 2-wire and 3-wire Serial EEPROMs. The kit
development in a PC host environment. It allows the includes everything necessary to read, write, erase or
user to simulate the PIC16/17 series microcontrollers program special features of any Microchip SEEPROM
on an instruction level. On any given instruction, the product including Smart Serials and secure serials.
user may examine or modify any of the data areas or The Total Endurance Disk is included to aid in trade-
provide external stimulus to any of the pins. The input/ off analysis and reliability calculations. The total kit can
output radix can be set by the user and the execution significantly reduce time-to-market and result in an
can be performed in; single step, execute until break, optimized system.
or in a trace mode.
12.16 TrueGauge Intelligent Battery
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C and MPASM. The Software Simulator offers Management
the low cost flexibility to develop and debug code out- The TrueGauge development tool supports system
side of the laboratory environment making it an excel- development with the MTA11200B TrueGauge Intelli-
lent multi-project software development tool. gent Battery Management IC. System design verifica-
tion can be accomplished before hardware prototypes
12.12 C Compiler (MPLAB-C)
are built. User interface is graphically-oriented and
The MPLAB-C Code Development System is a com- measured data can be saved in a file for exporting to
plete C compiler and integrated development environ- Microsoft Excel.
ment for Microchips PIC16/17 family of
microcontrollers. The compiler provides powerful inte- 12.17 KEELOQ Evaluation and
gration capabilities and ease of use not found with Programming Tools
other compilers.
KEELOQ evaluation and programming tools support
For easier source level debugging, the compiler pro- Microchips HCS Secure Data Products. The HCS eval-
vides symbol information that is compatible with the uation kit includes an LCD display to show changing
MPLAB IDE memory display (PICMASTER emulator codes, a decoder to decode transmissions, and a pro-
software versions 1.13 and later). gramming interface to program test transmitters.
12.13 Fuzzy Logic Development System

(fuzzyTECH-MP)
fuzzyTECH-MP fuzzy logic development tool is avail-
able in two versions - a low cost introductory version,
MP Explorer, for designers to gain a comprehensive
working knowledge of fuzzy logic system design; and a
full-featured version, fuzzyTECH-MP, edition for imple-
menting more complex systems.

Product ** MPLAB MPLAB C MP-DriveWay fuzzyTECH-MP *** PICMASTER/ ICEPIC ****PRO MATE PICSTART Lite PICSTART Plus
Integrated Compiler Applications Explorer/Edition PICMASTER-CE Low-Cost II Universal Ultra Low-Cost Low-Cost
Development Code Fuzzy Logic In-Circuit In-Circuit Microchip Dev. Kit Universal
Environment Generator Dev. Tool Emulator Emulator Programmer Dev. Kit
PIC12C508, 509 SW007002 SW006005 EM167015/ DV007003 DV003001
EM167101
TABLE 12-1:
PIC14000 SW007002 SW006005 EM147001/ DV007003 DV003001

EM147101
PIC16C52, 54, 54A, SW007002 SW006005 SW006006 DV005001/ EM167015/ EM167201 DV007003 DV162003 DV003001
55, 56, 57, 58A DV005002 EM167101
PIC16C554, 556, 558 SW007002 SW006005 DV005001/ EM167033/ - DV007003 DV003001
DV005002 EM167113
1996 Microchip Technology Inc.

PIC16C61 SW007002 SW006005 SW006006 DV005001/ EM167021/ EM167205 DV007003 DV162003 DV003001
DV005002 N/A
PIC16C62, 62A, SW007002 SW006005 SW006006 DV005001/ EM167025/ EM167203 DV007003 DV162002 DV003001
64, 64A DV005002 EM167103
PIC16C620, 621, 622 SW007002 SW006005 SW006006 DV005001/ EM167023/ EM167202 DV007003 DV162003 DV003001
DV005002 EM167109
PIC16C63, 65, 65A, SW007002 SW006005 SW006006 DV005001/ EM167025/ EM167204 DV007003 DV162002 DV003001
73, 73A, 74, 74A DV005002 EM167103
PIC16C642, 662* SW007002 SW006005 EM167035/ - DV007003 DV162002 DV003001
EM167105
DV005002 EM167105
PIC16C710, 711 SW007002 SW006005 SW006006 DV005001/ EM167027/ DV007003 DV162003 DV003001
DV005002 EM167105
PIC16C72 SW007002 SW006005 SW006006 EM167025/ DV007003 DV162002 DV003001
Preliminary
EM167103
DEVELOPMENT TOOLS FROM MICROCHIP
PIC16F83 SW007002 SW006005 SW006006 DV005001/ EM167029/ DV007003 DV162003 DV003001

DV005002 EM167107
DV005002 EM167107
PIC16F84 SW007002 SW006005 SW006006 DV005001/ EM167029/ DV007003 DV162003 DV003001
DV005002 EM167107
PIC16C923, 924* SW007002 SW006005 SW006006 DV005001/ EM167031/ DV007003 DV003001
DV005002 EM167111
PIC17C42, SW007002 SW006005 SW006006 DV005001/ EM177007/ DV007003 DV003001
42A, 43, 44 DV005002 EM177107
*Contact Microchip Technology for availability date ***All PICMASTER and PICMASTER-CE ordering part numbers above include
**MPLAB Integrated Development Environment includes MPLAB-SIM Simulator and PRO MATE II programmer
MPASM Assembler ****PRO MATE socket modules are ordered separately. See development systems
ordering guide for specific ordering part numbers
Product TRUEGAUGE Development Kit SEEVAL Designers Kit Hopping Code Security Programmer Kit Hopping Code Security Eval/Demo Kit
All 2 wire and 3 wire N/A DV243001 N/A N/A
Serial EEPROM's
MTA11200B DV114001 N/A N/A N/A
HCS200, 300, 301 * N/A N/A PG306001 DM303001
DS40122B-page 106
PIC14000
PIC14000
13.0 ELECTRICAL CHARACTERISTICS FOR PIC14000
ABSOLUTE MAXIMUM RATINGS
Ambient temperature under bias.............................................................................................................-55C to+ 125C
Storage Temperature ............................................................................................................................. -65C to +150C
Voltage on any pin with respect to VSS (except VDD and MCLR) ...................................................... -0.5V to VDD +0.6V
Voltage on VDD with respect to VSS .............................................................................................................. 0 to +6.0 V
Voltage on MCLR with respect to VSS (Note 2) ...............................................................................................0 to +14 V
Total power Dissipation (Note 1) ..............................................................................................................................1.0 W
Maximum Current out of VSS pin ...........................................................................................................................300mA
Maximum Current into VDD pin ..............................................................................................................................250mA
Input clamp current, IIK (VI <0 or VI> VDD) .........................................................................................................................20mA
Output clamp current, IOK (VO <0 or VO>VDD) ...................................................................................................................20mA
Maximum Output Current sunk by any I/O pin .........................................................................................................25mA
Maximum Output Current sourced by any I/O pin....................................................................................................25mA
Maximum Current sunk by PORTA, PORTC, and PORTD(combined) ..................................................................200mA
Maximum Current sourced by PORTA, PORTC, and PORTE (combined) ............................................................200mA
Maximum Current sunk by PORTC and PORTD (combined) ................................................................................200mA
Maximum Current sourced by PORTC and PORTD (combined)...........................................................................200mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL)
Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80mA, may cause latch-up. Thus,
a series resistor of 50-100 should be used when applying a low level to the MCLR pin rather than pulling
this pin directly to VSS.
NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

PIC14000
13.1 DC Characteristics: PIC14000
Standard Operating Conditions (unless otherwise stated)

Operating temperature -40C TA + 85C for industrial and
DC CHARACTERISTICS
0C TA +70C for commercial
Operating voltage VDD = 2.7V to 6.0V
Characteristic Sym Min Typ Max Units Conditions
Supply Voltage VDD 2.7 6.0 V IN or HS at Fosc 4 MHz
4.5 5.5 V HS at Fosc > 4 MHz
RAM Data Retention VDR 1.5 V Device in SLEEP mode

Voltage (Note 1)
VDD start voltage to VPOR VSS V See section on power-on reset for details
guarantee Power-On Reset
VDD rise rate to guarantee SVDD 0.05* V/ms See section on power-on reset for details
Power-On Reset
Operating Current in SLEEP Mode (Note 2)
During A/D conversion: IPD1 TBD 900 A VDD = 3.0V

all analog on and internal IPD1 TBD 1250 A VDD = 4.0V
oscillator active
Comparator interrupt enabled: IPD2 75 100 A VDD = 3.0V, CMOFF = 0, LSOFF = 0, REFOFF = 0
level-shift, programmable
reference, and comparator active IPD2 95 125 A VDD = 4.0V, CMOFF = 0, LSOFF = 0, REFOFF = 0
All analog off, WDT on (Note 5) IPD3 7.5 20 A VDD = 3.0V

IPD3 10.5 28 A VDD = 4.0V
All analog off, WDT off IPD4 0.9 12 A VDD = 3.0V

(Hibernate mode) (Note 5) IPD4 1.5 16 A VDD = 4.0V
Operating Supply Current (Note 2, 4)
Internal oscillator mode IDD 2.2 TBD mA Fosc = 4 MHz, VDD = 5.5V
1.1 TBD mA Fosc = 4 MHz, VDD = 3.0V
HS oscillator mode 2.4 TBD mA Fosc = 4 MHz, VDD = 5.5V

1.2 TBD mA Fosc = 4 MHz, VDD = 3.0V
10 TBD mA Fosc = 20 MHz, VDD = 5.5V
* These parameters are characterized but not tested.
Data in Typ column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to VDD.
MCLR = VDD; WDT enabled/disabled as specified.
3: Measured with all inputs at rails, no DC loads. IPD1 measured with internal oscillator active.
4: IDD values of individual analog module cannot be tested independently but are characterized.
5: Worst-case IPD conditions with all configuration bits unprogrammed. Programming configuration bits
may reduce IPD.

PIC14000
13.2 DC Characteristics: PIC14000
Operating temperature -40C TA + 85C for industrial and
DC CHARACTERISTICS
Operating voltage VDD range as described in Section 13.1.
Characteristic Sym Min Typ Max Units Conditions
Input Low Voltage
I/O ports VIL
Schmitt Trigger mode VSS 0.2VDD V
SMBus mode (RC7, RC6, RD0, RD1) VSS 0.6 V SMBus bit, MISC<3> = 1
MCLR, OSC1 (in IN mode) Vss 0.2VDD V
OSC1 (in HS mode) Vss 0.3VDD V
Input High Voltage
I/O ports VIH
Schmitt Trigger mode 0.85 VDD VDD V

SMBus mode (RC7, RC6, RD0, RD1) 1.4V VDD V SMBus bit, MISC<3> = 1
PORTC<5:0> weak pull-up current IPURC 50 200 400 A VDD = 5V, VPIN = VSS
Input Leakage Current (Notes 1,2)
I/O ports, CDAC IIL 1 A Vss VPIN VDD, Pin at hi-impedance
MCLR 5 A Vss VPIN VDD
OSC1 5 A Vss VPIN VDD
Output Low Voltage
I/O ports VOL 0.6 V IOL = 8.5mA, VDD-4.5V, -40C to +85C
OSC2 0.6 V IOL = 1.6mA, VDD-4.5V, -40C to +85C
Output High Voltage
I/O ports (Note 2) VOH VDD-0.7 V IOH = -3.0mA, VDD=4.5V, -40C to +85C
RC6, RC7, RD0, RD1 (except I2C mode) 2.4 V IOH = -2.0mA, VDD=4.5V, -40C to +85C
OSC2 VDD-0.7 V IOH = -1.3mA, VDD=4.5V, -40C to +85C
Capacitive Loading Specs on Output
Pins
OSC2 pin COSC2 15 pF
All I/O pins except OSC2 (in IN mode) CIO 50 pF
SCL, SDA in I2C mode Cb 400 pF
and are not tested.
Note 1: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
2: Negative current is defined as coming out of the pin.

PIC14000
13.3 Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS 3. TCC:ST (I2C specifications only)
2. TppS 4. Ts (I2C specifications only)
F Frequency T Time
Lowercase subscripts (pp) and their meanings:
pp
ck CLKOUT osc OSC1
di SDI t0 T0CKI
io I/O port
mc MCLR
Uppercase letters and their meanings:
F Fall P Period
H High R Rise
I Invalid (Hi-impedance) V Valid
L Low Z Hi-impedance
I2C only
AA output access High High
BUF Bus free Low Low
TCC:ST (I2C specifications only)
CC
HD Hold SU Setup
ST
DAT DATA input hold STO STOP condition
STA START condition

PIC14000
13.4 Timing Diagrams and Specifications
FIGURE 13-1: EXTERNAL CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
OSC1
1 3 3 4 4
2
CLKOUT
TABLE 13-1: EXTERNAL CLOCK TIMING REQUIREMENTS
Parameter Sym Characteristic Min Typ Max Units Conditions

No.
FOSC External CLKIN Frequency (Note 1) DC 4 MHz HS osc mode (PIC14000-04)

DC 20 MHz HS osc mode (PIC14000-20)
Oscillator Frequency (Note 1) 4 4 MHz HS osc mode (PIC14000-04)

4 20 MHz HS osc mode (PIC14000-20)
1 TOSC External CLKIN Period (Note 1) 250 ns HS osc mode (PIC14000-04)
50 ns HS osc mode (PIC14000-20)
Oscillator Period (Note 1) 250 250 ns HS osc mode (PIC14000-04)

50 250 ns HS osc mode (PIC14000-20)
2 TCY Instruction Cycle Time (Note 1) 200 DC ns TCY = 4/FOSC
3 TOSL, Clock in (OSC1) High or Low Time 10 ns HS oscillator
TOSH
4 TOSR, Clock in (OSC1) Rise or Fall Time 15 ns HS oscillator
TOSF
and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at min. values with an external
clock applied to the OSC1 pin.
When an external clock input is used, the Max. cycle time limit is DC (no clock) for all devices.

PIC14000
FIGURE 13-2: LOAD CONDITIONS
Load condition 1 Load condition 2
VDD/2
RL
CL CL
Pin Pin
VSS VSS
RL = 464
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output

PIC14000
FIGURE 13-3: CLKOUT AND I/O TIMING
Q4 Q1 Q2 Q3
OSC1
11
10
CLKOUT
13 12
19 18
14 16
I/O Pin
(input)
17 15
I/O Pin old value new value

(output)
20, 21
Note: Refer to Figure 13-2 for load conditions
TABLE 13-2: CLKOUT AND I/O TIMING REQUIREMENTS

No.
10 TosH2ckL OSC1 to CLKOUT 15 30 ns Note 1
11 TosH2ckH OSC1 to CLKOUT 15 30 ns Note 1
12 TckR CLKOUT rise time 5 15 ns Note 1
13 TckF CLKOUT fall time 5 15 ns Note 1
14 TckL2ioV CLKOUT to Port out valid 0.5TCY+20 ns Note 1
15 TioV2ckH Port in valid before CLKOUT 0.25 TCY+25 ns Note 1
16 TckH2ioI Port in hold after CLKOUT 0 ns Note 1
17 TosH2ioV OSC1 (Q1 cycle) to Port out valid 80 - 100 ns
18 TosH2ioI OSC1 (Q2 cycle) to Port input invalid 100 ns
(I/O in hold time)
19 TioV2osH Port input valid to OSC1 (I/O in setup 0 ns
time)
20 TioR Port output rise time 10 25 ns
21 TioF Port output fall time 10 25 ns
22 Tinp PBTN pin high or low time 20 ns IN mode
only
23 Trbp RC<7:4> change INT high or low time 20 ns
and are not tested.
These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in IN Mode where CLKOUT output is 4 x TOSC

PIC14000
FIGURE 13-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER (HS MODE) AND
POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Timeout
32
OSC
Timeout
Internal
RESET
Watchdog
Timer
RESET
31
34
I/O Pin
TABLE 13-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS

No.
30 TmcL MCLR Pulse Width (low) 100 ns VDD = 5V, -40C to +85C
31 TWDT Watchdog Timer Timeout Period 7* 18 33* ms VDD = 5V, -40C to +85C
(No Prescaler)
ss(WDT) Supply Sensitivity -12.6 %/V TA = 25C
tc(WDT) Temperature Coefficient 0.5 %/C VDD = 5V

32 TOST Oscillation Start-up Timer Period 1024 TOSC ms TOSC = OSC1 period
8 TOSC ms IN osc mode
33 TPWRT Power up Timer Period 28* 72 132* ms VDD = 5V, -40C to +85C
34 TIOZ I/O High Impedance from MCLR 100 ns
Low
and are not tested.

PIC14000
FIGURE 13-5: TIMER0 CLOCK TIMINGS
T0CKI
40 41
42
Note: Refer to Figure 13-2 for load conditions.
TABLE 13-4: TIMER0 CLOCK REQUIREMENTS

No.
40 Tt0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20* ns
With Prescaler 10* ns

41 Tt0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20* ns
With Prescaler 10* ns

42 Tt0P T0CKI Period TCY + 40* ns N = prescale value
N (1, 2, 4, ..., 256)
and are not tested.

PIC14000
FIGURE 13-6: I2C BUS START/STOP BITS TIMING
SCL
91
81 93
83
90
80 92
82
SDA
START STOP
Condition Condition
TABLE 13-5: I2C BUS START/STOP BITS REQUIREMENTS

No.
90 TSU:STA START condition 100 KHZ mode 4700 Only relevant for repeated
ns START condition
Setup time 400 KHz mode 600
91 THD:STA START condition 100 KHz mode 4000 After this period the first clock
ns pulse is generated
Hold time 400 KHz mode 600
92 TSU:STO STOP condition 100 KHZ mode 4700
ns
Setup time 400 KHz mode 600
93 THD:STO STOP condition 100 KHz mode 4000
ns
Hold time 400 KHz mode 600

PIC14000
FIGURE 13-7: I2C BUS DATA TIMING
103
93 100
90 102
92
101
91
SCL
90
80
106
96
107
97
91
81 92
82
SDA
IN
100
110
109
99 109
99
SDA
OUT
TABLE 13-8: I2C BUS DATA REQUIREMENTS

Parameter Sym Characteristic Min Max Units Conditions
No.
100 THIGH Clock high time 100 kHz mode 4.0 s PIC14000 must operate at a
minimum of 1.5 MHz
400 kHz mode 0.6 s PIC14000 must operate at a
minimum of 10 MHz
I2C Module 1.5 TCY
101 TLOW Clock low time 100 kHz mode 4.7 s PIC14000 must operate at a
minimum of 1.5 MHz
400 kHz mode 1.3 s PIC14000 must operate at a
minimum of 10 MHz
I2C Module 1.5 TCY
102 TR SDA and SCL rise 100 kHz mode 1000 ns
time 400 kHz mode 20+0.1 Cb 300 ns Cb is specified to be from
10-400 pF
103 TF SDA and SCL fall 100 kHz mode 300 ns
time 400 kHz mode 20+0.1 Cb 300 ns Cb is specified to be from
10-400 pF
90 TSU:STA START condition 100 kHz mode 4.7 s Only relevant for repeated
setup time 400 kHz mode 0.6 s START condition
91 THD:STA START condition hold 100 kHz mode 4.0 s After this period the first clock
time 400 kHz mode 0.6 s pulse is generated
106 THD:DAT Data input hold time 100 kHz mode 0 ns
400 kHz mode 0 0.9 s
107 TSU:DAT Data input setup time 100 kHz mode 250 ns Note 2
400 kHz mode 100 ns
92 TSU:STO STOP condition setup 100 kHz mode 4.7 s
time 400 kHz mode 0.6 s
109 TAA Output valid from 100 kHz mode 3500 ns Note 1
clock 400 kHz mode ns
110 TBUF Bus free time 100 kHz mode 4.7 s Time the bus must be free
400 kHz mode 1.3 s before a new transmission
can start
Cb Bus capacitive loading 400 pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of STARTs or STOPs.
2: A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement
tSU:DAT250ns must then be met. This will automatically be the case if the device does not stretch the LOW
period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the
next data bit to the SDA line TR max.+tSU:DAT=1000+250=1250 ns (according to the standard-mode I2C
bus specification) before the SCL line is released.

PIC14000
13.5 DC and AC Characteristics Graphs FIGURE 13-10: TYPICAL IPD3 vs VDD AT 25C
and Tables for PIC14000
FIGURE 13-9: TYPICAL IPD4 VS VDD AT 25C

TO BE DETERMINED.
TO BE DETERMINED.
FIGURE 13-11: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN HS MODE) vs VDD
3.60
3.40
3.20
)
3.00 5C
to 8
40
C
2.80 x (-
Ma YP 5C
)
CT to 8
2.60 25 C
(-40
VTH (Volts)
2.40 Min
2.20
2.00
1.80
1.60
1.40
1.20
1.00
3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
VDD (Volts)

PIC14000
FIGURE 13-12: TYPICAL OPERATING SUPPLY CURRENT VS FREQ (EXT CLOCK, 25C)
10,000
6.0
5.5
5.0
4.5
4.0
3.5
3.0
1,000
IDD (A)
100
10
1
10,000 100,000 1,000,000 10,000,000 100,000,000
Frequency (Hz)
FIGURE 13-13: MAXIMUM OPERATING SUPPLY CURRENT VS FREQ (EXT CLOCK, -40 TO +85C)
TO BE DETERMINED.

PIC14000
FIGURE 13-14: MAXIMUM IPD1 VS FREQ (EXT CLOCK, -40 TO +85C)
TO BE DETERMINED.
FIGURE 13-15: WATCHDOG TIMER TIME-OUT PERIOD (TWDT) VS. TEMPERATURE (TYPICAL)
VDD=5V
24
22
WDT Time-Out Period (no Prescaler, mSec)
20
18
16
14
12
10
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Temperature (C)

PIC14000
FIGURE 13-16: WDT TIMER TIME-OUT FIGURE 13-18: IOH VS VOH, VDD = 3V*
PERIOD VS VDD
0
50.0
45.0 -5
40.0 C
Min @ +85
35.0 -10
IOH (mA)
WDT period (ms)
30.0 25C
Ma
x, 8 Typ @
5C
-15
25.0 Max,
70C
20.0 Typ,
25C
-20
-40C
15.0 Max @
Min, 0C
10.0
-25
Min, -40C
0 0.5 1 1.5 2 2.5 3
5.0 V OH (Volts)
2 3 4 5 6 7
V DD (Volts)
FIGURE 13-19: IOH VS VOH, VDD = 5V*
FIGURE 13-17: TRANSCONDUCTANCE (GM)
0
OF HS OSCILLATOR VS VDD
-5
9000
-10
8000
-15
7000
C
0
IOH (mA)
-4
-20
x,
Min @ 85C
Ma
6000
-25
gm (A/V)
5000 Typ @ 25C

-30
4000
C
, 25 -35
Typ
3000
-40
8 5C Max @ -40C
Min,
2000 -45
1000
-50
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0 VOH (Volts)
2 3 4 5 6 7
VDD (Volts)
*NOTE: All pins except RC6, RC7, RD0, RD1,OSC2

PIC14000
FIGURE 13-20: IOL VS VOL, VDD = 3V* FIGURE 13-21: IOL VS VOL, VDD = 5V*
35 90
Min @ -40C 80
30 Min @ -40C
70
25
60
Typ @ 25C Typ @ 25C
20
IOL (mA)
50
IOL (mA)
Min @ +85C
15 40
Min @ +85C
30
10
20
5
10
0
0
0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VOL (Volts)
VOL (Volts)
*NOTE: All pins except OSC2

PIC14000
14.0 ANALOG SPECIFICATIONS: PIC14000-04 (COMMERCIAL, INDUSTRIAL)
Operating Temperature: -40C TA +85C for industrial
VDD range: 2.7V (min) to 6.0V (max) unless otherwise stated.
Characteristic Sym. Min. Typ. Max. Units Conditions Notes
Bandgap Voltage Reference

Output Voltage vo(vref) 1.14 1.19 1.24 V
Turn-on Settling Time to < 0.1% ton(vref) 1 10 ms REFOFF bit in SLPCON 1
register 0
Temperature Coefficient tc(vref) 50 ppm/C Measured from 25C to 1
-40C, +85C
Temperature Coefficient tc(vref) 20 ppm/C Measured from 25C to 1
0C, +70C
Supply Sensitivity ss(vref) 0.04 %/V From VDDmin to VDDmax 1
Operating Current (on) idd(vref) 20 30 A REFOFF = 0 2
Operating Current (off) idd(vref) 0 A REFOFF = 1 2
Programmable Current Source

Output Current io(cdac) CDAC pin = 0V 3
18.75 33.75 48.75 A ADCON1<7:4> = 1111b
(full-scale)
1.25 2.25 3.25 A ADCON1<7:4> = 0001b
(1 LSB)
-0.5 0 0.5 A ADCON1<7:4> = 0000b
(zero-scale)
Resolution res(cdac) 1.25 2.25 3.25 A 1 LSB
Relative accuracy (linearity racc(cdac) -1/2 +1/2 lsb CDAC = 0V
error)
Turn-on Settling Time to < 0.1% ton(cdac) 1 10 ms Bias generator (reference) turn-on 1
(reference start-up) time
(REFOFF 1 0)
Turn-on Settling Time to < 0.1% ton(cdac) 1 10 s REFOFF = 0 (constant), 1
(reference already on and ADCON1<7:4> 0000b 1111b
stable)
Temperature Coefficient tc(cdac) 0.1 %/C Measured from 25C to Tmin, Tmax 1
Supply Sensitivity ss(cdac) 0.2 %/V From VDDmin to VDDmax 1
Output Voltage Sensitivity vs(cdac) -0.1 -0.01 %/V CDAC pin voltage = 0V to VDD -
1.4V
Output Voltage Range vo(cdac) 0 VDD-1.4 V
Operating Current (A/D on) idd(cdac) 50 70 A ADCON1<7:4> = 1111b 2
Operating Current (A/D off) idd(cdac) 0 A REFOFF = 1, ADOFF = 1 2
Temperature Sensor
Output Voltage vo(temp) 0.92 1.05 1.18 V TA = 25C
Supply Sensitivity ss(temp) 0.2 %/V From VDDmin to VDDmax 1
Temperature Coefficient KTC 3.2 3.65 4.1 mV/C Measured from 25C to Tmax.
Includes 2C temperature
calibration tolerance

PIC14000
Temperature Sensor (continued)

Output Linearity lin(temp) TBD 1
Operating Current (sensor on) idd(temp) 150 250 A TEMPOFF = 0 2
Operating Current (sensor off) idd(temp) 0 A TEMPOFF = 1 2
Slope Reference Voltage Divider

Output Voltage (SREFHI) voh(sref) 1.14 1.19 1.24 V
Output Voltage (SREFLO) vol(sref) 0.10 0.13 0.16 V
Slope Reference Calibration KREF 0.09 0.126 0.16 TA = 25C, VDD = 5V
Factor
KREF Supply Sensitivity ss(KREF) 0.02 %/V From VDDmin to VDDmax 1
KREF Temperature Coefficient tc(KREF) 20 ppm/C From Tmin to Tmax 1
Operating Current (A/D on) idd(sref) 55 85 A ADOFF = 0 2
Operating Current (A/D off) idd(sref) 0 A ADOFF = 1 2
A/D Comparator
Input Offset Voltage ioff(adc) -10 2 10 mV Measured over common-mode
range
Input Common Mode Voltage cmr(adc) 0 VDD-1.4 V
Range
Differential Voltage Gain gain(adc) 100 dB 1
Common Mode Rejection Ratio cmrr(adc) 80 dB VDD = 5V, TA = 25C, over 1
common-mode range
Power Supply Rejection Ratio psrr(adc) 70 dB TA = 25C, VDDmin to VDDmax 1
Operating Current (A/D on) idd(adc) 40 65 A ADOFF = 0 2
Operating Current (A/D off) 0 A ADOFF = 1 2
Programmable Reference(s)
Upper Range TA = 25C
Output Voltage vo(pref) 0.627 0.792 0.957 V PREFx<7:0> = 7Fh
(127 decimal), max
0.418 0.528 0.638 V PREFx<7:0> = 50h
(80 decimal), min
Coarse Resolution resc(pref) 38.0 48.0 58.0 mV PREFx<2:0> = constant
Fine Resolution resf(pref) 4.0 5.0 6.0 mV PREFx<7:3> = constant
Middle Range TA = 25C
Output Voltage vo(pref) 0.414 0.523 0.632 V PREFx<7:0> = 4F
(79 decimal), max
0.380 0.480 0.580 V PREFx<7:0> = 00h
(default), mid-point
0.342 0.432 0.522 V PREFx<7:0> = C8h
(200 decimal), min
Fine Resolution resf(pref) 0.38 0.46 0.54 mV PREFx<7:3> = constant 1

PIC14000
Programmable Reference(s) (continued)

Lower Range TA = 25C
Output Voltage vo(pref) 0.304 0.384 0.464 V PREFx<7:0> = D7h
(215 decimal), max
0.114 0.144 0.174 V PREFx<7:0> = F8h
(248 decimal), min
Fine Resolution resf(pref) 4.0 5.0 6.0 mV PREFx<7:3> = constant
Relative accuracy (linearity racc(pref) 1/2 +1/2 lsb lsb = resolution within selected
error) range
Settling Time to < 1/2 LSB ts(pref) 1 10 S PREFx<7:0> transition from 7Fh to 1
FFh
Temperature Coefficient tc(pref) 0.39 %/C From Tmin to Tmax 1
Supply Sensitivity ss(pref) 0.2 %/V From VDDmin to VDDmax 1
Operating Current (on) idd(pref) 5 10 A CMOFF = 0 2
Operating Current (off) idd(pref) 0 A CMOFF = 1 2
Low-Voltage Detector
Detect Voltage v-(lvd) 2.43 2.55 2.67 V Decreasing VDD
Release Voltage v+(lvd) 2.48 2.60 2.72 V Increasing VDD
Hysteresis vhys(lvd) 35 55 75 mV Between detect and release trip
points
Operating Current (on) idd(lvd) 15 25 A REFOFF = 0 2
Operating Current (off) idd(lvd) 0 A REFOFF = 1 2
Internal Oscillator
Frequency Range fosc(in) 3.0 4.0 5.0 MHz
Temperature Coefficient tc(in) -0.04 %/C From Tmin to Tmax 1
Supply Sensitivity ss(in) 0.8 %/V From VDDmin to VDDmax 1
Jitter jit(in) 100 ppm 3 sigma from mean 1
Start-up Time tsu(in) 8 Tcycs At Power-On Reset and exit from 4
SLEEP
Operating Current idd(in) 300 500 A 2
(oscillator on)
Operating Current idd(in) 0 A SLEEP mode, OSCOFF = 1 2
(oscillator off)
Voltage Regulator Control Output

Regulation Voltage vo(reg) 5.2 5.9 6.6 V Measured with Ivreg = 10A at TA =
25C
Temperature Coefficient tc(vreg) -0.2 %/C From Tmin to Tmax 1
Operating Current idd(vreg) 1 10 A Determined by external
(Recommended) components
Operating Current 0 If VREG pin is open

PIC14000
Programmable Reference Comparator(s)

Input Offset Voltage ioff(comp) -10 3 10 mV Tested at 0.5V common-mode
voltage
Input Common Mode Voltage cmr(comp) 0 VDD-1.4 V 1
Range
Differential Voltage Gain gain(comp) 80 dB 1
Common Mode Rejection Ratio cmrr(comp) 60 dB VDD = 5V, TA = 25C, over 1
common-mode range
Power Supply Rejection Ratio psrr(comp) 55 dB TA = 25C, VDDmin to VDDmax 1
Operating Current (on) idd(comp) 10 20 A CMOFF = 0 2
Operating Current (off) idd(comp) 0 A CMOFF = 1 2
Level-Shift Network(s)
Input Current (RA1/RD5 pin) iin(lvs) -3.4 -4.8 -6.2 A TA = 25C, RA1/RD5 = 0V (SUM
pin is open)
Output Voltage vo(lvs) 0.37 0.46 0.55 V TA = 25C, RA1/RD5 = 0V, (SUM
pin is open)
Zeroing Mismatch Error zm(lvs) 0.02 % 1
Output Voltage Temperature tc(lvs) 0.39 %/C From Tmin to Tmax 1
Coefficient
Output Voltage Supply ss(lvs) 0.2 %/V From VDDmin to VDDmax 1
Sensitivity
Operating Current (network on) idd(lvs) 5 15 A LSOFF = 0 2
Operating Current (network off) idd(lvs) 0 A LSOFF = 1 2

PIC14000
Calibration Accuracy All parameters calibrated at VDD = 3, 5
5V, TA = 25C unless noted.
Accuracy
Parameter Sym. Resolution Units Typ Max Conditions Notes
Slope Reference Ratio KREF 0.015% .02%
Bandgap Reference Voltage KBG 10 V .01%
Temperature Sensor Output VTHERM 20 V .02%
Voltage
Temperature Sensor Slope KTC 0.33 V/C 6.7% Calibrated at 25C and Tmax
Coefficient
Internal Oscillator Frequency FOSC 10.0 kHz 0.14%
Watchdog Timer Time-out TWDT 1 ms 0.5 ms
Period
Notes for the analog specifications:
Note 1: This parameter is characterized but not tested.
Note 2: IDD values of individual analog module cannot be tested independently but are characterized.
Note 3: Calibration temp accuracy is 1C typical, 2C max.
Note 4: Guaranteed by design.
Note 5: Refer to AN621 for further information on calibration parameters and accuracy.
Calculations:
Temperature coefficients are calculated as:
tc = (value @TMAX - value @TMIN) / ((TMAX-TMIN) * Average(value @TMAX,value @TMIN))
Temperature coefficient for the internal temperature sensor is calculated as:
tc sensor = (sensor voltage @ TMAX - sensor voltage @ 25C) / (TMAX - 25C)
Temperature coefficients for the bandgap reference and programmable current source are calculated as
the larger TC from 25C to either TMIN or TMAX
Supply sensitivities are calculated as:
ss = (value@VDDMAX - value@VDDMIN)/((VDDMAX - VDDMIN)*
Average(value@VDDMAX, value@VDDMIN))
Programmable current source output sensitivity is calculated as:
vs = (value@(VDD - 1.4V) - value @ 0V)/(VDD - 1.4V) *
Average(value@(VDD - 1.4V), value @ 0V)

PIC14000
FIGURE 14-1: BANDGAP REFERENCE OUTPUT VOLTAGE vs. TEMPERATURE
(TYPICAL DEVICES SHOWN)
1.194
1.192
Reference Output (Volts) 1.190
1.188
1.186
1.184
1.182
1.180
1.178
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Temperature (C)
FIGURE 14-2: PROGRAMMABLE CURRENT SOURCE vs. TEMPERATURE

2.7
2.5
Current Source Output (uA)
2.3
2.1
1.9
1.7
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Temperature (C)

PIC14000
FIGURE 14-3: TEMPERATURE SENSOR OUTPUT VOLTAGE vs. TEMPERATURE
1.4
1.3
Temperature Sensor Output (Volts)
1.2
1.1
1.0
0.9
0.8
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Temperature (C)
FIGURE 14-4: SLOPE REFERENCE RATIO (KREF) vs. SUPPLY VOLTAGE

0.1260
0.1258
Slope Reference Ratio (KREF)
0.1256
0.1254
0.1252
0.1250
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Supply Voltage (Volts)

PIC14000
FIGURE 14-5: SLOPE REFERENCE RATIO (KREF) vs. TEMPERATURE
0.1260
0.1258
0.1256
Slope Reference Ratio (KREF)
0.1254
0.1252
0.1250
0.1248
0.1246
-40 -20 0 20 40 60 80 100
Temperature (C)
Fixed Bandgap Reference Voltage
FIGURE 14-6: PROGRAMMABLE REFERENCE OUTPUT vs. TEMPERATURE (TYPICAL)

0.7
Programmable Reference Output (Volts)
0.6
0.5
0.4
0.3
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
Temperature (C)

PIC14000
FIGURE 14-7: INTERNAL RC OSCILLATOR FREQUENCY vs. SUPPLY VOLTAGE
4.3
4.2
4.1
Oscillator Frequency (MHz)
4.0
3.9
3.8
3.7
3.6
3.5
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Supply Voltage (Volts)
FIGURE 14-8: INTERNAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE

4.4
4.3
4.2
Oscillator Frequency (MHz)
4.1
4.0
3.9
3.8
3.7
3.6
3.5
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100
Temperature (C)

PIC14000
NOTES:

A.1
PIC14000 Devices

Clock Memory Peripherals Features
)
) rds
Hz wo s)
(M 4 le( T)
n (x1 du R g
t io o in
ra ry M SA m
pe o M ,U )
O em ) W 2C r ts am
of M es /P I/I t ol gr
y yt e r e rte els s ( V ro t p
nc am (b s) ar ( SP Po n e l P hi
u e r e( p ) e o nv an rc g e i a se -c
o g y u l s v u r e n
eq or om rt( la C Ch So an Se R O
Fr Pr em od /C /D s) R it ut
M M r e l Po e lS A e u e u - o n al es es
um M u l l e - r rr
pt ins
g rc o
ti ur ag
im er pt ia ra P lta Ci wn
ax P RO ata
i m a er a l / O o - r o d di eat ck
M E D T C S P S (h
op igh Inte
I V In B A F Pa
Internal Oscillator,
Bandgap Reference,
APPENDIX A: PIC16/17 MICROCONTROLLERS
Preliminary
Temperature Sensor,
Calibration Factors,
TMR0 I2C/ 28-pin DIP, SOIC, SSOP
PIC14000 20 4K 192 14 11 22 2.7-6.0 Yes Low Voltage Detector,
ADTMR SMBus (.300 mil)
SLEEP, HIBERNATE,
Comparators with
Programmable References

(2)
DS40122B-page 133
PIC14000
A.2
DS40122B-page 134
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PIC16C52 4 384 25 TMR0 12 2.5-6.25 33 18-pin DIP, SOIC
PIC16C54 20 512 25 TMR0 12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP
PIC16C54A 20 512 25 TMR0 12 2.0-6.25 33 18-pin DIP, SOIC; 20-pin SSOP
PIC16CR54A 20 512 25 TMR0 12 2.0-6.25 33 18-pin DIP, SOIC; 20-pin SSOP
Preliminary
PIC16C55 20 512 24 TMR0 20 2.5-6.25 33 28-pin DIP, SOIC, SSOP
PIC16C56 20 1K 25 TMR0 12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP
PIC16C57 20 2K 72 TMR0 20 2.5-6.25 33 28-pin DIP, SOIC, SSOP
PIC16CR57B 20 2K 72 TMR0 20 2.5-6.25 33 28-pin DIP, SOIC, SSOP
PIC16C58A 20 2K 73 TMR0 12 2.0-6.25 33 18-pin DIP, SOIC; 20-pin SSOP
PIC16CR58A 20 2K 73 TMR0 12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP
All PIC16/17 Family devices have Power-On Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.

A.3

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PIC16CXXX Family of Devices
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M E D T C I I I Vo Br Pa
PIC16C554 20 512 80 TMR0 3 13 2.5-6.0 18-pin DIP, SOIC; 20-pin SSOP
PIC16C556 20 1K 80 TMR0 3 13 2.5-6.0 18-pin DIP, SOIC; 20-pin SSOP
PIC16C558 20 2K 128 TMR0 3 13 2.5-6.0 18-pin DIP, SOIC; 20-pin SSOP
Preliminary
PIC16C620 20 512 80 TMR0 2 Yes 4 13 2.5-6.0 Yes 18-pin DIP, SOIC; 20-pin SSOP
PIC16C621 20 1K 80 TMR0 2 Yes 4 13 2.5-6.0 Yes 18-pin DIP, SOIC; 20-pin SSOP
PIC16C622 20 2K 128 TMR0 2 Yes 4 13 2.5-6.0 Yes 18-pin DIP, SOIC; 20-pin SSOP
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O
current capability.
All PIC16C6XXX Family devices use serial programming with clock pin RB6 and data pin RB7.
DS40122B-page 135
PIC14000
A.4
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DS40122B-page 136
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PIC16C62 20 2K 128 TMR0, 1 SPI/I2C 7 22 2.5-6.0 Yes 28-pin SDIP, SOIC, SSOP
TMR1, TMR2
PIC16C62A(1) 20 2K 128 TMR0, 1 SPI/I2C 7 22 2.5-6.0 Yes Yes 28-pin SDIP, SOIC, SSOP
TMR1, TMR2
PIC16CR62(1) 20 2K 128 TMR0, 1 SPI/I2C 7 22 2.5-6.0 Yes Yes 28-pin SDIP, SOIC, SSOP
TMR1, TMR2
PIC16C63 20 4K 192 TMR0, 2 SPI/I2C, 10 22 2.5-6.0 Yes Yes 28-pin SDIP, SOIC
TMR1, TMR2 USART
PIC16CR63(1) 20 4K 192 TMR0, 2 SPI/I2C, 10 22 2.5-6.0 Yes Yes 28-pin SDIP, SOIC
TMR1, TMR2 USART
Preliminary
PIC16C64 20 2K 128 TMR0, 1 SPI/I2C Yes 8 33 2.5-6.0 Yes 40-pin DIP;
TMR1, TMR2 44-pin PLCC, MQFP
PIC16C64A(1) 20 2K 128 TMR0, 1 SPI/I2C Yes 8 33 2.5-6.0 Yes Yes 40-pin DIP;
TMR1, TMR2 44-pin PLCC, MQFP, TQFP
PIC16CR64(1) 20 2K 128 TMR0, 1 SPI/I2C Yes 8 33 2.5-6.0 Yes Yes 40-pin DIP;
TMR1, TMR2 44-pin PLCC, MQFP, TQFP
PIC16C65 20 4K 192 TMR0, 2 SPI/I2C, Yes 11 33 2.5-6.0 Yes 40-pin DIP;
TMR1, TMR2 USART 44-pin PLCC, MQFP
PIC16C65A(1) 20 4K 192 TMR0, 2 SPI/I2C, Yes 11 33 2.5-6.0 Yes Yes 40-pin DIP;
TMR1, TMR2 USART 44-pin PLCC, MQFP, TQFP
PIC16CR65(1) 20 4K 192 TMR0, 2 SPI/I2C, Yes 11 33 2.5-6.0 Yes Yes 40-pin DIP;
All PIC16/17 family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect, and high I/O current capability.
All PIC16C6X family devices use serial programming with clock pin RB6 and data pin RB7.
Note 1: Please contact your local sales office for availability of these devices.

A.5

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PIC16C710 20 512 36 TMR0 4 4 13 2.5-6.0 Yes Yes 18-pin DIP, SOIC;
20-pin SSOP
PIC16C71 20 1K 36 TMR0 4 4 13 2.5-6.0 Yes 18-pin DIP, SOIC
PIC16C711 20 1K 68 TMR0 4 4 13 2.5-6.0 Yes Yes 18-pin DIP, SOIC;
20-pin SSOP
PIC16C72 20 2K 128 TMR0, 1 SPI/I2C 5 8 22 2.5-6.0 Yes Yes 28-pin SDIP, SOIC, SSOP
TMR1, TMR2
Preliminary
PIC16C73 20 4K 192 TMR0, 2 SPI/I2C, 5 11 22 2.5-6.0 Yes 28-pin SDIP, SOIC
TMR1, TMR2 USART
PIC16C73A(1) 20 4K 192 TMR0, 2 SPI/I2C, 5 11 22 2.5-6.0 Yes Yes 28-pin SDIP, SOIC
TMR1, TMR2 USART
PIC16C74 20 4K 192 TMR0, 2 SPI/I2C, Yes 8 12 33 2.5-6.0 Yes 40-pin DIP;
TMR1, TMR2 USART 44-pin PLCC, MQFP
PIC16C74A(1) 20 4K 192 TMR0, 2 SPI/I2C, Yes 8 12 33 2.5-6.0 Yes Yes 40-pin DIP;
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current
capability.
All PIC16C7X Family devices use serial programming with clock pin RB6 and data pin RB7.
DS40122B-page 137
PIC14000
A.6
DS40122B-page 138
PIC14000

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PIC16C84 10 1K 36 64 TMR0 4 13 2.0-6.0 18-pin DIP, SOIC
PIC16F84(1) 10 1K 68 64 TMR0 4 13 2.0-6.0 18-pin DIP, SOIC
Preliminary
PIC16CR84(1) 10 1K 68 64 TMR0 4 13 2.0-6.0 18-pin DIP, SOIC
PIC16F83(1) 10 512 36 64 TMR0 4 13 2.0-6.0 18-pin DIP, SOIC
PIC16CR83(1) 10 512 36 64 TMR0 4 13 2.0-6.0 18-pin DIP, SOIC
All PIC16/17 family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect, and
high I/O current capability.
All PIC16C8X family devices use serial programming with clock pin RB6 and data pin RB7.

A.7

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PIC16C923 8 4K 176 TMR0, 1 SPI/I2C 4 Com 8 25 27 3.0-6.0 Yes 64-pin SDIP(1), TQFP,
TMR1, TMR2 32 Seg 68-pin PLCC, DIE
PIC16C924 8 4K 176 TMR0, 1 SPI/I2C 5 4 Com 9 25 27 3.0-6.0 Yes
Preliminary
64-pin SDIP(1), TQFP,
TMR1, TMR2 32 Seg 68-pin PLCC, DIE
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.
All PIC16CXX Family devices use serial programming with clock pin RB6 and data pin RB7.
Note 1: Please contact your local Microchip representative for availability of this package.
DS40122B-page 139
PIC14000
A.8
DS40122B-page 140
PIC14000
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PIC17C42 25 2K 232 TMR0,TMR1, 2 2 Yes Yes 11 33 4.5-5.5 55 40-pin DIP;

TMR2,TMR3 44-pin PLCC, MQFP
PIC17C42A 25 2K 232 TMR0,TMR1, 2 2 Yes Yes Yes 11 33 2.5-5.5 58 40-pin DIP;
Preliminary
PIC17CR42 25 2K 232 TMR0,TMR1, 2 2 Yes Yes Yes 11 33 2.5-5.5 58 40-pin DIP;
PIC17C43 25 4K 454 TMR0,TMR1, 2 2 Yes Yes Yes 11 33 2.5-6.0 58 40-pin DIP;
TMR2,TMR3 44-pin PLCC, TQFP, MQFP
PIC17CR43 25 4K 454 TMR0,TMR1, 2 2 Yes Yes Yes 11 33 2.5-6.0 58 40-pin DIP;
PIC17C44 25 8K 454 TMR0,TMR1, 2 2 Yes Yes Yes 11 33 2.5-6.0 58 40-pin DIP;
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.

PIC14000
A.9 Pin Compatibility
Devices that have the same package type and VDD,
VSS and MCLR pin locations are said to be pin
compatible. This allows these different devices to
operate in the same socket. Compatible devices may
only requires minor software modification to allow
proper operation in the application socket
(ex., PIC16C56 and PIC16C61 devices). Not all
devices in the same package size are pin compatible;
for example, the PIC16C62 is compatible with the
PIC16C63, but not the PIC16C55.
Pin compatibility does not mean that the devices offer
the same features. As an example, the PIC16C54 is
pin compatible with the PIC16C71, but does not have
an A/D converter, weak pull-ups on PORTB, or
interrupts.
TABLE A-1: PIN COMPATIBLE DEVICES
Pin Compatible Devices Package
PIC12C508, PIC12C509 8-pin
PIC16C54, PIC16C54A, 18-pin

PIC16CR54A, 20-pin
PIC16C56,
PIC16C58A, PIC16CR58A,
PIC16C61,
PIC16C554, PIC16C556, PIC16C558
PIC16C620, PIC16C621, PIC16C622,
PIC16C710, PIC16C71, PIC16C711,
PIC16C83, PIC16CR83,
PIC16C84, PIC16C84A, PIC16CR84
PIC16C55, 28-pin
PIC16C57, PIC16CR57B
PIC16C62, PIC16CR62, PIC16C62A, PIC16C63, 28-pin

PIC16C72, PIC16C73, PIC16C73A
PIC16C64, PIC16CR64, PIC16C64A, 40-pin

PIC16C65, PIC16C65A,
PIC16C74, PIC16C74A
PIC17C42, PIC17C43, PIC17C44 40-pin

PIC14000
NOTES:

PIC14000
INDEX ADDWF ...................................................................... 93
ANDLW....................................................................... 93
A ANDWF ...................................................................... 93
Absolute Maximum Ratings ............................................. 107 BCF ............................................................................ 94
ADDLW Instruction ............................................................ 93 BSF............................................................................. 94
ADDWF Instruction ............................................................ 93 BTFSC........................................................................ 94
ALU ...................................................................................... 7 BTFSS ........................................................................ 95
ANDLW Instruction ............................................................ 93 CALL........................................................................... 95
ANDWF Instruction ............................................................ 93 CLRF .......................................................................... 95
Application Notes CLRW ......................................................................... 95
AN607 ........................................................................ 80 CLRWDT .................................................................... 96
Assembler ........................................................................ 104 COMF ......................................................................... 96
B DECF.......................................................................... 96
BCF Instruction .................................................................. 94 DECFSZ ..................................................................... 96
Block Diagram GOTO ......................................................................... 97
PIC16C74 .................................................................... 8 INCF ........................................................................... 97
Block Diagrams INCFSZ....................................................................... 97
On-Chip Reset Circuit ................................................ 79 IORLW........................................................................ 97
BSF Instruction .................................................................. 94 IORWF........................................................................ 98
BTFSC Instruction.............................................................. 94 MOVF ......................................................................... 98
BTFSS Instruction.............................................................. 95 MOVLW ...................................................................... 98
C MOVWF...................................................................... 98
C Compiler (MP-C) .......................................................... 105 NOP............................................................................ 99
CALL Instruction ................................................................ 95 OPTION...................................................................... 99
Carry bit ............................................................................... 7 RETFIE....................................................................... 99
Clocking Scheme ............................................................... 11 RETLW ....................................................................... 99
CLRF Instruction ................................................................ 95 RETURN................................................................... 100
CLRW Instruction............................................................... 95 RLF........................................................................... 100
CLRWDT Instruction .......................................................... 96 RRF .......................................................................... 100
Code Examples SLEEP ...................................................................... 100
Saving STATUS and W registers in RAM.................. 85 SUBLW..................................................................... 101
COMF Instruction............................................................... 96 SUBWF..................................................................... 101
Compatibility, upward........................................................... 3 SWAPF..................................................................... 102
computed goto ................................................................... 23 TRIS ......................................................................... 102
D XORLW .................................................................... 102
DC Characteristics ........................................................... 108 XORWF .................................................................... 102
DECF Instruction................................................................ 96 Section........................................................................ 91
DECFSZ Instruction ........................................................... 96 Summary Table .......................................................... 92
Development Support ...................................................... 103 INTCON.............................................................................. 19
Development Tools .......................................................... 103 IORLW Instruction .............................................................. 97
Digit Carry bit ....................................................................... 7 IORWF Instruction .............................................................. 98
E L
Electrical Characteristics.................................................. 107 Loading of PC..................................................................... 23
F M
Family of Devices MCLR ................................................................................. 79
PIC14XXX................................................................ 133 Memory Organization
PIC16C5X ................................................................ 134 Data Memory .............................................................. 14
PIC16C62X .............................................................. 134 Memory Organization ................................................. 13
PIC16C6X ................................................................ 136 Program Memory........................................................ 13
PIC16C7X ................................................................ 137 MOVF Instruction................................................................ 98
PIC16C8X ................................................................ 138 MOVLW Instruction ............................................................ 98
PIC17CXX................................................................ 140 MOVWF Instruction ............................................................ 98
FSR.................................................................................... 24 MPASM Assembler .................................................. 103, 104
Fuzzy Logic Dev. System (fuzzyTECH-MP) ........... 103, 105 MP-C C Compiler ............................................................. 105
G MPSIM Software Simulator ...................................... 103, 105
GOTO Instruction............................................................... 97 N
I NOP Instruction .................................................................. 99
IDLE_MODE ...................................................................... 54 O
INCF Instruction ................................................................. 97 Opcode ............................................................................... 91
INCFSZ Instruction ............................................................ 97 OPTION.............................................................................. 18
Instruction Cycle ................................................................ 11 OPTION Instruction ............................................................ 99
Instruction Flow/Pipelining ................................................. 11 P
Instruction Format .............................................................. 91 Paging, Program Memory................................................... 23
Instruction Set PCL..................................................................................... 23
ADDLW ...................................................................... 93 PCLATH ............................................................................. 23

PIC14000
PCON................................................................................. 22 LIST OF EXAMPLES
PD ...................................................................................... 79
Example 3-1: Instruction Pipeline Flow ........................... 11
PICDEM-1 Low-Cost PIC16/17 Demo Board........... 103, 104
Example 4-1: Call Of A Subroutine In Page 1
PICDEM-2 Low-Cost PIC16CXX Demo Board ........ 103, 104
from Page 0............................................... 23
PICDEM-3 Low-Cost PIC16C9XXX Demo Board............ 104
Example 4-2: Indirect Addressing .................................... 24
PICMASTER RT In-Circuit Emulator............................. 103
Example 5-1: Initializing PORTA ..................................... 25
PICSTART Low-Cost Development System ................. 103
Example 5-2: Initializing PORTC ..................................... 27
PIE1 ................................................................................... 20
Example 5-3: Initializing PORTD ..................................... 35
Pin Compatible Devices ................................................... 141
Example 5-4: Read Modify Write Instructions
PIR1 ................................................................................... 21
On An I/O Port ........................................... 35
POR
Example 6-1: Changing Prescaler (TIMER0WDT) ....... 40
Oscillator Start-up Timer (OST) ................................. 80
Example 6-2: Changing Prescaler (WDTTIMER0) ....... 40
Power-on Reset (POR) .............................................. 80
Example 10-1: Saving STATUS and W Registers
Power-up Timer (PWRT) ........................................... 80
in RAM........................................................ 84
TO .............................................................................. 79
Prescaler ............................................................................ 39 LIST OF FIGURES
PRO MATE Universal Programmer............................... 103
Figure 3-1: PIC14000 Block Diagram ............................ 8
R Figure 3-2: Clock/Instruction Cycle .............................. 11
RCV_MODE....................................................................... 54 Figure 4-1: PIC14000 Program Memory Map
Read Modify Write.............................................................. 35 and Stack .................................................. 13
Register File ....................................................................... 14 Figure 4-2: Register File Map ...................................... 14
Reset.................................................................................. 79 Figure 4-3: Status Register .......................................... 17
RETFIE Instruction............................................................. 99 Figure 4-4: Option Register ......................................... 18
RETLW Instruction ............................................................. 99 Figure 4-5: INTCON Register ...................................... 19
RETURN Instruction......................................................... 100 Figure 4-6: PIE1 Register ............................................ 20
RLF Instruction................................................................. 100 Figure 4-7: PIR1 Register ............................................ 21
RRF Instruction ................................................................ 100 Figure 4-8: PCON Register .......................................... 22
S Figure 4-9: Loading of PC In Different Situations ........ 23
Saving W register and STATUS in RAM............................ 85 Figure 4-10: Indirect/indirect Addressing ....................... 24
SLEEP................................................................................ 79 Figure 5-1: PORTA Block Diagram .............................. 25
SLEEP Instruction ............................................................ 100 Figure 5-2: PORTA Data Register ............................... 26
Software Simulator (MPSIM)............................................ 105 Figure 5-3: Block Diagram of PORTC<7:6> Pins ........ 27
Special FUNCTION Registers............................................ 15 Figure 5-4: Block Diagram of PORTC<5:4> Pins ........ 28
SSP Figure 5-5: Block Diagram of PORTC<3:0> Pins ........ 29
SSPCON.................................................................... 43 Figure 5-6: PORTC Data Register ............................... 30
SSPSTAT................................................................... 42 Figure 5-7: TRISC Register ......................................... 31
Stack .................................................................................. 23 Figure 5-8: Block Diagram of PORTD<7:4> Pins ........ 32
overflows.................................................................... 23 Figure 5-9: Block Diagram oF PORTD<3:2> Pins ....... 32
underflow ................................................................... 23 Figure 5-10: Block Diagram of PORTD<1:0> Pins ........ 33
SUBLW Instruction........................................................... 101 Figure 5-11: PORTD Data Register ............................... 33
SUBWF Instruction ........................................................... 101 Figure 5-12: TRISD Register ......................................... 34
SWAPF Instruction........................................................... 102 Figure 5-13: Successive I/O OperatioN ......................... 36
T Figure 6-1: TIMER0 and Watchdog Timer
Timer0 Block Diagram ........................................... 37
TMR0 with External Clock.......................................... 39 Figure 6-2: TIMER0 Timing: Internal Clock/
Timer1 No Prescale ............................................... 38
Switching Prescaler Assignment................................ 40 Figure 6-3: TIMER0 Timing: Internal Clock/
Timing Diagrams and Specifications................................ 111 Prescale 1:2 .............................................. 38
TRIS Instruction ............................................................... 102 Figure 6-4: TIMER0 Interrupt Timing ........................... 38
W Figure 6-5: TIMER0 Timing with External Clock .......... 39
Watchdog Timer (WDT) ..................................................... 79 Figure 7-1: I2C Start And Stop Conditions ................... 41
X Figure 7-2: I2CSTAT: I2C Port Status Register ............ 42
XMIT_MODE...................................................................... 54 Figure 7-3: I2CCON: I2C Port Control Register ........... 43
Figure 7-4: I2C 7-bit Address Format ........................... 44
XORLW Instruction .......................................................... 102
XORWF Instruction .......................................................... 102 Figure 7-5: I2C 10-bit Address Format ......................... 44
Figure 7-6: I2C Slave-Receiver Acknowledge ............. 45
Z Figure 7-7: Sample I2C Data Transfer ......................... 45
Zero bit ................................................................................. 7 Figure 7-8: Master - Transmitter Sequence ................. 46
Figure 7-9: Master - Receiver Sequence ..................... 46
Figure 7-10: Combined Format ...................................... 46
Figure 7-11: Multi-master Arbitration (2 Masters) .......... 47
Figure 7-12: I2C Clock Synchronization ......................... 47
Figure 7-13: I2C Block Diagram ..................................... 48
Figure 7-14: I2C Waveforms For Reception
(7-bit Address) ........................................... 50

PIC14000
Figure 7-15: I2C Waveforms For Transmission Figure 13-16: WDT Timer Time-out Period vs VDD .........121
(7-bit Address) ........................................... 51 Figure 13-17: Transconductance (gm) of HS Oscillator
Figure 7-16: MISC Register ........................................... 53 vs VDD ......................................................121
Figure 7-17: Operation Of The I2C in Idle_Mode, Figure 13-18: IOH vs VOH, VDD = 3V* ............................121
RCV_Mode or Xmit_Mode ......................... 54 Figure 13-19: IOH vs VOH, VDD = 5V* ............................121
Figure 7-18: SMHOG State Machine ............................. 55 Figure 13-20: IOL vs VOL, VDD = 3V* .............................122
Figure 8-1: A/D Block Diagram .................................... 58 Figure 13-21: IOL vs VOL, VDD = 5V* .............................122
Figure 8-2: Example A/d Conversion Cycle ................. 59 Figure 14-1: Bandgap Reference Output
Figure 8-3: A/D Capture Timer (Low Byte) ................... 59 Voltage vs. Temperature
Figure 8-4: A/D Capture Timer (High Byte) .................. 59 (Typical Devices Shown) ..........................128
Figure 8-5: A/D Capture Register (Low Byte) .............. 59 Figure 14-2: Programmable Current Source
Figure 8-6: A/D Capture Register (High Byte) .............. 59 vs. Temperature
Figure 9-1: Level-shift Networks .................................. 66 (Typical Devices Shown) ..........................128
Figure 9-2: Slope Reference Divider ............................ 67 Figure 14-3: Temperature Sensor
Figure 9-3: Comparator and Programmable Output Voltage vs. Temperature
Reference Block Diagram .......................... 68 (Typical Devices Shown) ..........................129
Figure 9-4: Programmable Reference Transfer Figure 14-4: Slope Reference Ratio
Function ..................................................... 70 (KREF) vs. Supply Voltage
Figure 9-5: Comparator CONTROL Register ............... 71 (Typical Devices Shown) ..........................129
Figure 9-6: PREFA Register ........................................ 72 Figure 14-5: Slope Reference Ratio
Figure 9-7: PREFB Register ........................................ 72 (KREF) vs. Temperature
Figure 9-8: Voltage Regulator Circuit ........................... 73 (Typical Devices Shown) ..........................130
Figure 10-1: Configuration Word..................................... 75 Figure 14-6: Programmable Reference
Figure 10-2: MISC Register ........................................... 76 Output vs. Temperature (Typical) .............130
Figure 10-3: Crystal/Ceramic Resonator Operation Figure 14-7: Internal RC Oscillator Frequency
(HS OSC Configuration) ............................ 77 vs. Supply Voltage
Figure 10-4: External Clock Input Operation (Typical Devices Shown) ..........................131
(HS OSC Configuration) ............................ 77 Figure 14-8: Internal RC Oscillator Frequency
Figure 10-5: External Parallel Resonant Crystal vs. Temperature
Oscillator Circuit ......................................... 77 (Typical Devices Shown) ..........................131
Figure 10-6: External Series Resonant Crystal
Oscillator Circuit ......................................... 78 LIST OF TABLES
Figure 10-7: Simplified Block Diagram of On-chip Table 3-1: Pin Descriptions ........................................... 9
Reset Circuit .............................................. 78 Table 4-1: Calibration Data Overview.......................... 13
Figure 10-8: External Power-on Reset Circuit Table 4-2: Calibration Constant Addresses................. 14
(For Slow VDD Power-up) .......................... 80 Table 4-3: Special Function Registers for the
Figure 10-9: Interrupt Logic Schematic .......................... 82 PIC14000 ................................................... 15
Figure 10-10: External (OSC1/PBTN) Interrupt Timing .... 83 Table 5-1: Port RC0 Pin Configuration Summary........ 28
Figure 10-11: Watchdog Timer Block Diagram Table 6-1: Summary of TIMER0 Registers.................. 40
(with Timer0) .............................................. 85 Table 6-2: Registers Associated with Timer0 .............. 40
Figure 10-12: SLPCON Register ...................................... 88 Table 7-1: I2C Bus Terminology .................................. 44
Figure 10-13: Wake-up From Sleep and Hibernate Table 7-2: Data Transfer Received Byte Actions ........ 49
Through Interrupt ....................................... 88 Table 7-3: Registers Associated With I2C Operation .. 52
Figure 10-14: Typical In-system Serial Programming Table 8-1: A/D Channel Assignment ........................... 60
Connection ................................................. 90 Table 8-2: Programmable Current Source Selection... 61
Figure 11-1: General Format for Instructions ................. 91 Table 8-3: A/D Control and Status Register 0 ............. 62
Figure 13-1: External Clock Timing .............................. 111 Table 8-4: A/D Control and Status Register 1 ............. 63
Figure 13-2: Load Conditions ....................................... 112 Table 8-5: PORTA and PORTD Configuration ............ 63
Figure 13-3: CLKOUT and I/O Timing .......................... 113 Table 8-6: CDAC Capacitor Selection (Examples
Figure 13-4: Reset, Watchdog Timer, Oscillator Start-up for Full Scale of 3.5V and 1.5V) ................. 64
Timer (HS Mode) And Power-up Timer Table 9-1: Programmable Reference Coarse
Timing ...................................................... 114 Range Selection ......................................... 69
Figure 13-5: TIMER0 Clock Timings ............................ 115 Table 9-2: Programmable Reference Fine
Figure 13-6: I2C Bus Start/Stop Bits Timing ................. 116 Range Selection ......................................... 70
Figure 13-7: I2C Bus Data Timing ................................ 117 Table 10-1: Ceramic Resonators................................... 77
Figure 13-9: Typical IPD4 vs VDD ................................ 118 Table 10-2: Capacitor Selection For Crystal
Figure 13-10: Typical IPD3 vs VDD ................................ 118 Oscillator .................................................... 77
Figure 13-11: VTH (Input Threshold Voltage) Table 10-3: Status Bits And Their Significance ............. 79
of OSC1 Input (in HS Mode) vs VDD ........ 118 Table 10-4: Reset Condition For Special Registers ...... 80
Figure 13-12: Typical IDD vs Freq (Ext clock, 25C) ...... 119 Table 10-5: Reset Conditions For Registers ................. 81
Figure 13-13: Maximum, IDD vs Freq (Ext clock, Table 10-6: Summary of Power Management
-40 to +85C) .......................................... 119 Options ....................................................... 86
Figure 13-14: Maximum IPD1 vs Freq (Ext clock, Table 11-1: Opcode Field Descriptions ......................... 91
-40 to +85C) .......................................... 120 Table 11-2: PIC14000 Instruction Set ........................... 92
Figure 13-15: PIC14000 Watchdog Timer Time-Out Table 12-1: Development Tools From Microchip......... 106
Period (TWDT) vs. Temperature (Typical) 120 Table 13-1: External Clock Timing Requirements ....... 111

PIC14000
Table 13-2: CLKOUT and I/O Timing Requirements .. 113
Table 13-3: Reset, Watchdog Timer, Oscillator
Start-up Timer And Power-up Timer
Requirements .......................................... 114
Table 13-4: Timer0 Clock Requirements .................... 115
Table 13-5: I2C Bus Start/stop Bits Requirements...... 116
Table 13-8: I2C Bus Data Requirements .................... 117
Table A-1: Pin Compatible Devices ........................... 141

PIC14000
ON-LINE SUPPORT The procedure to connect will vary slightly from country
to country. Please check with your local CompuServe
Microchip provides two methods of on-line support. agent for details if you have a problem. CompuServe
These are the Microchip BBS and the Microchip World service allow multiple users various baud rates
Wide Web (WWW) site. depending on the local point of access.
Use Microchip's Bulletin Board Service (BBS) to get The following connect procedure applies in most loca-
current information and help about Microchip products. tions.
Microchip provides the BBS communication channel for
you to use in extending your technical staff with micro- 1. Set your modem to 8-bit, No parity, and One stop
controller and memory experts. (8N1). This is not the normal CompuServe setting
which is 7E1.
To provide you with the most responsive service possible,
2. Dial your local CompuServe access number.
the Microchip systems team monitors the BBS, posts
the latest component data and software tool updates, 3. Depress the <Enter> key and a garbage string will
provides technical help and embedded systems appear because CompuServe is expecting a 7E1
insights, and discusses how Microchip products pro- setting.
vide project solutions. 4. Type +, depress the <Enter> key and Host Name:
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The web site, like the BBS, is used by Microchip as a
means to make files and information easily available to 5. Type MCHIPBBS, depress the <Enter> key and you
customers. To view the site, the user must have access will be connected to the Microchip BBS.
to the Internet and a web browser, such as Netscape or In the United States, to find the CompuServe phone
Microsoft Explorer. Files are also available for FTP number closest to you, set your modem to 7E1 and dial
download from our FTP site. (800) 848-4480 for 300-2400 baud or (800) 331-7166
Connecting to the Microchip Internet Web Site for 9600-14400 baud connection. After the system
responds with Host Name:, type NETWORK, depress
The Microchip web site is available by using your the <Enter> key and follow CompuServe's directions.
favorite Internet browser to attach to:
www.microchip.com For voice information (or calling from overseas), you
may call (614) 723-1550 for your local CompuServe
The file transfer site is available by using an FTP ser- number.
vice to connect to:
ftp.mchip.com/biz/mchip Microchip regularly uses the Microchip BBS to distribute
technical information, application notes, source code,
The web site and file transfer site provide a variety of
errata sheets, bug reports, and interim patches for
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ety of Microchip specific business information is also
are accepted from the user community in general to
available, including listings of Microchip sales offices,
limit the spread of computer viruses.
distributors and factory representatives. Other data
available for consideration is: Systems Information and Upgrade Hot Line
Latest Microchip Press Releases The Systems Information and Upgrade Line provides
Technical Support Section with Frequently Asked system users a listing of the latest versions of all of
Questions Microchip's development systems software products.
Design Tips Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Device Errata
Hot Line Numbers are:
Job Postings
Microchip Consultant Program Member Listing 1-800-755-2345 for U.S. and most of Canada, and
Links to other useful web sites related to 1-602-786-7302 for the rest of the world.
Microchip Products
960513
Connecting to the Microchip BBS
Connect worldwide to the Microchip BBS using either Trademarks: The Microchip name, logo, PIC, PICSTART,
the Internet or the CompuServe communications net- PICMASTER, and are registered trademarks of Microchip
work. Technology Incorporated in the U.S.A. and other coun-
tries. FlexROM, MPLAB, PRO MATE, and fuzzyLAB, are
Internet: trademarks and SQTP is a service mark of Microchip in
You can telnet or ftp to the Microchip BBS at the the U.S.A.
address: fuzzyTECH is a registered trademark of Inform Software
mchipbbs.microchip.com Corporation. IBM, IBM PC-AT are registered trademarks
of International Business Machines Corp. Pentium is a
CompuServe Communications Network: trademark of Intel Corporation. Windows is a trademark
When using the BBS via the Compuserve Network, and MS-DOS, Microsoft Windows are registered trade-
in most cases, a local call is your only expense. marks of Microsoft Corporation. CompuServe is a regis-
tered trademark of CompuServe Incorporated.
The Microchip BBS connection does not use CompuServe
membership services, therefore you do not need All other trademarks mentioned herein are the property of
CompuServe membership to join Microchip's BBS. their respective companies.
There is no charge for connecting to the Microchip BBS.

PIC14000
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
To: Technical Publications Manager Total Pages Sent

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Application (optional):
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Device: PIC14000 Literature Number: DS40122B
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?

PIC14000
PIC14000 PRODUCT IDENTIFICATION SYSTEM
To order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed
sales offices.
PART NO. -XX X /XX XXX

Pattern: 3-Digit Pattern Code for QTP (blank otherwise)
Package: SP = 300 mil PDIP

SO = 300 mil SOIC (Gull Wing, 300 mil body)
SS = 209 mil SSOP
JW = Windowed CERDIP
Temperature - = 0C to +70C
Range: I = -40C to +85C
Frequency 04 = 4 MHz
Range: 20 = 20 MHz
Device: PIC14000: VDD range 2.7V to 6.0V

PIC14000T: VDD range 2.7V to 6.0V (Tape & Reel)
1996 Microchip Technology Inc. Preliminary DS30444C-page 149

PIC14000
NOTES:
DS30444C-page 150 Preliminary 1996 Microchip Technology Inc.

PIC14000
NOTES:
1996 Microchip Technology Inc. Preliminary DS30444C-page 151

Note the following details of the code protection feature on PICmicro MCUs.
The PICmicro family meets the specifications contained in the Microchip Data Sheet.
Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-
edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.
Information contained in this publication regarding device Trademarks

applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to The Microchip name and logo, the Microchip logo, FilterLab,
ensure that your application meets with your specifications. KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,
No representation or warranty is given and no liability is PICSTART, PRO MATE, SEEVAL and The Embedded Control
assumed by Microchip Technology Incorporated with respect Solutions Company are registered trademarks of Microchip Tech-
to the accuracy or use of such information, or infringement of nology Incorporated in the U.S.A. and other countries.
patents or other intellectual property rights arising from such
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
use or otherwise. Use of Microchips products as critical com-
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
ponents in life support systems is not authorized except with
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
express written approval by Microchip. No licenses are con-
MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode
veyed, implicitly or otherwise, under any intellectual property
and Total Endurance are trademarks of Microchip Technology
rights.
Incorporated in the U.S.A.
Serialized Quick Turn Programming (SQTP) is a service mark

of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their

respective companies.
2002, Microchip Technology Incorporated, Printed in the

U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system

certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Companys quality system processes and
procedures are QS-9000 compliant for its
PICmicro 8-bit MCUs, KEELOQ code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchips quality
system for the design and manufacture of
development systems is ISO 9001 certified.

M
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03/01/02

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PIC14000

28-Pin Programmable Mixed Signal Controller

1996 Microchip Technology Inc. Preliminary DS40122B-page 1

This document was created with FrameMaker 4 0 4

To Our Valued Customers

DS40122B-page 2 Preliminary 1996 Microchip Technology Inc.

1996 Microchip Technology Inc. Preliminary DS40122B-page 3

This document was created with FrameMaker 4 0 4

DS40122B-page 4 Preliminary 1996 Microchip Technology Inc.

2.2 One-Time-Programmable (OTP)

1996 Microchip Technology Inc. Preliminary DS40122B-page 5

This document was created with FrameMaker 4 0 4

DS40122B-page 6 Preliminary 1996 Microchip Technology Inc.

1996 Microchip Technology Inc. Preliminary DS40122B-page 7

This document was created with FrameMaker 4 0 4

13 Data Bus 8 PORTA

FSR reg PORTC

Voltage Temp Bandgap I2C

VREG SUM CDAC

Note 1: Higher order bits are from the STATUS register.

DS40122B-page 8 Preliminary 1996 Microchip Technology Inc.

Pin Pin Type

1996 Microchip Technology Inc. Preliminary DS40122B-page 9

Pin Pin Type

DS40122B-page 10 Preliminary 1996 Microchip Technology Inc.

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

1. MOVLW 55h Fetch 1 Execute 1

1996 Microchip Technology Inc. Preliminary DS40122B-page 11

DS40122B-page 12 Preliminary 1996 Microchip Technology Inc.

Reset Vector 0000h

On-chip Program 0005h

1996 Microchip Technology Inc. Preliminary DS40122B-page 13

This document was created with FrameMaker 4 0 4

* Not a physical register.

DS40122B-page 14 Preliminary 1996 Microchip Technology Inc.

TABLE 4-3: SPECIAL FUNCTION REGISTERS FOR THE PIC14000

1996 Microchip Technology Inc. Preliminary DS40122B-page 15

DS40122B-page 16 Preliminary 1996 Microchip Technology Inc.

FIGURE 4-3: STATUS REGISTER

Bit Name Function

1996 Microchip Technology Inc. Preliminary DS40122B-page 17

FIGURE 4-4: OPTION REGISTER

R/W R/W R/W R/W R/W R/W R/W R/W

T0SE: TMR0 source edge

T0CS: TMR0 clock source

Reserved. This bit should be programmed as a 1. Use of this bit as

RCPU: PORTC pull-up enable

DS40122B-page 18 Preliminary 1996 Microchip Technology Inc.

FIGURE 4-5: INTCON REGISTER

Reserved. This bit should be programmed as 0. Use of this bit

Reserved. This bit should be programmed as 0. Use of this bit

T0IF: TMR0 overflow interrupt flag

1996 Microchip Technology Inc. Preliminary DS40122B-page 19

FIGURE 4-6: PIE1 REGISTER

R/W R R R/W R/W R/W R/W R/W

2CIE Register: PIE1 W: Writable

OVFIE: A/D Counter Overflow Interrupt Enable

ADCIE: A/D Capture Interrupt Enable

RCIE: PORTC Interrupt on change Enable

I2CIE: I2C Port Interrupt Enable

PBIE: External Pushbutton Interrupt Enable

CMIE: Programmable Reference Comparator Interrupt Enable

DS40122B-page 20 Preliminary 1996 Microchip Technology Inc.

FIGURE 4-7: PIR1 REGISTER

R/W R R R/W R/W R/W R/W R/W

OVFIF: A/D counter Overflow Interrupt Flag

ADCIF: A/D Capture Interrupt Flag

RCIF: PORTC Interrupt on Change Flag

I2CIF: I2C Port Interrupt Flag

PBIF: External Pushbutton Interrupt Flag

CMIF: Programmable Reference Comparator Interrupt Flag

1996 Microchip Technology Inc. Preliminary DS40122B-page 21

FIGURE 4-8: PCON REGISTER

LVD: Low Voltage Detect Flag

POR: Power on Reset Flag