ISSN 2347 - 3983

Volume 3, No.9, September 2015

International
Ans Jose et al., Journal
International Journal of Trends
of Emerging Emerging Trends
in Engineering in3(9),
Research, Engineering
September 2015,Research
105 108
Available Online at http://www.warse.org/IJETER/static/pdf/file/ijeter04392015.pdf

Implementation of three phase five level multilevel inverter

Ans Jose Absal Nabi

M Tech student Assistant Professor
Electrical and Electronics Engineering Electrical and Electronics Engineering
Ilahia College of Engineering and Technology Ilahia College of Engineering and Technology
Ernakulam , India Ernakulam , India
e-mail: ansjose90@gmail.com e-mail: absalnabi@gmail.com

AbstractA new configuration of a three-phase five- CHB are considered the main drawbacks of these
level multilevel inverter is introduced here. Demerits topologies.
of inverter are less efficiency, high cost, and high Asymmetrical and hybrid multistage topologies
switching losses. To overcome these demerits, are becoming one of the most interested research area. In
multilevel inverters used. These inverters include an the asymmetrical configurations, the magnitudes of dc
arrangement of semiconductors and dc voltage voltage supplies are unequal[6]. These topologies reduce
sources required to generate a staircase output the cost and size of the inverter and improve the
waveform, this waveform look like a sinusoidal reliability since minimum number of power electronic
waveform. The new topology constitutes the components, capacitors, and dc supplies are used. The
conventional three-phase two-level bridge with three hybrid multistage converters consist of different
bidirectional switches. A multilevel dc link using fixed multilevel configurations with unequal dc voltage
dc voltage supply and cascaded half-bridge is supplies. With such converters, different modulation
connected in such a way that the new inverter outputs strategies and power electronic components technologies
the required output voltage levels. Here, to generate are needed. For the purpose of improving the
the appropriate switching gate signals staircase performance of the conventional single and three phase
modulation technique is used. The new topology inverters, different topologies employing different types
results in reduction of installation area and cost. The of bidirectional switches have been suggested in [7][8].
validity of the inverter and its performance are As compared to the unidirectional, bidirectional switch
verified by using MATLAB/SIMULINK and the are able to conduct the current and withstanding the
results also presented. voltage in both directions. Bidirectional switches with an
appropriate control technique can improve the
performance of multilevel inverters in terms of reducing
Key words Bidirectional switch, fundamental the number of semiconductor components, minimizing
frequency staircase modulation, multilevel inverter. the withstanding voltage and achieving the desired output
voltage with higher levels.
1. INTRODUCTION Based on this technical background, this
In Recent Years, industry has begun to demand suggests a novel topology for a three phase five-level
higher power equipment, which now reaches the multilevel inverter. The number of switching devices,
megawatt level. Controlled ac drives in the megawatt insulated-gate driver circuits, and installation area and
range are usually connected to the medium-voltage cost are significantly reduced. The magnitudes of the
network[1]-[2]. Today, it is hard to connect a single utilized dc voltage supplies have been selected in a way
power semiconductor switch directly to medium voltage that brings the high number of voltage level with an
grids. For these reasons, a new family of multilevel effective application of a fundamental frequency
inverters has emerged as the solution for working with staircase modulation technique. Simulation results are
higher voltage levels. given and explained. This paper is organized as follows:
Multilevel inverters include an array of power The outline of this paper is as follows. In Section II, the
semiconductors and voltage sources, the output of which three phase five level multilevel inverter and its
generate voltages with stepped waveforms. This operation. In Section III it includes simulations and
technology has started with the three-level converter results in Finally, Section VI presents some conclusions
followed by numerous multilevel converter topologies. based on the results from this paper.
The cascade multilevel inverter was first proposed in
1975. The common multilevel inverter configurations are 2. THE THREE PHASE FIVE LEVEL MULTILEVEL
neutral point clamped (NPC)[3], the flying capacitor INVERTER AND ITS OPERATION
(FC), and the cascaded H-bridge (CHB)[5]-[6]. The
diode-clamped inverter was first used in a three-level The new topology constitutes the conventional three-
inverter in which the mid-voltage level was defined as phase two-level bridge with three bidirectional switches.
the neutral point. Because the NPC inverter effectively It use a multilevel dc link with fixed dc voltage supply
doubles the device voltage level without requiring and cascaded half-bridge is connected in such a way that
precise voltage matching, the circuit topology prevailed the new inverter outputs the required output voltage
in the 1980s. The deviating voltage of neutral-point levels. Figure.1 shows the typical configuration of the
voltage in NPC, the unbalanced voltage in the dc link of three-phase five-level multilevel inverter. It consists of
FC, and the large number of separated dc supplies in one bidirectional switch and two diodes and two switches
in each phase. The three bidirectional switches are S1-

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S6,Da1-Da2. The other switches are named as Q1-Q6, TABLE 1 Switching State Sa and Inverter Line-to-Ground
the diodes are denoted as D1-D6. Three bidirectional Voltage Vag
switches (S1S6, Da1Dc2), two switchestwo diodes
type, are added to the conventional three-phase two-level Sa Q1 S1 S2 Q2 T1 T2 T3 T4 Vag
bridge (Q1Q6). The function of these bidirectional 4 On Off Off Off On Off On Off +4Vdc
switches is to block the higher voltage and ease current
flow to and from the midpoint (o).A multilevel dc link 3 Off On On Off On Off On Off +3Vdc
built by a single dc voltage supply with fixed magnitude
2 Off On On Off Off On On Off +2Vdc
of 4Vdc and CHB having two unequal dc voltage
supplies of Vdc and 2Vdc are connected to bridge 1 Off On On Off On Off Off On +Vdc
terminals. Moreover the CHB cells are added by the
switching of T1-T4 switches. Based on the desired 0 Off Off Off On On Off Off On 0
number of output voltage levels, a number of CHB cells
are used. Since the new inverter is designed to achieve
five voltage levels, the power circuit of the CHB makes Depending on the switching sequence given in the table
use of two series cells having two unequal dc voltage different voltage levels can be achieved. It is easier to
supplies. In each cell, the two switches are turned ON define the inverter line-to-ground voltages Vag, Vbg , and
and OFF under inverted conditions to output two Vcg in terms of switching states Sa, Sb, and Sc as,
different voltage levels.
4
=
1

where N = 5 is the maximum number of voltage levels.

The balanced load voltages can be achieved if the
proposed inverter operates on the switching states
depicted in Table 2. The inverter may have 24 different
modes within a cycle of the output waveform. According
to Table.2, it can be noticed that the bidirectional
switches operate in 18 modes. For each mode, there is no
more than one bidirectional switch in on state. As a
result, the load current commutates over one switch and
one diode (for instance: in (410), the load current Ib can
flow in S3 and Db1 or S4 and Db2). Since some
Figure1. three-phase five-level multilevel inverter insulated gate bipolar transistors (IGBTs) share the same
switching gate signals, the proposed configuration
significantly contributed in reducing the utilized gate
Operating Status Of The Switches driver circuits and system complexity.
By considering phase a, the operating status of
the switches and the inverter line-to-ground voltage Vag
are given in Table1.
TABLE 2 Switching States Sequence Of The new Inverter Within One Cycle

Sa, Period ON ON ON switches ON switches Vag Vbg Vcg

Sb, T[s] switches switches Leg c cascaded half [V] [V] [V]
Sc Leg a Leg b bridge
400 t1 Q1 Q4 Q6 T1,T4 4Vdc 0 0
410 t2 Q1 S3,S4 Q6 T1,T4 4Vdc Vdc 0
420 t3 Q1 S3,S4 Q6 T2,T3 4Vdc 2Vdc 0
430 t4 Q1 S3,S4 Q6 T1,T3 4Vdc 3Vdc 0
440 t5 Q1 Q3 Q6 T1,T3 4Vdc 4Vdc 0
340 t6 S1,S2 Q3 Q6 T1,T3 3Vdc 4Vdc 0
240 t7 S1,S2 Q3 Q6 T2,T3 2Vdc 4Vdc 0
140 t8 S1,S2 Q3 Q6 T1,T4 Vdc 4Vdc 0
040 t9 Q2 Q3 Q6 T1,T4 0 4Vdc 0
041 t10 Q2 Q3 S5,S6 T1,T4 0 4Vdc Vdc
042 t11 Q2 Q3 S5,S6 T2,T3 0 4Vdc 2Vdc
043 t12 Q2 Q3 S5,S6 T1,T3 0 4Vdc 3Vdc
044 t13 Q2 Q3 Q5 T1,T3 0 4Vdc 4Vdc
034 t14 Q2 S3,S4 Q5 T1,T3 0 3Vdc 4Vdc
024 t15 Q2 S3,S4 Q5 T2,T3 0 2Vdc 4Vdc
014 t16 Q2 S3,S4 Q5 T1,T4 0 Vdc 4Vdc

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004 t17 Q2 Q4 Q5 T1,T4 0 0 4Vdc

104 t18 S1,S2 Q4 Q5 T1,T4 Vdc 0 4Vdc
204 t19 S1,S2 Q4 Q5 T2,T3 2Vdc 0 4Vdc
304 t20 S1,S2 Q4 Q5 T1,T3 3Vdc 0 4Vdc
404 t21 Q1 Q4 Q5 T1,T3 4Vdc 0 4Vdc
403 t22 Q1 Q4 S5,S6 T1,T3 4Vdc 0 3Vdc
402 t23 Q1 Q4 S5,S6 T2,T3 4Vdc 0 2Vdc
401 t24 Q1 Q4 S5,S6 T1,T4 4Vdc 0 Vdc

3. SIMULATION RESULTS AND DISCUSSIONS system is modelled in continuous-time mode. The

figure2 shows the simulation diagram of three phase five
The new multilevel inverter is modelled using level multilevel inverter and the simulation results are
MATLAB/SimPowerSystems. The interfaces and also showed.
controllers are done using Simulink toolbox. The studied

Figure2. Simulation diagram of the 3 phase five level multilevel inverter

Here in order to get the waveforms more CHB cells. This pattern for each phase is simply hard
clearly we use Vdc as 10v. So 4Vdc is equal to 40V, 3Vdc coded. Here it use three repeating sequence blocks, this
is equal to 30V, 2Vdc is equal to 20V and V dc is equal to sequence follows the same order of Sa, Sb,Sc in table 3.2
10V. The gating signals for the switches are given by each contain 24 stages. Example if 4 appears in the
using the combinatorial logic. The Combinatorial Logic repeating sequence, that denote 4V dc is needed so Q1
block implements a standard truth table for modelling should be turned on.0 appears in the repeating sequence
programmable logic arrays (PLAs), logic circuits, that denote 0 is needed so Q2 should be turned on. 1,2,3
decision tables, and other Boolean expressions. W can appears in the repeating sequence that denote Vdc ,2Vdc ,
use this by specify a matrix that defines all possible 3 V dc is needed so S should be turned on. Other phases
block outputs as the Truth table parameter. Each row of are similar to this. Then corresponding sample time is
the matrix contains the output for a different combination calculated.
of input elements and also specify outputs for every
combination of inputs. The number of columns is the
number of block outputs.
Here the bidirectional switches are denoted as ,
S1-S2 as S, S3-S4 as S1, S5-S6 as S2. The inverter may
have 24 different modes within a cycle of the output
waveform. According to Table.2, it can be noticed that
the bidirectional switches operate in 18 modes. For each
mode, there is no more than one bidirectional switch in
onstate. In phase A the switch corresponding to 4 V dc is Figure3. gaiting signals for switches T1, T2, T3, T4.
Q1,ie, if we want to get 4 Vdc then switch on Q1 and for
0V switch on Q2. For getting the remaining The Figure.3 shows the gaiting signals for switches T1,
corresponding bidirectional switches were turned on ie, T2, T3, T4. This is from the combinatorial logic. In

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figure 4 we can see the five level voltages. The Figure5 components and overall size will cause minimisation of
shows the Waveform of line voltages Vab Vbc Vca. overall cost. The fundamental frequency staircase
modulation technique was comfortably employed and
showed high flexibility and simplicity in control.
Moreover, the new configuration can be extended to N-
level with different methods. The obtained simulation
results met the desired output. Hence, subsequent work
in the future may include an extension to higher level
with other methods.

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Figure4.Waveform of voltages Vag Vbg Vcg
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